DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/05/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8; 2, 3, 4, 5, 9, 10, 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Berger et al. U.S. Pub. No. 2022/0222771 in view of Uhrenholt et al U.S. Pub. No. 2023/0195631.
Re: claim 1, Berger teaches
1. (Currently Amended) A method, comprising: storing, by an image processor, a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame; (“Referring to Fig. 3A, a conceptual representation of an example rolling cache (or local buffer or local memory) 300 for storing pixel values of an input image...”; Berger, [0049], Fig. 3A)
Fig. 3A illustrates a rolling cache for storing pixels of an input image (frame).
(“For example memory block 304 may overlap with memory block 306 forming an overlap 322. In these cases, just the remainder of a block 306 may be written to the cache when the overlapped area 322 is already in the cache since it was loaded as part of memory block 304.”; Berger, [0057], Fig. 3A)
Fig. 3A illustrates that the rolling cache stores memory block 304 (first stripe of a first frame), which has an overlapping region 322 (first portion of a first stripe of a first frame in a cache) with memory block 306 (second stripe). The overlapping area 322 (first portion of a first stripe of the first frame in a cache) overlaps a portion of memory block 306 (the first portion of the first stripe overlapping a second portion of a second stripe of the first frame) of the frame.
reading, by the image processor, a third portion of the second stripe from a memory; (“When an input image block is requested by the image processing application, the system may check whether a cache hit occurs for that block. This cache hit search also acts to check for block overlaps. Thus, if a hit occurs on a previously stored block, an overlap is present and the data already on the cache is not retrieved from external memory again. Instead, just the miss or non-overlapping portion of the requested input image block is read from external memory and written to the rolling cache.”; Berger, [0071])
If a cache hit occurs on a previously stored block, an overlap (from the first stripe) is present and the data is already in the cache and is not retrieved from external memory. Instead, just the non-overlapping portion (third portion of the second stripe from a memory) of the requested input image block is read (reading, by the image processor) from external memory and written to the rolling cache.
reading, by the image processor, the first portion of the first stripe from the cache in accordance with a read with evict command associated with the first portion of the first stripe; (“For example memory block 304 may overlap with memory block 306 forming an overlap 322. In these cases, just the remainder of a block 306 may be written to the cache when the overlapped area 322 is already in the cache since it was loaded as part of memory block 304... When an input image block is requested by the image processing application, the system may check whether a cache hit occurs for that block. This cache hit search also acts to check for block overlaps. Thus, if a hit occurs on a previously stored block, an overlap is present and the data already on the cache is not retrieved from external memory again. Instead, just the miss or non-overlapping portion of the requested input image block is read from external memory and written to the rolling cache.”; Berger, [0057], [0071], Fig. 3A)
If a cache hit occurs on a previously stored block (first stripe, which includes the first portion of the first stripe), an overlap (from the first stripe) is present and the data is already in the cache and is not retrieved from external memory. Thus, the previously stored block is read from the rolling cache.
(“... memory block 304 may not be discarded (or evicted) until the space on the tiles memory block 304 occupies is needed for a new memory block. However, once processing is complete for memory block 304 and checked to see if it is needed to process any adjacent blocks, the memory block may be marked as checked and released, and therefore its tiles are available for overwriting.”; Berger, [0057])
Fig. 3A illustrates, for example, overlapping memory blocks 304 and 306 (first stripe and second stripe). Memory block 304 includes overlapped area 322 (first portion of the first stripe from the cache). Once processing is complete for memory block 304 (reading the first portion of the first stripe from the cache), memory block 304 is marked as checked and released, but it is only discarded (evicted) when the space that memory block 304 occupies is needed for a new memory block. Thus, when the space that memory block 304 occupies is to be updated with a new memory block the current memory block 304 is invalidated. Also, when the processing is complete for memory block 304 (thus the reading is complete), and the space that memory block 304 occupies is to be updated, this is considered to be read with evict command. The overlapping portion is read from the cache, then the same overlapping portion is discarded (evicted) from the cache (read with evict).
invalidating, by the image processor in accordance with the read with evict command, the first portion of the first stripe in the cache after reading the first portion of the first stripe from the cache; (“... memory block 304 may not be discarded (or evicted) until the space on the tiles memory block 304 occupies is needed for a new memory block. However, once processing is complete for memory block 304 and checked to see if it is needed to process any adjacent blocks, the memory block may be marked as checked and released, and therefore its tiles are available for overwriting.”; Berger, [0057])
Fig. 3A illustrates, for example, overlapping memory blocks 304 and 306 (first stripe and second stripe). Memory block 304 includes overlapped area 322 (first portion of the first stripe in the cache). Once processing is complete for memory block 304 (after reading the first portion of the first stripe from the cache), memory block 304 is marked as checked and released, but it is only discarded (evicted) when the space that memory block 304 occupies is needed for a new memory block. Thus, when the space that memory block 304 occupies is to be updated with a new memory block the current memory block 304 is invalidated. Berger does not explicitly state that the updating is equivalent to invalidating, however Uhrenholt teaches this limitation.
(“An update to an entry in the first cache that triggers updates in the second... cache can comprise any suitable and desirable update to the cache entry in the first cache. It... comprises... the processor writing updated data to the entry in the first cache.”; Uhrenholt, [0057])
When an entry in the first cache is updated, it triggers an update in the second cache.
(“The updating (e.g., invalidating) of the entries in the second cache... could be triggered immediately to the entry in the first cache being updated.”; Uhrenholt, [0060])
The updating (invalidating) of entries in the second cache are triggered by updating the entry in the first cache. The overlapping portion is read from the cache, then the same overlapping portion is discarded (evicted) from the cache (read with evict). Uhrenholt is combined with Berger such that when the current memory block 304, of Berger, is updated with a new memory block, the current memory block 304 is invalidated. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Berger by adding the feature of invalidating, by the image processor, in accordance with the read with evict command, the first portion of the first stripe in the cache after reading the first portion of the first stripe from the cache, in order to facilitate cache coherence by an updating a cache entry in once cache triggering invalidation of cache entries in another cache, as taught by Uhrenholt ([0028]).
Berger teaches and processing, by the image processor, the second stripe using the first portion of the first stripe read from the cache and the third portion of the second stripe read from the memory. (“For example, memory block 304 may overlap with memory bock 306 forming an overlap 322. In these cases, just the remainder of a block 306 may be written to the cache when the overlapped area 322 is already in the cache since it was loaded as part of memory block 304.”; Berger, [0057], Fig. 3A)
Fig. 3A illustrates, for example, overlapping memory block 304 and 306 (first stripe and second stripe). Just the remainder of block 306 (third portion of the second stripe) is written to the cache (read into the cache from memory) when the overlapped area 322 is already in the cache since it was loaded as part of memory block 304. Thus, processing the memory block 306 includes the overlapped portion 322 (first portion of the first stripe), which is already in the cache and the remainder of block 306 (third portion of the second stripe), which is loaded from memory (read from memory).
Claim 8 is an apparatus analogous to the method of claim 1, is similar in scope and is rejected under the same rationale. Claim 8 has additional limitations. Re: claim 8, Berger teaches
8. (Currently Amended) An apparatus, comprising: a memory storing processor-readable code; and at least one processor coupled to the memory, the at least one processor configured to execute the processor-readable code to cause the at least one processor to perform operations including: (“The material disclosed herein also may be implemented as instructions stored on a machine-readable medium or memory, which may be read and executed by one or more processors.”; Berger, [0026])
A machine readable medium or memory stores instructions (processor-readable code), which is executed by one or more processors (at least one processor coupled to the memory, the at least one processor configured to execute the processor-readable code to cause the at least one processor to perform operations including).
Re: claims 2 and 9 (which are rejected under the same rationale), Berger and Uhrenholt teach
2. (Original) The method of claim 1, further comprising: reading, by the image processor, the first stripe of the first frame from the memory before storing the first portion of the first stripe in the cache. (“For example, memory block 304 may overlap with memory block 306 forming an overlap 322. In these cases, just the remainder of a block 306 may be written to the cache when the overlapped area 322 is already in the cache since it was loaded as part of memory block 304.”; Berger, [0057], Fig. 3A)
Fig. 3A illustrates that rolling cache stores the memory block 304 (first stripe of the first frame) that has already been loaded from external memory.
(“The image processing application 410 may have an input coordinate calculation unit 412 to determine which input image block or blocks to retrieve in order to generate the image data for an output pixel location. The system 400 then determines if the data is not already in the rolling cache 414. If not, the desired input image blocks are retrieved from the external memory 402 and placed in the cache for transmission to the image processing application.”; Berger, [0061], Fig. 4)
Fig. 4 illustrates an input coordinate calculation unit that determines which input image block, such as memory block 304 (first strip of the first frame), to retrieve from external memory. The system determines whether memory block 304 is in the rolling cache. If it is not in the rolling cache, memory block 304 is retrieved from the external memory (reading, by the image processor, the first stripe of the first frame from the memory before storing the first portion of the first stripe in the cache) and placed (stored) in the cache.
Re: claims 3 and 10 (which are rejected under the same rationale), Berger and Uhrenholt teach
3. (Original) The method of claim 1, wherein the first portion of the first stripe comprises a first tile of the first stripe, and wherein the second portion of the second stripe comprises a second tile of the second stripe. (“Cache or local memory 300 may be conceptually arranged in rows and columns of tiles 301 separated by tile boundaries 330 to form a 2D map 302 that corresponds to, or represents, the 2D pixel space of an input image... For example, memory block 304 may overlap with memory block 306 forming an overlap 322. In these cases, just the remainder of a block 306 may be written to the cache when the overlapped area 322 is already in the cache since it was loaded a spart of memory block 304.”; Berger, [0049], [0057], Fig. 3A)
Fig. 3A illustrates, for example, memory block 304 (first stripe) and memory block 306 (second stripe), which share overlapping portion 322 (first portion of the first stripe and the second portion of the second stripe). The overlapping portion 322 includes, for example, tiles from column 312 (which includes a first tile of the first stripe) and the same overlapping portion 322 of memory block 306 (second portion of the second stripe) includes tiles from column 313 (which includes a second tile of the second stripe).
Re: claims 4 and 11 (which are rejected under the same rationale), Berger and Uhrenholt teach
4. (Original) The method of claim 1, wherein the third portion of the second stripe does not overlap the second portion of the second stripe. (“For example memory block 304 may overlap with memory block 306 forming an overlap 322. In these cases, just the remainder of a block 306 may be written to the cache when the overlapped area 322 is already in the cache since it was loaded as part of memory block 304.”; Berger, [0057], Fig. 3A) Fig. 3A illustrates that memory block 306 (second stripe) has an overlapping portion 322 (second portion of the second stripe) and a non-overlapping portion (third portion of the second stripe).
Re: claims 5 and 12 (which are rejected under the same rationale), Berger and Uhrenholt teach
5. (Original) The method of claim 1, wherein storing the first portion of the first stripe in the cache comprises: generating, by the image processor, a command to allocate a first area of the cache for storage of the first portion of the first stripe. (“Process 700 may include “determine if there is a cache hit on a previous overlapping block or a miss” 704. This operation may be performed by the cache hit unit 609 of system 600 (Fig. 6A) and may preliminarily include calculating cache virtual pixel addresses for the input image pixel coordinates of the current block (or current memory block). This may include the use of a valid table that lists the tiles already being used by other blocks. By one form, the input pixel locations are assigned to tiles that are not listed on the valid, or are listed as free on the valid table.”; Berger, [0108])
The process generates a command to determine if there is a cache hit or miss on a previous overlapping memory block. This operation includes, for a cache miss, calculating cache virtual pixel addresses for the input image pixel coordinates of the current memory block, such as memory block 304 (first stripe). This includes the use of a valid table that lists the tiles in the rolling cache that are being used. Then, input pixel locations for the current memory block 304 (which includes a first portion of the first stripe) are assigned (allocated) to tiles in the rolling cache that are listed as free on the valid table (generating, by the image processor, a command to allocate a first area of the cache for storage of the first portion of the first stripe).
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Berger in view of Uhrenholt as applied to claims 1 and 8 above, and further in view of Marchya et al. U.S. Pub. No. 2021/0385493.
Re: claims 6 and 13 (which are rejected under the same rationale), Berger and Uhrenholt are silent regarding, a format of the first frame is a universal bandwidth compression/decompression (UBWC) tiled format, however, Marchya teaches
6. (Original) The method of claim 1, wherein a format of the first frame is a universal bandwidth compression/decompression (UBWC) tiled format. (“The determination component 198 can also be configured to configure a plurality of tile rows in the one or more layers in the frame. The determination component 198 can also be configured to calculate a bandwidth compression ratio (CR) for each of a plurality of tile rows in one or more layers in a frame, where each of the one or more layers may be associated the one or more regions in the frame... Some aspects of bandwidth compression, e.g., universal bandwidth compression (UBWC), can compress pixels which may help reduce the total bytes fetched from DDR bandwidth.”; Marchya, [0032], [0040], Fig. 1)
Fig. 1 illustrates a determination component that calculates the bandwidth compression ratio for each of the plurality of tile rows in a frame, where the bandwidth compression is universal bandwidth compression (UBWC). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Berger by adding the feature of a format of the first frame is a universal bandwidth compression/decompression (UBWC) tiled format, in order to optimize a display bandwidth vote or request such that, the power consumption of a display can be optimized, as taught by Marchya ([0050]).
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Berger in view of Uhrenholt as applied to claims 1 and 8 above, and further in view of Maeda U.S. Pub. No. 2008/0256296.
Re: claims 7 and 14 (which are rejected under the same rationale), Berger and Uhrenholt teach
7. (Currently Amended) The method of claim 1, wherein the read with evict command includes a cache allocation bit set to a value indicating cache space storing the first portion of the first stripe should be deallocated. (“When data is read into a cache, the coherency information is... updated to indicate that the read in data is now cached by that cache. Correspondingly, when data is evicted from a cache, the coherency information is... updated to indicate that the evicted data is not cached by that cache.”; Uhrenholt, [0036])
When data is read into a cache, the coherency information (allocation information) is updated to indicate that this data is cached. When data is evicted from the cache, the coherency information is updated to indicate that this data is no longer cached. Berger and Uhrenholt are silent regarding the coherency information is a bit, however, Maeda teaches this imitation.
(“Each of the tags is configured by a tag address having a 16-bit width, a valid flag having a 1-bit width, and a dirty flag having a 1-bit width.”; Maeda, [0036], Fig. 4)
Fig. 4 illustrates cache lines stored in a tag array, where the valid flag and the dirty flag have a 1-bit width (cache allocation bit).
(“The valid flag indicates whether the data stored in the cache line of the corresponding data array 20a are valid “1” or invalid “0”. In the case in which the valid flag is “1” and the dirty flag is “1”, it is indicated that write is performed for the data stored in the cache line of the corresponding data array 20a.”; Maeda, [0037])
The valid flag of “1” indicates valid data stored in the cache and the dirty flag of “1” indicates that a write is to be performed to overwrite (thus discarding or evicting the current data) this valid and dirty data in the cache.
(“In Fig. 4, the contents stored in the “tag 1-0” indicate that data stored in a “cache line 1-0” are valid (the valid flag of “1”) and overwrite is performed over the data (the dirty flag of “1”), and the tag address is “0x10F0”. ”; Maeda, [0038])
Fig. 4 illustrates, for example, that for tag 1-0 the valid flag is 1 and the dirty flag is 1 (cache allocation bit). The dirty flag indicates that data stored in cache line 1-0 are to be overwritten (evicted/deallocated). Maeda is combined with Berger and Uhrenholt such that the information indicating the eviction of Uhrenholt is the 1-bit dirty flag of Maeda. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the method of Berger by adding the feature of the read with evict command includes a cache allocation bit set to a value indicating cache space storing the first portion of the first stripe should be deallocated, in order to increase the speed of the data access process, as taught by Maeda ([0042]).
Response to Arguments
Applicant's arguments filed 3/05/2026 have been fully considered but they are not persuasive. Applicant argues regarding claim 1:
“Berger fails to disclose “reading the first portion of the first stripe from the cache in accordance with a read with evict command associated with the first portion of the first stripe” and “invalidating, by the image processor in accordance with the read with evict command, the first portion of the first stripe in the cache after reading the first portion of the first stripe from the cache” because Berger does not disclose a read with evict command in accordance with which an image processor reads and invalidates a first portion of a first stripe. For example, in discussing dependent claim 7 at page 17, the Office Action states that “when the processing is complete for memory block 304 (thus the reading is complete), and the space that memory block 304 occupies is to be updates, this is considered to be read with evict command.” However, no read with evict command is disclosed in Berger... Contrary to the Office’s assertion at page 17 of the Office Action, this disclosure of Berger does not include a disclosure of a read with evict command. In fact, this disclosure of Berger does not discuss commands for causing information to be read from the cache and evicted. In the Advisory Action, the Office notes that “when the processing is complete for memory block 304 (thus the reading is compete), and the space that memory block 304 occupies is to be updated, that is considered to be read with evict command.” However, Berger’s operations including processing of stored data and updating of space that memory block 304 occupies are not disclosed as being performed in accordance with the same read with evict command. Instead, Berger discloses, as outlined above, that “memory block 304 may not be discarded (or evicted) until the space on the tiles memory block 304 occupies is needed for a new memory block.” No single command in accordance with which both operations are performed is disclosed in Berger. Furthermore, the disclosure of Berger does not include a disclosure of reading and invalidating a first portion of a first stripe in a cache in accordance with a read with evict command. Uhrenholt fails to remedy this deficiency. Accordingly, claim 1, as amended is novel over Berger and nonobvious over Berger in view of Uhrenholt. Claim 8 is amended similarly to claim 1 and is novel and nonobvious for at least the same reasons. Accordingly, Applicant respectfully requests that the rejection of claims 1 and 8 as anticipated by Berger are withdrawn.“
Examiner disagrees. Regarding Applicant’s argument that the Berger does not disclosed a read with evict command. The Specification in para [0081], discloses,
“For example, the processor may read the portion 310, 312 of the first stripe 302 that overlaps with the second stripe 304 from the cache for processing of the second stripe by issuing a read with evict command to read the overlapping portion 310, 312 from the cache and invalidate, such as evict, erase or otherwise forget, the stored overlapping portion 310, 312 from the cache.”
And, the Specification also discloses in para [0088],
“In some embodiments, after the image processor reads the first portion of the first stripe from the cache, the image processor may invalidate the first portion of the first stripe in the cache.”
The Specification discloses that the read with evict command is a two-step process performed by the image processor, where the overlapping portion is read from the cache, then the same overlapping portion is invalidated or evicted or erased or forgotten from the cache. Berger teaches in para [0057],
“For example, memory block 304 may overlap with memory block 306 forming an overlap 322. In these cases, just the remainder of a block 305 maybe written to the cache when the overlapped area 322 is already in the cache since it was loaded as part of memory block 304... memory block 304 may not be discarded (or evicted) until the space on the tiles memory block 304 occupies is needed for a new memory block. However, once processing is complete for memory block 304 and checked to see if it is needed to process any adjacent blocks, the memory block may be marked as checked and released, and therefore its tiles are available for overwriting.”
Fig. 3A illustrates, for example, overlapping memory blocks 304 and 306 (first stripe and second stripe). Memory block 304 includes overlapped area 322 (first portion of the first stripe in the cache). Once processing is complete for memory block 304 (after reading the first portion of the first stripe from the cache), memory block 304 is marked as checked and released, but it is only discarded (evicted) when the space that memory block 304 occupies is needed for a new memory block. Thus, when the space that memory block 304 occupies is to be updated with a new memory block the current memory block 304 is invalidated. Therefore, Berger also teaches an equivalent two-step process performed by the image processor. The overlapping portion is read from the cache, then the same overlapping portion is discarded (evicted) from the cache. The rejections for claims 8 and 8 are maintained.
Applicant's arguments filed 3/05/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claims 2-5 and 7 depend either directly or indirectly from independent claim 1 and claims 9-12 and 14 depend either directly or indirectly from independent claim 8, and therefore inherit every element of the claim(s) form which they depend. Accordingly, dependent claims 2-5, 7, 9-12 and 14 are patentable at least for the reasons set forth with respect to the independent claims. Further, these claims set forth additional elements making them patentable in their own right. For example, claim 7, as amended, is further novel over Berger because Berger does not disclose that “the read with evict command includes a cache allocations bit set to a value indicating cache space storing the first portion of the first stripe should be deallocated. For example, there is no disclosure in Berger of the recited cache allocation bit. Accordingly, claim 7 is further novel over Berger. Claim 14 is similarly amended and is novel for at least the same reasons.”
Examiner disagrees. Claims 1, 8, and claims 2-5, 7, 9-12 and 14 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 3/05/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claim 6 depends either directly or indirectly from independent claim 1 and claim 13 depends either directly or indirectly from independent claim 8, and therefore, inherit every element of the claim(s) from which they depend. Accordingly, dependent claims 6 and 13 are patentable at least for the reasons set forth with respect to the independent claims. Further, these claims set forth additional elements making them patentable in their own right. Therefore, Applicant respectfully requests that the rejections of dependent claims 6 and 13 also be withdrawn.”
Examiner disagrees. Claims 1, 8, 6 and 13 have been rejected. Please see the corresponding rejections.
Applicant's arguments filed 3/05/2026 have been fully considered but they are not persuasive. Applicant argues:
“Claim 7 depends either directly or indirectly from independent claim 1, and claim 14 depends either directly or indirectly from independent claim 8. Therefore claims 7 and 14 inherit every element of the claim(s) from which they depend. Accordingly, dependent claims 7 and 14 are patentable at least for the reasons set forth with respect to the independent claims. Uhrenholt does not cure the deficiencies with respect to Berger, as discussed herein, with respect to either the features of claims 1 and 8 or the features of claims 7 and 14. For example, claims 7 and 14 set forth additional elements making them patentable in their own right, as discussed herein, and Uhrenholt fails to remedy the deficiencies of Berger with respect to claims 7 and 14. Therefore, Applicant respectfully requests that the rejections of dependent claims 6 and 13 also be withdrawn.”
Examiner disagrees. Uhrenholt and Maeda teach this limitation. Uhrenholt teaches that when data is read into a cache, the coherency information (allocation information) is updated to indicate that this data is cached. When data is evicted from the cache, the coherency information is updated to indicate that this data is no longer cached (Uhrenholt, [0036]). Maeda teaches that this information to evict data from the cache is a bit (allocation bit). Meada teaches Fig. 4 illustrates cache lines stored in a tag array, where the valid flag and the dirty flag have a 1-bit width (cache allocation bit). ([0036], Fig. 4). The valid flag of “1” indicates valid data stored in the cache and the dirty flag of “1” indicates that a write is to be performed to overwrite (thus discarding or evicting the current data) this valid and dirty data in the cache. (Maeda, [0037]). Fig. 4 illustrates, for example, that for tag 1-0 the valid flag is 1 and the dirty flag is 1 (cache allocation bit). The dirty flag indicates that data stored in cache line 1-0 are to be overwritten (evicted/deallocated). (Maeda, [0038]).
Conclusion
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/Donna J. Ricks/Examiner, Art Unit 2612
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618