Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restriction
This action is in response to applicant’s response filed on 01/27/2026. Applicant’s election of claims 1-10 in the reply filed on 01/27/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). In view of the applicant's response filed on 01/27/2026, claims 11-30 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-10 are pending.
The IDS has been considered by the examiner.
The specification and drawings have been accepted by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao (US 20160182000) and further in view of Lovlekar (US 20220240079).
Referring to claim 1, Liao discloses an apparatus (FIG. 3, Apparatus, and Par. 4, “an apparatus includes a first amplifier stage configured to amplify an input signal at an input terminal to generate a first amplified signal.”), comprising:
a radio frequency (RF) transceiver (FIG. 1 and 3, the amplification circuit 112 provides amplification for signals received by a receiver in the wireless device 110. Note that the wireless device 110 includes transceiver antenna to receive and transmit signals) comprising a semiconductor die (Par. 79, “amplification circuit may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS)”, note that semiconductor die is just a small piece of semiconductor that the transistors are incorporated into),
the RF transceiver comprising:
an input port for receiving a radio frequency (RF) signal (Par. 27, “single-ended RF input signal is received at an input terminal 316 that is connected to capacitors 322 and 324. The capacitor 322 is connected to node 318 that is further connected to a source terminal of the transistor 308.” Note that the RF input reads on input port and see figure 3 and Par. .54, “the RF input goes to a high level, the transistor 308 can be enabled by the bias signal VBP1 and the transistor 314 is disabled. When the transistor 308 is enabled by the RF input and the bias signal VBP1, current I flows through transistor 308 and is diverted through two signal paths”); and
a low noise amplifier (LNA) coupled to the input port (Par. 5, “a low noise amplifier (LNA) to amplify received RF signals prior to demodulation. Impedance matching, isolation, and linearity are the major concerns for LNAs in receivers”. Note that the LNA is attached to the input port and amplifies the received signals) and a first output port and a second output port (Par. 27 and 29, and 33, “complementary common gate amplifier stage 302 outputs a non-inverted first amplified output signal (RF output) from the node 348.”),
the LNA configured to output the RF signal with a first gain as a first amplified RF signal at the first output port (FIG. 3-5, Par. 31, 35 and 37“receive the first amplified output signal and a second terminal of the first winding connected to the node 350 to receive the second amplified output signa”, first gain, first output port and second output port) and to output the RF signal with a different, second gain as a second amplified RF signal at the second output port (FIG. 3 and 4, and Par. 55, “the gain is increased when more transistors are enabled to divert more current to the output and fewer transistors are enabled to divert less current to the capacitor 762. The gain is decreased when fewer transistors are enabled to divert less current to the output and more transistors are enabled to divert more current to the capacitor 762”, note that the gain of each amplifier increases the gain at the output of the amplifier individually, thus, different second gain from the second amplifier).
Liao is silent on a first carrier corresponding to a first subscriber identity module (SIM) and a second carrier corresponding to a second subscriber identity module (SIM).
In an analogous art, Lovlekar discloses first carrier corresponding to a first subscriber identity module (SIM) and a second carrier corresponding to a second subscriber identity module (SIM) (Par. 230, “The first SIM may be associated with (e.g., subscribed to) a first carrier network. The second SIM may be associated with a second carrier (e.g., subscribed to) a second carrier network. UE 1000 may also include a first transceiver (TxRx1) 1010 and a second transceiver (TxRx2) 1012”).
It would have been obvious to one skilled in the art, before the effective filing date of the claimed invention, to modify the invention of Liao by incorporating the teachings of Lovlekar so that both different SIM are used for different carriers, for the purpose of simplifying communication resources and account setting. Further, this an example of use of known technique to improve similar devices, methods or products in the same way. MPEP 2143.
Referring to claim 2, the combination of Liao/Lovlekar discloses the apparatus of claim 1, wherein: the LNA comprises a plurality of slices, and the apparatus further comprises: a controller configured to control the LNA to provide the first output port with the first gain and the second output port with the second gain by controlling the plurality of slices (Liao, Par. 39 and 40, “The current diverter 702 includes two groups of PMOS transistors and two groups of NMOS transistors. The first group of PMOS transistors includes PMOS transistors 706, 708, and 710. The transistors 706, 708, and 710 have source terminals connected to the drain terminal of transistor 308 and have drain terminals connected to node 756, which is also connected to a first terminal of a resistor 758 (e.g., 1-5 kohms). The (non-inverted) output signal RF_OUTP is output from the node 756. The transistors 706, 708, and 710 have gate terminals connected to receive control signals D1, D2, and D3, respectively, which are generated by the controller”).
Referring to claim 3, the combination of Liao/Lovlekar discloses apparatus of claim 1, further comprising: a controller configured to control the LNA to provide the first output port with the first gain and the second output port with the second gain by supplying a different bias to different parts of the LNA corresponding to the first output port and the second output port (Liao, Par. 27, 31, “PMOS side of amplifier stage 302 are designed symmetrically to have better IIP2 performance. The complementary common gate amplifier stage 302 outputs a non-inverted first amplified output signal (RF output) from the node 348”, “control the amplifier to provide the first output port with the first gain and the second output port with the second gain”).
Referring to claim 4, the combination of Liao/Lovlekar discloses the apparatus of claim 1, wherein: the LNA comprises a plurality of attenuators, and the apparatus further comprises: a controller configured to control the LNA to provide the first output port with the first gain and the second output port with the second gain by controlling the plurality of attenuators (Liao, FIG. 3-5 and Par. 23, 27, 29 and 31, “the amplification circuit 112 provides amplification for signals received by a receiver in the wireless device 110. The amplification circuit 112 is designed to utilize less power and circuit area than conventional amplifiers while providing adjustable gain and constant input impedance”, “capacitor 326 and to a voltage supply (VDD) through a first winding of transformer 330. The node 320 is connected to the signal ground through capacitor 328 and through a seconding winding of the transformer 330. The transformer 330 comprises windings in a ratio of (1:1) since transistor 308 and transistor 314 are also sized to deliver the same gm. For example, the NMOS side and the PMOS side of amplifier stage 302 are designed symmetrically to have better IIP2 performance. The complementary common gate amplifier stage 302 outputs a non-inverted first amplified output signal”, note that the transistors are the attenuators and they control the LNA to provide the first output port with the first gain and the second output port with the second gain).
Referring to claim 5, the combination of Liao/Lovlekar discloses the apparatus of apparatus of claim 1, wherein: the LNA comprises a plurality of stages of amplifiers, and the apparatus further comprises: a controller configured to control the LNA to provide the first output port with the first gain and the second output port with the second gain by controlling the plurality of stages of amplifiers (Liao, FIG. 3-4 and Par. 27, 30, 39, “the dashed line 768 separates the complementary common gate amplifier stage 302 and the complementary common source amplifier stage 304. The complementary common gate amplifier stage 302 is expanded to include a current diverter 702 and the complementary common source amplifier stage 304”).
Referring to claim 6, the combination of Liao/Lovlekar discloses apparatus of The apparatus of claim 1, further comprising: a first RF processing chain coupled to the first output port for processing the first carrier, the first RF processing chain comprising a first baseband filter configured to provide a third gain to the first amplified RF signal; and a second RF processing chain coupled to the second output port for processing the second carrier, the second RF processing chain comprising a second baseband filter to provide a fourth gain to the second amplified RF signal (Liao, FIG. 3-7, and Par. 39, 40 and 45, “the transistors 310, 312 of the complementary common gate amplifier stage 302 are replaced with the current diverter 702. The current diverter 702 includes two groups of PMOS transistors and two groups of NMOS transistors. The first group of PMOS transistors includes PMOS transistors 706, 708, and 710. The transistors 706, 708, and 710 have source terminals connected to the drain terminal of transistor 308 and have drain terminals connected to node 756, which is also connected to a first terminal of a resistor 758 (e.g., 1-5 kohms).”).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao (US 20160182000) and further in view of Lovlekar (US 20220240079) and further in view of Deng (US 20240356495) and further in view of Zheng (US 10,608691).
Referring to claim 7, the combination of Liao/Lovlekar discloses the apparatus of claim 6.
The above combination is not relied on for disclosing the limitation, “input port is coupled to a RF front end (RFFE)”.
In an analogous art, Deng discloses input port is coupled to a RF front end (RFFE) (FIG. 5A-5B and Par. 54, “The RF power amplifier circuit 500A is configured to receive an input RF signal from the input port 501 (which can be coupled to an input port of the RF front end circuitry 218), amplify the RF signal, and output the amplified RF signal via the output port 570”).
It would have been obvious to one skilled in the art, before the effective filing date of the claimed invention, to modify the above combination by incorporating the teachings of Deng in the format claimed, for the purpose of isolating DC bias voltages between stages and matching impedances for maximum power transfer. Further, this an example of use of known technique to improve similar devices, methods or products in the same way. MPEP 2143.
The combination of Liao/Lovlekar/Deng is not relied on for the limitation, RF front end (RFFE) for receiving the RF signal comprising the first carrier and the second carrier through a single signal path.
In an analogous art, Zheng discloses RF front end (RFFE) for receiving the RF signal comprising the first carrier and the second carrier through a single signal path (FIG. 3, Col. 5, lines 59-67, “front-end circuits can utilize multiple carrier frequencies”, “the front-end circuit 310 generates or processes signals associated with a first carrier frequency 314 and a second carrier frequency 316”. Note that figure 3 shows front-end circuit 310 receives RF signals that include RF signals 314 and RF signals 316 corresponding to first carrier frequency and second carrier frequency respectively, which reads on the claim language).
It would have been obvious to one skilled in the art, before the effective filing date of the claimed invention, to modify the above combination by incorporating the teachings Zheng in the format claimed, for the purpose of supporting multi-band/multi-carrier systems and enabling carrier aggregation and improving signal diversity. Further, this an example of use of known technique to improve similar devices, methods or products in the same way. MPEP 2143.
Allowable Subject Matter
Claim(s) 8-10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the examiner’s statement of reasons for allowance:
Regarding claim 8:
The prior art fails to disclose or suggest the limitations “wherein: a RF transceiver comprises the LNA, the first RF processing chain, and the second RF processing chain, and the apparatus further comprising: a first SIM interface for receiving a first SIM; a second SIM interface for receiving a second SIM; and a baseband modem processor coupled to the first RF processing chain and to the second RF processing chain and coupled to the first SIM interface and to the second SIM interface, the baseband modem processor configured to process the first amplified RF signal based on the first SIM and to process the second amplified RF signal based on the second SIM”, as recited in claim 8 along with the limitations of the intermediate and/or base claims.
Regarding claims 9-10:
Claims 9-10 depend on allowable subject matter of claims 8, thus, they are allowable for being dependent upon allowable claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED A CASCA whose telephone number is (571)272-7918. The examiner can normally be reached on Monday through Friday from 9 to 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kathy Wang-Hurst, can be reached at (571) 270-5371. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/FRED A CASCA/Primary Examiner, Art Unit 2644