DETAILED ACTION
This action is in response to the 01/29/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim(s) 1 and 14 is/are objected to because of the following informalities:
Claim 1, line 7 recites “the first current”. Said limitation lacks antecedent basis.
Claim 14, line 7 recites “the first current”. Said limitation lacks antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21 – 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 21 and 22 recite “wherein the switch voltage has an amplitude of zero during the ringing of the primary voltage prior to the primary switch being deactivated.” The disclosure, however, states in paragraph 066 “In response to the switch voltage VSW decreasing at the trough of the ringing of the primary voltage VPRI to zero at the time T3, the input controller 610 activates the primary switch NP, as described above.” There’s no support in the original specifications to the claimed “wherein the switch voltage has an amplitude of zero during the ringing of the primary voltage prior to the primary switch being deactivated”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 23 and 25 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Patent No. 11,588,411; (hereinafter Nayaknur).
Regarding claim 23, Nayaknur [e.g. Figs. 1A] discloses a switch [e.g. S1, 112] coupled to primary side terminals [e.g. lower terminal of primary winding and ground]; and a controller [e.g. 128] coupled to the switch and configurable to: activate the switch responsive to a voltage across the switch is zero [e.g. col. 18, line 66 – col. 19, line 3 recite “After a delay time, the power switch S1 112 is turned ON at time t12. As shown, the delay time is the duration between time t11 and time t12. The duration of the delay time may be selected such that the voltage across the power switch S1 112 falls to zero”]; and deactivate the switch responsive to a current across the switch exceeding a threshold [e.g. col. 7, lines 31 – 33 recite “The first controller 128 is coupled to receive a current sense signal ISNS 146 representative of the drain current ID 113 of the power switch S1 112”. Col. 7, lines 54 – 58 recite “the first controller 128 outputs the first drive signal DR 144 to turn OFF the power switch S1 112 when the drain current ID 113 provided by the current sense signal ISNS 146 reaches a current limit.” Examiner note: the primary switch current corresponds to the primary winding current].
Regarding claim 25, Nayaknur [e.g. Figs. 1A] discloses further comprising a flyback converter [e.g. 100] including the switch [e.g. S1 112] and the controller [e.g. 128].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 2 and 14 – 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2020/0280263; (hereinafter Lin) in view of Nayaknur.
Regarding claim 1, Lin [e.g. Figs. 2A-3] discloses an integrated circuit (IC) comprising: a switching stage comprising a primary switch [e.g. S1] and an input controller [e.g. 80], the input controller being configurable to:activate the primary switch to conduct a primary current [e.g. Ip] in a primary winding [e.g. W1] of a transformer [e.g. 10] in response to a switch voltage at a switching terminal having an amplitude of zero [e.g. Fig. 2A; paragraph 037 recites “the circulation current Ip at the primary side winding W1 can discharge the parasitic capacitor Cp of the primary side switch S1 substantially to 0V, and the charges of the parasitic capacitor Cp will be transferred to an input capacitor CI. Consequently, the primary side switch S1 can achieve zero voltage switching (ZVS) when the primary side switch S1 is turned ON in the next cycle and further cycles”]; and deactivate the primary switch to provide a secondary current [e.g. Fig. 2A; ISR] in a secondary winding [e.g. W2] of the transformer [e.g. Fig.3 with respect to S1C and S2C; paragraph 036 recites “When the primary side switch S1 is turned ON and then OFF (as shown by the timing point t1 in FIG. 3), the SR-control pulse PSR controls the synchronous rectifier switch S2 to be ON for an SR time period T_SR, to perform secondary side synchronous rectification. The SR time period T_SR is substantially synchronous with the conduction time of an induction current of the secondary side winding W2. In other words, the SR time period T_SR begins at a timing point (i.e., the timing point t1) when the secondary side winding W2 starts generating the induction current due to energy transferred from the primary side winding W1 to the secondary side winding W2, and the SR time period T_SR ends at a timing point (i.e., as shown by the timing point t2 in FIG. 3) when the induction current of the secondary side winding W2 is reduced to zero”]; and an output stage [e.g. S2, CO, 90] configurable to provide an output voltage [e.g. VO] at an output in response to the secondary current, the output stage comprising a secondary switch [e.g. S2] and an output controller [e.g. 90], the output controller being configurable to: activate the secondary switch [e.g. using S2C] in response to an amplitude of the output voltage [e.g. see VO input to 90] and ringing of a primary voltage across the primary winding [e.g. paragraph 041 recites “During the period wherein a ringing current is generated, a signal related to such ringing current can be obtained via a primary side voltage VDS1 and/or a secondary side voltage VDS2”. Paragraph 042 recites “the secondary side controller circuit 90 determines a trigger timing point of the ZVS pulse PZV according to a second waveform characteristic of the ringing signal, to control the synchronous rectifier switch S2 to be turned ON for a predetermined ZVS time period T_ZVS”]; and deactivate the secondary switch to reduce the switch voltage to zero [e.g. paragraph 037 recites “when the synchronous rectifier switch S2 is turned OFF at a timing point (i.e., as shown by the timing point t4 in FIG. 3) at the end of the ZVS pulse PZV, the power transformer 10 will induce a circulation current Ip at the primary side winding W1 (as shown in FIG. 2B). According to the present invention, the circulation current Ip at the primary side winding W1 can discharge the parasitic capacitor Cp of the primary side switch S1 substantially to OV, and the charges of the parasitic capacitor Cp will be transferred to an input capacitor CI. Consequently, the primary side switch S1 can achieve zero voltage switching (ZVS) when the primary side switch S1 is turned ON in the next cycle and further cycles”].
Lin fails to disclose deactivate the primary switch responsive to an amplitude of the first current. Emphasis added to the lacking limitation.
Nayaknur [e.g. Fig. 1A] teaches deactivate the primary switch [e.g. S1 112] responsive to an amplitude of the first current [e.g. col. 7, lines 31 – 33 recite “The first controller 128 is coupled to receive a current sense signal ISNS 146 representative of the drain current ID 113 of the power switch S1 112”. Col. 7, lines 54 – 58 recite “the first controller 128 outputs the first drive signal DR 144 to turn OFF the power switch S1 112 when the drain current ID 113 provided by the current sense signal ISNS 146 reaches a current limit.” Examiner note: the primary switch current corresponds to the primary winding current].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Lin by s deactivate the primary switch responsive to an amplitude of the first current as taught by Nayaknur in order of being able to provide a reliable operation by using a robust controller using multiple electrical parameters.
Regarding claim 14, Lin [e.g. Figs. 2A-3] discloses a system comprising: a transformer [e.g. 10] comprising a primary winding [e.g. W1] and a secondary winding [e.g. W2]; a switching stage comprising a primary switch [e.g. S1] and an input controller [e.g. 80], the input controller being configured to activate the primary switch to conduct a primary current [e.g. Ip] in the primary winding in response to a switch voltage at a switching terminal having an amplitude of zero [e.g. Fig. 2A; paragraph 037 recites “the circulation current Ip at the primary side winding W1 can discharge the parasitic capacitor Cp of the primary side switch S1 substantially to OV, and the charges of the parasitic capacitor Cp will be transferred to an input capacitor CI. Consequently, the primary side switch S1 can achieve zero voltage switching (ZVS) when the primary side switch S1 is turned ON in the next cycle and further cycles”], and to deactivate the primary switch to provide a secondary current [e.g. Fig. 2A; ISR] in the secondary winding [e.g. W2; Fig.3 with respect to S1C and S2C; paragraph 036 recites “When the primary side switch S1 is turned ON and then OFF (as shown by the timing point t1 in FIG. 3), the SR-control pulse PSR controls the synchronous rectifier switch S2 to be ON for an SR time period T_SR, to perform secondary side synchronous rectification. The SR time period T_SR is substantially synchronous with the conduction time of an induction current of the secondary side winding W2. In other words, the SR time period T_SR begins at a timing point (i.e., the timing point t1) when the secondary side winding W2 starts generating the induction current due to energy transferred from the primary side winding W1 to the secondary side winding W2, and the SR time period T_SR ends at a timing point (i.e., as shown by the timing point t2 in FIG. 3) when the induction current of the secondary side winding W2 is reduced to zero”]; and an output stage [e.g. S2, CO, 90] configurable to provide an output voltage [e.g. VO] at an output in response to the secondary current, the output stage comprising a secondary switch [e.g. S2] and an output controller [e.g. 90], the output controller being configurable to activate the secondary switch [e.g. using S2C] in response to an amplitude of the output voltage [e.g. see VO input to 90] and ringing of a primary voltage across the primary winding [e.g. paragraph 041 recites “During the period wherein a ringing current is generated, a signal related to such ringing current can be obtained via a primary side voltage VDS1 and/or a secondary side voltage VDS2”. Paragraph 042 recites “the secondary side controller circuit 90 determines a trigger timing point of the ZVS pulse PZV according to a second waveform characteristic of the ringing signal, to control the synchronous rectifier switch S2 to be turned ON for a predetermined ZVS time period T_ZVS”], and to deactivate the secondary switch to reduce the switch voltage to zero [e.g. paragraph 037 recites “when the synchronous rectifier switch S2 is turned OFF at a timing point (i.e., as shown by the timing point t4 in FIG. 3) at the end of the ZVS pulse PZV, the power transformer 10 will induce a circulation current Ip at the primary side winding W1 (as shown in FIG. 2B). According to the present invention, the circulation current Ip at the primary side winding W1 can discharge the parasitic capacitor Cp of the primary side switch S1 substantially to OV, and the charges of the parasitic capacitor Cp will be transferred to an input capacitor CI. Consequently, the primary side switch S1 can achieve zero voltage switching (ZVS) when the primary side switch S1 is turned ON in the next cycle and further cycles”].
Lin fails to disclose deactivate the primary switch responsive to an amplitude of the first current. Emphasis added to the lacking limitation.
Nayaknur [e.g. Fig. 1A] teaches deactivate the primary switch [e.g. S1 112] responsive to an amplitude of the first current [e.g. col. 7, lines 31 – 33 recite “The first controller 128 is coupled to receive a current sense signal ISNS 146 representative of the drain current ID 113 of the power switch S1 112”. Col. 7, lines 54 – 58 recite “the first controller 128 outputs the first drive signal DR 144 to turn OFF the power switch S1 112 when the drain current ID 113 provided by the current sense signal ISNS 146 reaches a current limit.” Examiner note: the primary switch current corresponds to the primary winding current].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Lin by s deactivate the primary switch responsive to an amplitude of the first current as taught by Nayaknur in order of being able to provide a reliable operation by using a robust controller using multiple electrical parameters.
Regarding claim 2 and claim 15, Lin [e.g. Figs. 2A-3] discloses wherein the input controller has inputs coupled to the primary winding [e.g. see input of controller 80 directly connected to resistor having VM and input directly connected to ground; where the primary winding W1 is coupled magnetically to WA and electrically connected via resistor to the input of 80 and ground is coupled to the primary winding W1 via switch S1] and is configurable to monitor the ringing of the primary voltage and to activate the primary switch in response to the switch voltage having an amplitude of approximately zero after at least one trough of the ringing of the primary voltage [e.g. Fig. 3; see time t5. Also, paragraph 040 recites “the present invention can, via a ringing signal which is related to a ringing current of the power transformer 10, synchronize the above-mentioned switching signal S1C and the ZVS pulse PZV, thereby achieving zero voltage switching of the primary side switch S1”. Paragraph 041 recites “During the period wherein a ringing current is generated, a signal related to such ringing current can be obtained via a primary side voltage VDS1 and/or a secondary side voltage VDS2”].
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nayaknur in view of Lin.
Regarding claim 24, Nayaknur fails to disclose wherein the controller is configurable to activate the switch after a ringing at the primary side terminals, in which the voltage across the switch is zero at least once during the ringing.
Lin [e.g. Figs. 2A and 3] teaches wherein the controller [e.g. Fig. 2A; 80] is configurable to activate the switch [e.g. S1 ON at t5 of Fig. 3] after a ringing at the primary side terminals [e.g. VDS1 ringing at T1; paragraph 041 recites “During the period wherein a ringing current is generated, a signal related to such ringing current can be obtained via a primary side voltage VDS1”], in which the voltage across the switch is zero at least once during the ringing [e.g. Fig. 3; VDS1 is zero before t1].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Nayaknur by wherein the controller is configurable to activate the switch after a ringing at the primary side terminals, in which the voltage across the switch is zero at least once during the ringing as taught by Lin in order of being able to reduce losses by precisely synchronize the primary and secondary sides of the converter while maintaining zero voltage switching, paragraph 05.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 3 – 8 and 16 – 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 and claim 16 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the output controller is configured to monitor the output voltage and to activate the secondary switch in response to the output voltage exceeding an output voltage threshold to provide for concurrent activation of the primary switch and the secondary switch, wherein the input controller is configured to deactivate the primary switch in response to the primary current exceeding a primary current threshold”.
The primary reason for the indication of the allowability of claim 4 and claim 17 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the input controller comprises: a switch comparator configured to monitor an amplitude of the primary current and to generate a deactivate signal in response to the primary current exceeding a primary current threshold; a switch terminal comparator configured to monitor an amplitude of the switch voltage and to generate an activate signal in response to the switch voltage decreasing to approximately zero; and an activation latch configured to control the primary switch, wherein the activate signal is provided to a set input of the activation latch and the deactivate signal is provided to a reset input of the activation latch”.
The primary reason for the indication of the allowability of claim 6 and claim 19 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the output controller comprises: a secondary ringing comparator configured to monitor a secondary voltage across a secondary winding and to generate a zero-crossing signal in response to an increasing zero-crossing of the secondary voltage in response to the ringing of the primary voltage; an on-delay element configured to generate a delayed zero-crossing signal by delaying the zero-crossing signal by a quarter of a period of the ringing of the primary voltage; an output voltage comparator configured to monitor an amplitude of the output voltage and to generate an activate signal in response to the output voltage decreasing below an output voltage threshold; and an AND-gate configured to control the secondary switch based on the activate signal and the delayed zero-crossing signal”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838