DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-14 and 21-26 are presented for examination. Claims 15-20 are canceled.
Response to Arguments
3. Applicant’s argument filed on 06/01/2026 with respect claims 1 AND 26 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of "generating, by the computer, a hybrid layout by removing or converting the components associated with the scan chain for the structural test from the DFT layout."
First of all, the Examiner directs the applicant’s attention that during examination, a claim must be given its broadest reasonable interpretation (BRI) consistent with the specification as it would be interpreted by one of ordinary skill in the art (MPEP 2111). The Examiner interprets the feature of generating a hybrid layout from the DFT layout by removing or converting the components associated with the scan chain for the structural test from the DFT layout as the generating the structural test without including components associated with the scan chain based on paragraph [0041] of the applicant’s specification. Therefore, the Examiner respectfully disagrees and asserts the reference of Mielke (US 2023/0099503 A1) in paragraphs [0004], [0009], [0012], [0026], and [0083] teaches the such limitation. For example, FIGS. 1 and 2 show an example of testing a device under test (DUT) without using a SCAN test and with implementing a SCAN test in the device under test (DUT). FIG. 1 shows an integrated circuit to be tested without “scan cells”. Without scan cells, testing of the circuit is generally limited to the inputs and outputs of the circuit. FIG. 2 shows the integrated circuit where design's flip-flops were modified to allow them to function as stimulus and observation points, or “scan cells” during test, while performing their intended functional role during normal operation. The modified flip-flops, or scan cells, allow the overall design to be viewed as many small segments of combinational logic that can be more easily tested. See paragraph [0004].
Thus, usage of a test structure which is responsive to a magnetic field pulse allows to influence a test of the integrated circuit at one or more arbitrary locations of the integrated circuit while eliminating delays (and an increase in test time) which is normally caused by scan chains. For example, the test structure, which is responsive to a magnetic field impulse, is well suited to trigger “simple” test operations, like the activation or deactivation of a component, reset operations, a setting of certain registers to a desired default value or the like, which would normally require a dedicated signal line (or even a dedicated pin of the integrated circuit) or a lengthy scan chain operation. As an example, including one or more additional new circuits (e.g., one or more test structures which are responsive to a magnetic field impulse) in design for test (DFT) parts for structural tests enables testing partial areas without full loading of the scan chain, e.g., due to induction, e.g., intervening, in SCAN test. Additional possibilities of using magnetic fields, e.g., dynamic magnetic fields, in SCAN tests, are thus created, which helps to decrease time and cost of test. See paragraph [0009].
According to an embodiment, the test structure is configured to set one or more flipflops of a scan chain, which may, for example, be used for a test of the functional circuit structure, for example, by providing test signals to the functional circuit structure, to one or more test values. One or more inner flipflops of the scan chain may be, for example, set to test values directly without clocking a sequence of values through the whole scan chain. For example, the test value may be injected into a flipflop, e.g., an inner flipflop, of the scan chain, bypassing one or more preceding flipflops of the scan chain. Accordingly, there is no need to load the whole scan chain, since the test value is, for example, injected into a particular flipflop bypassing preceding flipflops of the scan chain. The speed of the testing will increase with corresponding decreasing of the cost of the testing. As a consequence, it is possible to determine values of one or more “inner” flipflops of the test chain in a highly efficient (and possible well time-synchronized) manner using a magnetic field impulse. See paragraph [0012]. Moreover, this embodiment is based on the finding that providing a magnetic field impulse to an integrated circuit configured to set a signal to a test value in response to the magnetic field impulse enables, for example, testing partial areas of the integrated circuit without full loading of the scan chain due to induction, e.g., intervening in SCAN test. See paragraph [0026].
Due to including an additional test structure or test circuit 302, partial areas of the integrated circuit 300 may be tested without full loading of the whole scan chain shown in FIG. 3 (e.g., the scan chain comprising flipflops 3041, 3042, 3043 and corresponding input multiplexers 3051, 3052, 3053). See paragraph [0044].
FIG. 5 shows an example of manipulation of SE signal (scan-enable) and/or clock-gating with induction switching element in order to avoid a capture of some values into scan-chain in accordance with an embodiment. See paragraph [0057].
According to an aspect of the invention, it has been found that if, for example, additional induction switching elements are installed in these critical areas, one could (or can) e.g., test partial areas, e.g., with manipulation of local clock gating, several times during one normal shift pattern. According to an aspect of the invention, it has been found that other additional test logic could (or can) also be implemented with help of induction switching elements without connection to the clock/reset system (e.g., changeable scan cells or switchable delay elements). See paragraph [0082].
As been described above, it would have been obvious to one of ordinary skill in the art that Mielke (US 2023/0099503 A1) teaches generating a hybrid layout [in design for test (DFT) parts for structural tests enables testing partial areas without full loading of the scan chain] by removing or converting the components associated with the scan chain for the structural test from the DFT layout [SE signal (scan-enable) and/or clock-gating with induction switching element in order to avoid a capture of some values into scan-chain]." Emphasis added.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claims 1 and 26 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Liu et al. (US 2015/0180618 A1)" herein after as Liu" in view of Kim (US 2012/0233511 A1)
in further view of Mielke (US 2023/0099503 A1).
As per claims 1 and 26:
Liu substantially teaches or discloses a method of testing an electronic device, the method comprising: receiving, by a computer, a circuit layout corresponding to the electronic device (see abstract, paragraph [0014], herein generating a design test pattern with an electronic design automation related (EDA) tool, e.g., in a native format thereof. Commands and/or instructions may also thus be sent to the ATE, with which the ATE may be controlled from within the design environment. The generated design test pattern is sent directly to an automated test equipment related (ATE) apparatus over a communication pipeline); generating, by the computer, a design for test (DFT) layout from the circuit layout (see abstract, paragraph [0076], herein Moreover, test cases may be brought up and turned around faster and easier as design for testing (DFT) engineering may create and drive test patterns directly onto an ATE apparatus platform and the test patterns may be iteratively fine tuned automatically using batch processing, and Fig.2 step 21); generating, by the computer, a test pattern by using an electronic design automation (EDA) tool, based at least in part on the DFT layout (see paragraph [0036], herein a design test pattern, commands and/or instructions are generated with an electronic design automation related (EDA) tool in a native format thereof).
Liu does not explicitly teach the DFT layout including components associated with a scan chain for a structural test of the electronic device.
However, Kim in the same the field of endeavor teaches the DFT layout including components associated with a scan chain for a structural test of the electronic device (see paragraph [0048], herein for testing a semiconductor device including complicated logic circuits, various DFT schemes are adopted. A scan scheme is one widely known DFT scheme, and the scan scheme uses a scan chain that is implemented with storage elements and operates as a shift register).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the test system of Liu with the teachings of Kim by including the DFT layout including components associated with a scan chain for a structural test of the electronic device.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the DFT layout including components associated with a scan chain for a structural test of the electronic device would have improved efficiency of testing during a design phase of the semiconductor device (see paragraph [0005] of Kim).
Liu-Kim as combined teaches all the subject matter of claims 1 and 26 except generating, by the computer, a hybrid layout from the DFT layout by removing or converting the components associated with the scan chain for the structural test from the DFT layout, wherein the electronic device manufactured by using the hybrid layout is tested by using the test pattern.
However, Mielke in the same the field of endeavor teaches generating, by the computer, a hybrid layout from the DFT layout (see paragraph [0009], one or more additional new circuits (e.g., one or more test structures which are responsive to a magnetic field impulse) in design for test (DFT) parts for structural tests enables testing partial areas without full loading of the scan chain, e.g., due to induction, e.g., intervening, in SCAN test; and paragraphs [0012], [0026], and [0044) by removing or converting the components associated with the scan chain for the structural test from the DFT layout (see paragraph [0057], FIG. 5 shows an example of manipulation of SE signal (scan-enable) and/or clock-gating with induction switching element in order to avoid a capture of some values into scan-chain in accordance with an embodiment; and paragraph [0082]), wherein the electronic device manufactured by using the hybrid layout is tested by using the test pattern (see paragraph [0027], herein the apparatus is configured to generate the magnetic field impulse in synchronism with a test program. The synchronization in magnetic field impulse delivery and data acquisition during test allows to combine a conventional testing concept, e.g., using a provision of stimulus signals for the integrated circuit under test by an automated test equipment and/or using a provision of input signals for a scan chain of the integrated circuit under test by an automated test equipment, which an influencing of the integrated circuit via a magnetic field impulse [note that the Examiner interprets the feature of electronic device manufactured by using the hybrid layout is tested by using the test pattern based on BRI and paragraph [0043] of the applicant’s specification which describes that the electronic device may receive a source layout relating to an electronic device under test (i.e., to be manufactured)).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the test system of Liu-Kim as combined with the teachings of Mielke by generating a hybrid layout from the DFT layout by removing or converting the components associated with the scan chain for the structural test from the DFT layout, wherein the electronic device manufactured by using the hybrid layout is tested by using the test pattern.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized generating a hybrid layout from the DFT layout by removing or converting the components associated with the scan chain for the structural test from the DFT layout, wherein the electronic device manufactured by using the hybrid layout is tested by using the test pattern would have improved tradeoff between reliability, test coverage and time and cost of test (see paragraph [0006] of Mielke).
Allowable Subject Matter
5. Claims 21-25 are allowed. See the examiner’s statement of reasons for allowance in the final action dated on 12/04/2025.
6. Claims 2, 5, 7, 11, 12, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim. Dependent claims 3-4, 6, 8-10 and 14 depend from on claims 2, 5, 7, and 13 and inherently include limitations therein and therefore are allowed as well.
Examiner Notes
7. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
8. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
9. THIS ACTION IS MADE FINAL; Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069.
The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN ALSHACK/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
Prosecution Insights