DETAILED ACTION
Response to Arguments
Applicant's arguments filed 09 July 2026 with respect to the 35 U.S.C. 103 rejection of the claims based on Yao have been fully considered and are persuasive. Specifically, Yao is understood not to actually reduce parasitic capacity as required by the claim, but merely reduce the effect of said parasitic capacity. Accordingly, the previous rejection has been withdrawn and prosecution is being reopened.
Applicant’s response with respect to the drawing objection has been fully considered and is accepted. The drawing objection has been withdrawn.
Applicant arguments with response to the objections to claims 1 and 16 for being ungrammatical has been considered, but is not persuasive. Necessary grammatical corrections may be required by the examiner. This is clear from MPEP 608 ("Necessary grammatical corrections, however, should be required by the examiner, but it must be remembered that an examination is not made for the purpose of securing grammatical perfection.") Accordingly, the objection for grammatical correction required previously are being maintained.
Claim Objections
Claims 1 and 16 are objected to because of the following informalities. Appropriate correction is required.
Claims 1 and 16 recite "the compensation device has" in the newly amended portion. This should be " the compensation device having."
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the compensation device recited in claims 1 and 16. This is understood to require, in addition to the structure recited in claims 1 and 16, a source of constant potential or a ground connection in order to achieve the reduction in parasitic capacity required by the claim. This is as discussed in the interview of 11 June 2026.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 7,589,390 to Yao, US 8,076,590 to Zhao et al. (hereinafter referred to as Zhao), and US 6,864,687 to Walker et al. (hereinafter referred to as Walker).
With regards to claim 1, Yao teaches a capacitive sensor device (see the embodiments of fig. 1, 2, fig. 4-5, 7, etc.), comprising:
a printed circuit board (PCB) (14; which may be a PCB as per col. 2, ll. 38-43) having a plurality of first vias (via 10 and any neighboring vias, not depicted but mentioned in col. 5, ll. 57-60 and col. 8, ll. 4-10) and
a sensing device (signal generating device 22; which may be a sensor as per col. 2, ll. 18-20) connected with the first via (see fig. 1, 2); and
a compensation device (shield element 32 in fig. 2, 110 in fig. 5b, etc.) reducing the effect of a time-dependent parasitic capacity of the PCB between the first vias and/or between any first tracks (col. 3, ll. 40-49 and col. 5, l. 57 to col. 6, l. 53), the compensation device having a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks (in the embodiment of fig. 1, 2, fig. 4a and fig. 5b, for example, see col. 7, ll. 19-25, plural shielding vias 32, 110, corresponding to second vias, would be arranged between first vias when multiple first vias are shielded as per col. 8, ll. 4-10).
PNG
media_image1.png
577
842
media_image1.png
Greyscale
Yao does not expressly teach a plurality of first tracks connected with the first vias, or reducing not merely the effect thereof, but reducing the time-dependent parasitic capacity of the PCB between the first vias and/or between any first tracks.
Still, it is well known to connect vias in a PCB to tracks or traces in or on the surface of a PCB in order to route signals. For example, Zhao (see fig. 1), shows just this. It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly have the PCB of Yao comprise a plurality of first tracks connected with the first vias in order to route signals as needed.
Walker teaches the feature of providing a ground plane (22 in fig. 1b), grounded vias (fig. 8b), and grounded traces (shielding traces in fig. 8b) connecting sets of the grounded vias in order to reduce parasitic coupling between signal-carrying elements of a PCB (see at least col. 4, ll. 48-56). This is addressing essentially the same problem as Yao: parasitic coupling between elements on/in a PCB that influences signal measurements.
PNG
media_image2.png
364
539
media_image2.png
Greyscale
PNG
media_image3.png
402
537
media_image3.png
Greyscale
In view hereof, It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Walker to Yao and Yang such that the compensation device comprises a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks (either by simply grounding vias 110 in Yang, or by providing grounded shielding traces, grounded vias, and a ground plane like taught by Walker in a manner suited to the particular PCB of Yao and Yang, such that these elements provide shielding whereby parasitic coupling (capacitance) between the first vias and/or between the first tracks is reduced as is likewise realized in Walker). One of ordinary skill in the art would be motivated to do so in order to realize the predictable benefit of reducing parasitic coupling. This would have an advantage of also being able to address parasitic coupling with the use of voltage following circuitry as in Yao.
Moreover, the shielding configuration taught by Walker would merely provide one known, specific configuration for addressing parasitic coupling, and nothing about the basic operation of the sensing arrangement of Yao would change. Merely connecting the shielding elements to ground would not cause the device of Yang to become inoperable, etc. The result of this combination would thus be predictable to one of ordinary skill in the art, and this combination accordingly amounts to no more than the predictable use of prior-art elements according to their established functions.
With regards to claim 3, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. In this combination, the second vias are connected with a source of constant electrical potential (ground, as per Walker).
With regards to claim 11, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. Yao further teaches the capacitive sensor device sensing a capacitance of below one pico-Farad (col. 2, ll. 18-25).
With regards to claim 14, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. Yao further teaches the capacitive sensor device sensing temperature, pressure (col. 2, l. 19), relative or absolute humidity, or a combination thereof.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yao, Zhao, and Walker as applied to claim 3 above, and further in view of US 7,091,424 to Oggioni et al. (hereinafter referred to as Oggioni).
With regards to claim 4, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 3. Yao appears to further teach the feature of providing the compensation device with a plurality of second tracks arranged in the PCB and connected with the second vias (in the embodiment of fig. 7, see metals 141 connected to shield elements 150 (corresponding to the second vias) within the substrate). However, even if this were not the case, Oggioni teaches the feature of providing a compensation device having a plurality of second tracks arranged in a PCB and connected with second (shielding) vias (see fig. 6 and 7; here, to reduce parasitic elements such as capacitance, Oggioni teaches the use of grounded vias (corresponding to the second vias; see 615 in fig. 6, corresponding to vias 750 in fig. 7) to shield a sensitive signal line from parasitics, and in the embodiment of fig. 7 teaches the these plural vias being connected to plural tracks 740, 725 to shield signal track 720 and its via as it penetrates the surrounding substrate). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly adopt such a configuration in the device of Yao, Zhao, and Walker such that the compensation device has a plurality of second tracks arranged in the PCB and connected with the second vias. One of ordinary skill in the art would be motivated to do so in order to shield first vias through multiple substrate (PCB) layers.
With regards to claim 5, the combination of Yao, Zhao, Walker, and Oggioni teaches the capacitive sensor device of claim 4. In this combination, Walker teaches the source of constant electrical potential being ground (see fig. 8b of Walker). Note also that, to reduce the effect of parasitic elements such as capacitance, Oggioni teaches the feature of providing shielding vias and tracks around a signal via, and specifically teaches that a ground potential is preferable (col. 5, ll. 65-67).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yao, Zhao, and Walker as applied to claim 1 above, and further in view of US 10,998,260 to Then et al. (hereinafter referred to as Then).
With regards to claim 6, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. This combination does not expressly teach the compensation device having an opening in the PCB between the first vias and/or between the first tracks.
Then teaches the use of openings in a substrate between elements in order to reduce parasitic capacitance therebetween (see air gaps 470, 460, 440 in fig. 4, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly adopt openings in the PCB of Yao, Zhao, and Walker between the first vias and/or between the first tracks in order to reduce parasitics therebetween.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yao, Zhao, and Walker as applied to claim 1 above, and further in view of US 2020/0211781 to Cho et al. (hereinafter referred to as Cho).
With regards to claim 7, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. Although this art does not expressly teach the time-dependent parasitic capacity of the PCB depending on temperature and/or humidity of an environment of the capacitive sensor device, Cho indicates that "PCBs generally have parasitic capacitance varying with temperature, and TCCs may be different according to the lengths of respective conductive lines at the time of designing the PCBs." ([0007]). Accordingly, the PCB taught in Yao is understood to reasonably have a time-dependent parasitic capacity of the PCB that depends on temperature and/or humidity of an environment of the capacitive sensor device. In other words, as evidenced by Cho, this is an inherent property of the base reference.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yao, Zhao, and Walker as applied to claim 1 above, and further in view of US 5,148,355 to Lowe et al. (hereinafter referred to as Lowe).
With regards to claim 8, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the PCB being an epoxy material.
Lowe teaches the feature of forming a PCB from an epoxy material (e.g., a polymerized epoxy containing glass fibers (col. 1, ll. 33-49). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly form the PCB of Yao from an epoxy material. In addition to this being well-known PCB configuration, doing so would enable a high-strength PCB to be provided (col. 1, ll. 45-49; Lowe).
With regards to claim 9, the combination of Yao, Zhao, Walker, and Lowe teaches the capacitive sensor device of claim 8. In this combination, the first vias would be formed in the epoxy material and the first tracks would be formed in or on the epoxy material.
With regards to claim 10, the combination of Yao, Zhao, Walker, and Lowe teaches the capacitive sensor device of claim 9. In this combination, when the PCB is epoxy as per Lowe, the compensation device would be at least partially formed in the epoxy material.
Claims 12-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yao, Zhao, and Walker as applied to claim 1 above, and further in view of Risos, Alex et al.: "Interdigitated Sensors: A Design Principle for Accurately Measuring the Permittivity of Industrial Oils," IEEE Sensors Journal, October 1, 2017, pp. 6232-6239, vol. 17, no. 19, ISSN: 1530-437X (hereinafter referred to as Risos; cited by applicant).
With regards to claim 12, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the sensing device contacting a fluid.
Risos teaches an interdigitated capacitive sensor that contacts a fluid to measure the relative permittivity thereof (see title, abstract, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yao, Zhao, and Walker such that the sensing device is configured as an interdigitated sensor as in Risos and is configured to contact a fluid. One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
With regards to claim 13, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the sensing device having a plurality of sensing electrodes and a sensing layer, the sensing electrodes and the sensing layer form a capacitor.
Risos teaches an interdigitated capacitive sensor that senses a property of a fluid (see title, abstract, etc.), the sensing device having a plurality of sensing electrodes (see IDS electrodes in fig. 1(a) and a sensing layer (resin layer in fig. 1(a)), the sensing electrodes and the sensing layer form a capacitor (see fig. 1(a)-1(b)). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yao, Zhao, and Walker such that the sensing device is configured as an interdigitated sensor and is configured to contact a fluid as in Risos. One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
With regards to claim 15, the combination of Yao, Zhao, and Walker teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the capacitive sensor device sensing a property of a fluid.
Risos teaches an interdigitated capacitive sensor that senses a property of a fluid (contacts a fluid to measure the relative permittivity thereof; see title, abstract, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yao and Zhao such that the sensing device senses a property of a fluid as in Risos (e.g., is configured as an interdigitated sensor and is configured to contact a fluid). One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yao, Zhao, Walker and Risos.
With regards to claim 16, Yao teaches a method, comprising:
providing a capacitive sensor device including (see the embodiments of fig. 1, 2, fig. 4-5, 7, etc.)
a printed circuit board (PCB) (14; which may be a PCB as per col. 2, ll. 38-43) having a plurality of first vias (via 10 and any neighboring vias, not depicted but mentioned in col. 5, ll. 57-60 and col. 8, ll. 4-10),
a sensing device (signal generating device 22; which may be a sensor as per col. 2, ll. 18-20) connected with the first vias (see fig. 1, 2), and
a compensation device (shield element 32 in fig. 2, 110 in fig. 5b, etc.) reducing the effect of a time-dependent parasitic capacity of the PCB between the first vias and/or between any first tracks (col. 3, ll. 40-49 and col. 5, l. 57 to col. 6, l. 53), the compensation device having a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks (in the embodiment of fig. 1, 2, fig. 4a and fig. 5b, for example, see col. 7, ll. 19-25, plural shielding vias 32, 110, corresponding to second vias, would be arranged between first vias when multiple first vias are shielded as per col. 8, ll. 4-10).
Yao does not expressly teach a plurality of first tracks connected with the first vias, reducing not merely the effect thereof, but reducing the time-dependent parasitic capacity of the PCB between the first vias and/or between any first tracks, the method being for sensing a property of a fluid, or contacting the fluid with the sensing device of the capacitive sensor device.
Still, it is well known to connect vias in a PCB to tracks or traces in or on the surface of a PCB in order to route signals. For example, Zhao (see fig. 1), shows just this. It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly have the PCB of Yao comprise a plurality of first tracks connected with the first vias in order to route signals as needed.
Walker teaches the feature of providing a ground plane (22 in fig. 1b), grounded vias (fig. 8b), and grounded traces (shielding traces in fig. 8b) connecting sets of the grounded vias in order to reduce parasitic coupling between signal-carrying elements of a PCB (see at least col. 4, ll. 48-56). This is addressing essentially the same problem as Yao: parasitic coupling between elements on/in a PCB that influences signal measurements.
In view hereof, It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Walker to Yao and Yang such that the compensation device comprises a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks (either by simply grounding vias 110 in Yang, or by providing grounded shielding traces, grounded vias, and a ground plane like taught by Walker in a manner suited to the particular PCB of Yao and Yang, such that these elements provide shielding whereby parasitic coupling (capacitance) between the first vias and/or between the first tracks is reduced as is likewise realized in Walker). One of ordinary skill in the art would be motivated to do so in order to realize the predictable benefit of reducing parasitic coupling. This would have an advantage of also being able to address parasitic coupling with the use of voltage following circuitry as in Yao.
Moreover, the shielding configuration taught by Walker would merely provide one known, specific configuration for addressing parasitic coupling, and nothing about the basic operation of the sensing arrangement of Yao would change. Merely connecting the shielding elements to ground would not cause the device of Yang to become inoperable, etc. The result of this combination would thus be predictable to one of ordinary skill in the art, and this combination accordingly amounts to no more than the predictable use of prior-art elements according to their established functions.
Risos teaches the features of sensing a property of a fluid (e.g., relative permittivity) with a provided interdigitated capacitive sensor (fig. 1(a), etc.), and specifically contacting the capacitive sensor with a fluid to measure the relative permittivity thereof (see title, abstract, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yao, Zhao, and Walker such that the method senses a property of a fluid, and the method involves contacting the fluid with the sensing device as in Risos. One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
With regards to claim 17, the combination of Yao, Zhao, Walker, and Risos teaches the method of claim 16. This combination further teaches the fluid being an automotive fluid, fuel, a coolant or oil (an oil; see the abstract and introduction of Risos).
With regards to claim 18, the combination of Yao, Zhao, Walker and Risos teaches the method of claim 16. This combination further teaches the capacitive sensor device sensing a property of the fluid, the property is at least one of viscosity, density, temperature, a dielectric constant (i.e., relative permittivity, which is sensed using the configuration of Risos) and contaminants.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James Split whose telephone number is (571)270-1524. The examiner can normally be reached Monday to Friday, 9:00 to 3:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JS/Examiner, Art Unit 2858
/JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858
Prosecution Insights