DETAILED ACTION
Response to Arguments
Applicant's arguments filed 30 December 2026 have been fully considered but they are not persuasive.
First, the applicant responds to the objection to the drawings under 37 CFR 1.83(a), in which the limitation of claim 13 claiming "the sensing device has a plurality of sensing electrodes and a sensing layer, the sensing electrodes and the sensing layer form a capacitor" was objected to because this feature is not shown in the claims, by stating "A drawing need not be furnished by Applicant if it is not necessary for the understanding of the subject matter sought. (See 37 C.F.R. § 1.81(a))." However, the regulation asserted by the applicant does not obviate the requirement under 37 CFR 1.83(a) that claimed features be shown in the drawings. Because the features of claim 13 are still not shown, the objection is maintained.
In view of the amendments to the claims and the statements made by the applicant, the 35 U.S.C. 112(d) interpretation of the claims is withdrawn as structure that performs the indicated function is, as stated by the applicant, now recited in the claims.
The rejection of claims 2-4 under 35 U.S.C. 112(d) is also withdrawn in view of the amendments to claim 1.
With respect to the 35 U.S.C. 103 rejections based on Yao in view of Zhao, the applicant argues that Yao does not teach "a compensation device reducing a time-dependent parasitic capacity of the PCB between the first vias and/or between the first tracks, the compensation device has a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks" as claimed in claim 1. This is allegedly because the references fail to show certain features of the invention. However, it is noted that the features upon which applicant relies (i.e., that the source of the parasitic capacitance is reduced) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The claims merely require that parasitic capacitance of the PCB between first vias and/or between first tracks be reduced. Yao, in col. 2, ll. 38∓40 and col. 4, ll. 40-43, explicitly teaches how shielding reduces parasitic capacitance around a via, and accordingly, Yao is seen to teach reducing parasitic capacitance of the PCB between first vias and/or between first tracks, at least for areas between a via and a respective shield element (compensation device).
The applicant further argues that Yao does not teach a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks. In the previous rejection of claims 1 and 2, the applicant was referred to the sensor device of the embodiments of fig. 1, 2, fig. 4-5, 7, etc. Even if the applicant disagrees with the embodiments of fig. 4 and 7, fig. 5b very clearly shows how plural second vias are located between two other through vias. In fig. 5b, the shielding via is actually composed of plural vias with a small gap therebetween. The compensation device of the capacitive sensor device cited against the claimed capacitive sensor device accordingly clearly has a plurality of second vias arranged in the PCB between the first vias (of Yao), and/or between the first tracks (when Yao is modified by Zhao). The previous rejections are accordingly essentially being maintained, except where as necessitated by amendment.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of the sensing device having a plurality of sensing electrodes and a sensing layer, the sensing electrodes and the sensing layer form a capacitor (claim 13) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claims 1 and 16 are objected to because of the following informalities. Appropriate correction is required.
Claims 1 and 16 recite "the compensation device has" in the newly amended portion. This should be " the compensation device having."
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 7,589,390 to Yao and US 8,076,590 to Zhao et al. (hereinafter referred to as Zhao).
With regards to claim 1, Yao teaches a capacitive sensor device (see the embodiments of fig. 1, 2, fig. 4-5, 7, etc.), comprising:
a printed circuit board (PCB) (14; which may be a PCB as per col. 2, ll. 38-43) having a plurality of first vias (via 10 and any neighboring vias, not depicted but mentioned in col. 5, ll. 57-60) and
a sensing device (signal generating device 22; which may be a sensor as per col. 2, ll. 18-20) connected with the first via (see fig. 1, 2); and
a compensation device (shield element 32) reducing a time-dependent parasitic capacity of the PCB between the first vias and/or between any first tracks (col. 3, ll. 40-49 and col. 5, l. 57 to col. 6, l. 53; also note that in the embodiment of fig. 4a, vias 88 would be arranged in the PCB at least between the first vias, in the embodiment of fig. 4b the vertical portion of 98 would be at least between the first vias, and in the embodiment of fig. 7, shield elements 150 correspond to the second vias and are disposed between first vias 152; finally, note that the output of coupling element 52 generates a constant, e.g., zero, electric field at the shield electrode), the compensation device having a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks (in the embodiment of fig. 4a, vias 88 would be arranged in the PCB at least between the first vias, in the embodiment of fig. 4b the vertical portion of 98 would be at least between the first vias, and in the embodiment of fig. 7, shield elements 150 correspond to the second vias and are disposed between first vias 152; in fig. 5b, also cited to teach this capacitive sensor device, there are plural vias 110 and these would be arranged between first vias).
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Yao does not expressly teach a plurality of first tracks connected with the first vias.
Still, it is well known to connect vias in a PCB to tracks or traces in or on the surface of a PCB in order to route signals. For example, Zhao (see fig. 1), shows just this. It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly have the PCB of Yao comprise a plurality of first tracks connected with the first vias in order to route signals as needed.
With regards to claim 3, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. Yao further teaches the second vias being connected with a source of constant electrical potential (the output of coupling element 52 generates a constant, e.g., zero, electric field at the shield electrode).
With regards to claim 11, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. Yao further teaches the capacitive sensor device sensing a capacitance of below one pico-Farad (col. 2, ll. 18-25).
With regards to claim 14, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. Yao further teaches the capacitive sensor device sensing temperature, pressure (col. 2, l. 19), relative or absolute humidity, or a combination thereof.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yao and Zhao as applied to claim 3 above, and further in view of US 7,091,424 to Oggioni et al. (hereinafter referred to as Oggioni).
With regards to claim 4, the combination of Yao and Zhao teaches the capacitive sensor device of claim 3. Yao appears to further teach the compensation device having a plurality of second tracks arranged in the PCB and connected with the second vias (in the embodiment of fig. 7, see metals 141 connected to shield elements 150 (corresponding to the second vias) within the substrate). However, even if this were not the case, Oggioni teaches the feature of providing a compensation device having a plurality of second tracks arranged in the PCB and connected with the second vias (see fig. 6 and 7; here, to reduce parasitic elements such as capacitance, Oggioni teaches the use of grounded vias (corresponding to the second vias; see 615 in fig. 6, corresponding to vias 750 in fig. 7) to shield a sensitive signal line from parasitics, and in the embodiment of fig. 7 teaches the these plural vias being connected to plural tracks 740, 725 to shield signal track 720 and its via as it penetrates the surrounding substrate). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly adopt such a configuration in the device of Yao and Zhao such that the compensation device has a plurality of second tracks arranged in the PCB and connected with the second vias. One of ordinary skill in the art would be motivated to do so in order to shield first vias through multiple substrate (PCB layers) between two layers being connected.
With regards to claim 5, the combination of Yao, Zhao, and Oggioni teaches the capacitive sensor device of claim 4. This combination does not expressly teach the source of constant electrical potential being ground. However, to reduce the effect of parasitic elements such as capacitance, Oggioni teaches the feature of providing shielding vias and tracks around a signal via, and specifically teaches that a ground potential is preferable (col. 5, ll. 65-67). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly connect the shielding elements in the device of Yao, Zhao, and Oggioni to ground in order to compensate for parasitics without the buffer of Yao.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yao and Zhao as applied to claim 1 above, and further in view of US 10,998,260 to Then et al. (hereinafter referred to as Then).
With regards to claim 6, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. This combination does not expressly teach the compensation device having an opening in the PCB between the first vias and/or between the first tracks.
Then teaches the use of openings in a substrate between elements in order to reduce parasitic capacitance therebetween (see air gaps 470, 460, 440 in fig. 4, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly adopt openings in the PCB of Yao and Zhao between the first vias and/or between the first tracks in order to reduce parasitics therebetween.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yao and Zhao as applied to claim 1 above, and further in view of US 2020/0211781 to Cho et al. (hereinafter referred to as Cho).
With regards to claim 7, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. Although this art does not expressly teach the time-dependent parasitic capacity of the PCB depending on temperature and/or humidity of an environment of the capacitive sensor device, Cho indicates that "PCBs generally have parasitic capacitance varying with temperature, and TCCs may be different according to the lengths of respective conductive lines at the time of designing the PCBs." ([0007]). Accordingly, the PCB taught in Yao is understood to reasonably have a time-dependent parasitic capacity of the PCB that depends on temperature and/or humidity of an environment of the capacitive sensor device. In other words, as evidenced by Cho, this is an inherent property of the base reference.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yao and Zhao as applied to claim 1 above, and further in view of US 5,148,355 to Lowe et al. (hereinafter referred to as Lowe).
With regards to claim 8, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the PCB being an epoxy material.
Lowe teaches the feature of forming a PCB from an epoxy material (e.g., a polymerized epoxy containing glass fibers (col. 1, ll. 33-49). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly form the PCB of Yao from an epoxy material. In addition to this being well-known PCB configuration, doing so would enable a high-strength PCB to be provided (col. 1, ll. 45-49; Lowe).
With regards to claim 9, the combination of Yao, Zhao, and Lowe teaches the capacitive sensor device of claim 8. In this combination, the first vias would be formed in the epoxy material and the first tracks would be formed in or on the epoxy material.
With regards to claim 10, the combination of Yao, Zhao, and Lowe teaches the capacitive sensor device of claim 9. In this combination, when the PCB is epoxy as per Lowe, the compensation device would be at least partially formed in the epoxy material.
Claims 12-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yao and Zhao as applied to claim 1 above, and further in view of Risos, Alex et al.: "Interdigitated Sensors: A Design Principle for Accurately Measuring the Permittivity of Industrial Oils," IEEE Sensors Journal, October 1, 2017, pp. 6232-6239, vol. 17, no. 19, ISSN: 1530-437X (hereinafter referred to as Risos; cited by applicant).
With regards to claim 12, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the sensing device contacting a fluid.
Risos teaches an interdigitated capacitive sensor that contacts a fluid to measure the relative permittivity thereof (see title, abstract, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yao and Zhao such that the sensing device is configured as an interdigitated sensor as in Risos and is configured to contact a fluid. One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
With regards to claim 13, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the sensing device having a plurality of sensing electrodes and a sensing layer, the sensing electrodes and the sensing layer form a capacitor.
Risos teaches an interdigitated capacitive sensor that senses a property of a fluid (see title, abstract, etc.), the sensing device having a plurality of sensing electrodes (see IDS electrodes in fig. 1(a) and a sensing layer (resin layer in fig. 1(a)), the sensing electrodes and the sensing layer form a capacitor (see fig. 1(a)-1(b)). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yao and Zhao such that the sensing device is configured as an interdigitated sensor and is configured to contact a fluid as in Risos. One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
With regards to claim 15, the combination of Yao and Zhao teaches the capacitive sensor device of claim 1. However, this combination does not expressly teach the capacitive sensor device sensing a property of a fluid.
Risos teaches an interdigitated capacitive sensor that senses a property of a fluid (contacts a fluid to measure the relative permittivity thereof; see title, abstract, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yao and Zhao such that the sensing device senses a property of a fluid as in Risos (e.g., is configured as an interdigitated sensor and is configured to contact a fluid). One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yao, Zhao, and Risos.
With regards to claim 16, Yao teaches a method, comprising: providing
a capacitive sensor device including (see the embodiments of fig. 1, 2, fig. 4-5, 7, etc.)
a printed circuit board (PCB) (14; which may be a PCB as per col. 2, ll. 38-43) having a plurality of first vias (via 10 and any neighboring vias, not depicted but mentioned in col. 5, ll. 57-60),
a sensing device (signal generating device 22; which may be a sensor as per col. 2, ll. 18-20) connected with the first vias (see fig. 1, 2), and
a compensation device (shield element 32) reducing a time-dependent parasitic capacity of the PCB between the first vias and/or between the first tracks (col. 3, ll. 40-49 and col. 5, l. 57 to col. 6, l. 53; also note that in the embodiment of fig. 4a, vias 88 would be arranged in the PCB at least between the first vias, in the embodiment of fig. 4b the vertical portion of 98 would be at least between the first vias, and in the embodiment of fig. 7, shield elements 150 correspond to the second vias and are disposed between first vias 152; finally, note that the output of coupling element 52 generates a constant, e.g., zero, electric field at the shield electrode), the compensation device having a plurality of second vias arranged in the PCB between the first vias and/or between the first tracks (in the embodiment of fig. 4a, vias 88 would be arranged in the PCB at least between the first vias, in the embodiment of fig. 4b the vertical portion of 98 would be at least between the first vias, and in the embodiment of fig. 7, shield elements 150 correspond to the second vias and are disposed between first vias 152; in fig. 5b, also cited to teach this capacitive sensor device, there are plural vias 110 and these would be arranged between first vias).
Yao does not expressly teach a plurality of first tracks connected with the first vias, the method of sensing a property of a fluid, or contacting the fluid with the sensing device of the capacitive sensor device.
Still, it is well known to connect vias in a PCB to tracks or traces in or on the surface of a PCB in order to route signals. For example, Zhao (see fig. 1), shows just this. It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to similarly have the PCB of Yao comprise a plurality of first tracks connected with the first vias in order to route signals as needed.
Risos teaches the features of sensing a property of a fluid (e.g., relative permittivity) with a provided interdigitated capacitive sensor (fig. 1(a), etc.), and specifically contacting the capacitive sensor with a fluid to measure the relative permittivity thereof (see title, abstract, etc.). It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yao and Zhao such that the method senses a property of a fluid, and the method involves contacting the fluid with the sensing device as in Risos. One of ordinary skill in the art would be motivated to do so in order to measure the relative permittivity of, e.g., an industrial oil while also compensating for parasitic capacitances.
With regards to claim 17, the combination of Yao, Zhao, and Risos teaches the method of claim 16. This combination further teaches the fluid being an automotive fluid, fuel, a coolant or oil (an oil; see the abstract and introduction of Risos).
With regards to claim 18, the combination of Yao, Zhao, and Risos teaches the method of claim 16. This combination further teaches the capacitive sensor device sensing a property of the fluid, the property is at least one of viscosity, density, temperature, a dielectric constant (i.e., relative permittivity, which is sensed using the configuration of Risos) and contaminants.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James Split whose telephone number is (571)270-1524. The examiner can normally be reached Monday to Friday, 9:00 to 3:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JS/Examiner, Art Unit 2858
/JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858
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