Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to application filed 12/03/2025.
Claims 1, 3-20 are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/03/2025 has been entered.
Response to Arguments
Applicant's arguments filed 12/03/2025 have been fully considered but they are not persuasive. Applicant assert that “Kumar teaches that certain parameters are used to select an already-generated Al model from a set of Al models. Kumar does not disclose a "control loop" that "generates a certified-DNN architecture based on the provided technical constraints," and “Kumar does not teach or suggest a translation of application level requirements/parameters into technical constraints”. Examiner respectfully disagrees.
Applicant’s current specification recites “(i) selecting, using the DNN search engine, a candidate DNN architecture based on the technical constraints, and (ii) generating, using the hardware synthesis engine, a hardware architecture corresponding to the selected candidate DNN architecture” ([0007]). Furthermore, applicant’s current specification recites, “the DSE 208 leverages a high-level HW synthesis engine (HSE) 210 to translate a software-defined neural network into a hardware-based architecture, for example a field-programmable gate array (FPGA)-compliant circuit configuration. The HSE 210 evaluates the selected DNN architecture, determines the DNN latency and energy consumption of the selected DNN, and provides the DNN latency and energy consumption as feedback to the DSE 208. The certified, optimal DNN structure 212 generated by the 4D-CS 200 is a best fit for the selected system constraints at the time that the DNN structure 212 was generated (fig. 2, [0030]-[0031]). In other words, applicant’s current specification discloses that an already generated DNN architecture is selected and certified as a best fit for the selected constraints.
Kumar discloses the AI-NF logic translates the requirements/parameters into a determination of which available AI model instance is suited (e.g., best suited, better suited, etc.) for the particular request. The AI-NF logic circuitry 430 transforms the request into a query for the associated model resource. Then, a query to the AI-NF infrastructure circuitry 410 is performed. (Block 940). For example, the table 350 can be queried such as by the AI-NF logic circuitry 430-434, the AI-NF model discovery circuitry 560, the AI-NF model offering circuitry 520, the AI-NF execution logic circuitry 540, etc., to identify one or more models from the table 350, cache 460, etc., for comparison to one or more requirements/criterion/constraints provided as part of the query (e.g. translated constraints) ([0060], [0124]-[0126]). Furthermore, Loh discloses a controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250 (e.g. control loop). Therefore, the cited prior art of record discloses the argue limitations
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 2022/0150125 A1) in view of Loh et al. (US 2021/0192337 A1).
Regarding claim 1, Kumar discloses a method of generating a [neural network] comprising: receiving one or more application-level requirements associated with network communications ([0060]: edge services can trigger AI-NF logic hosted on the infrastructure to execute an AI-NF model with a set of requirements or parameters (e.g., accuracy, latency, etc.); translating the one or more application-level requirements into one or more technical constraints ([0060]: The AI-NF logic translates the requirements/parameters into a determination of which available AI model instance is suited (e.g., best suited, better suited, etc.) for the particular request), the one or more application-level requirements comprising end-to-end radio access network (RAN) latency and accuracy ([0060]: a set of requirements or parameters (e.g., accuracy, latency, etc.). [0163]: The edge cloud 1310 thus may be embodied as any type of network that provides edge computing and/or storage resources which are proximately located to radio access network (RAN) capable endpoint devices), and the one or more technical constraints comprising DNN level latency, hardware/software resources, and DNN-level accuracy ([0058]: Each named model instance (e.g., a speech to text neural network (NN), etc.) has a set of meta-data fields that defines characteristics of the model instance (e.g. accuracy, latency etc.). [0065]: One or more of the AI-NF local inventory circuitry 440-444 can produce set(s) of one or more models 470-475 including associated parameters/characteristics such as accuracy, latency, recall, etc.),
providing the one or more technical constraints to a [control] that generates a certified [neural network architecture] based on the provided technical constraints ([0058],[0078]-[0079], [0126]: telemetry information (e.g., related to the network, one or more edge servers/appliances, other infrastructure telemetry information, etc.) can be used as part of a model query to identify an available model instance to select. Telemetry information can be used to organize models in the example table 350 according to use case, type of function, accuracy, recall, latency, etc. The AI-NF execution logic circuitry 540 can leverage the telemetry circuitry 530 to determine whether one or more models available in the table 350 satisfy requirements and/or other parameters provided in a query for a model/model type).
However, Kumar does not disclose a method of generating a deep neural network (DNN), comprising: providing the one or more technical constraints to a control loop that generates a certified DNN architecture based on the provided technical constraints
In an analogous art, Loh disclose a method of generating a deep neural network (DNN), comprising: providing the one or more technical constraints to a control loop that generates a certified DNN architecture based on the provided technical constraints ([0058]: Generating an optimal DNN model requires navigating through the latency and accuracy characteristics of different DNN elements targeting different heterogeneous components…reinforcement learning is used to search through the DNN elements to maximize the accuracy within provided latency constraints. [0063]: Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250. In certain embodiments, controller module 220 adjusts the DNN model elements, or selects a new DNN model, to maximize the reward. The new or adjusted DNN model is provided to trainer module 230, latency/HA utilization predictor module 240 and feedback generator module 250 for another iteration).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Kumar to comprise “method of generating a deep neural network (DNN), comprising: providing the one or more technical constraints to a control loop that generates a certified DNN architecture based on the provided technical constraints” taught by Loh.
One of ordinary skilled in the art would have been motivated because it would have enabled generating an optimal DNN model require for navigating through the latency and accuracy characteristics of different DNN elements targeting different heterogeneous components (Loh, [0058]).
Regarding claim 8, Kumar-Loh discloses the method of claim 1, wherein the technical constraints comprise one or more of (i) network latency, (ii) available hardware resources, (iii) available software resources, (iv) required DNN accuracy, (iv) computation and/or network slicing allocation, (v) current noise and/or interference levels at an input of the DNN (Loh, [0058]: DNN elements to maximize the accuracy within provided latency constraints). The same rationale applies as in claim 1.
Regarding claim 9, Kumar-Loh discloses the method of claim 1, further comprising producing, by the certified DNN architecture, a certified DNN output based on the certified DNN architecture and a dynamic DNN input, wherein the control loop revises the certified DNN architecture based on the certified output (Loh, [0062]-[0063]: Feedback generator module 250 provides feedback to controller module 220 regarding the performance of the selected DNN model on each particular HA. In certain embodiments, the feedback is a metric, such as a reward, that is a function of one or more objectives, such as, for example, DNN model size, accuracy, latency, and HA utilization. Additional objectives may include, for example, power efficiency, etc. Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250). The same rationale applies as in claim 1.
Regarding claim 10; the claim is interpreted and rejected for the same reason as set forth in claim 1.
Claims 3-7, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Loh, as applied in claim 1, in further view of Melodia et al. (WO 2021/055824 A1).
Regarding claim 3, Kumar-Loh discloses the method of claim 1. Loh discloses wherein the control loop comprises a DNN search engine (Loh, [0063]: Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250. In certain embodiments, controller module 220 adjusts the DNN model elements, or selects a new DNN model).
However, Kumar-Loh does not disclose the control loop comprises hardware synthesis engine.
In an analogous art, Melodia discloses the control loop comprises hardware synthesis engine ([0036]: Supervised DRL Model Selection and Bootstrap (S-DMSB) technique that combines concepts from transfer learning and high- level synthesis (HLS) circuit design to select a deep neural network architecture that concurrently (a) satisfies hardware and application throughput constraints and (b) improves the DRL algorithm convergence).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Kumar-Loh to comprise “the control loop comprises hardware synthesis engine” taught by Melodia.
One of ordinary skilled in the art would have been motivated because it would have enabled selects a neural network model as a function of latency and hardware size constraints (Melodia, [0057]).
Regarding claim 4, Kumar-Loh discloses the method of claim 3. Loh discloses further comprising (i) selecting, using the DNN search engine, a candidate DNN architecture based on the technical constraints (Loh, [0058]: Generating an optimal DNN model requires navigating through the latency and accuracy characteristics of different DNN elements targeting different heterogeneous components…reinforcement learning is used to search through the DNN elements to maximize the accuracy within provided latency constraints. [0063]: Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250. In certain embodiments, controller module 220 adjusts the DNN model elements, or selects a new DNN model),.
However, Kumar-Loh does not disclose (ii) generating, using the hardware synthesis engine, a hardware architecture corresponding to the selected candidate DNN architecture.
In an analogous art, Melodia discloses (ii) generating, using the hardware synthesis engine, a hardware architecture corresponding to the selected candidate DNN architecture ([0036]: Supervised DRL Model Selection and Bootstrap (S-DMSB) technique that combines concepts from transfer learning and high- level synthesis (HLS) circuit design to select a deep neural network architecture that concurrently (a) satisfies hardware and application throughput constraints and (b) improves the DRL algorithm convergence).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Kumar-Loh to comprise “(ii) generating, using the hardware synthesis engine, a hardware architecture corresponding to the selected candidate DNN architecture” taught by Melodia.
One of ordinary skilled in the art would have been motivated because it would have enabled selects a neural network model as a function of latency and hardware size constraints (Melodia, [0057]).
Regarding claim 5, Kumar-Loh-Melodia discloses the method of claim 4, wherein the hardware architecture comprises a DNN structure and associated weighting coefficients (Loh, [0069]: a weighted-average ensembling technique is used to weight the output of the HA-specific DNN models). The same rationale applies as in claim 1.
Regarding claim 6, Kumar-Loh-Melodia discloses the method of claim 4, further comprising determining, using the hardware synthesis engine, latency and energy consumption associated with the generated DNN hardware architecture, and providing the generated latency and energy consumption associated the DNN hardware architecture to the DNN search engine (Melodia, [0032]-[0033]: a core challenge is how to design a DNN “small” enough to provide low latency and energy consumption, yet also “big” enough to provide a good approximation of the state-action function. High-level synthesis (HLS) circuit design to provide a neural network architecture that satisfies hardware and application throughput constraints and speeds up the DRL algorithm convergence. Example embodiments can be implemented for real-time DRL-based algorithms on a real-world wireless platform with multiple channel conditions, and can support increases (e.g., 16x) data rate and consume less energy (e.g., 14x) than a software-based implementation). The same rationale applies as in claim 1.
Regarding claim 7, Kumar-Loh-Melodia discloses the method of claim 6, further comprising revising, by the DNN search engine using the latency and energy consumption associated with the DNN hardware architecture, the selected DNN architecture to produce the certified DNN architecture (Loh, [0062]-[0063]: Feedback generator module 250 provides feedback to controller module 220 regarding the performance of the selected DNN model on each particular HA. In certain embodiments, the feedback is a metric, such as a reward, that is a function of one or more objectives, such as, for example, DNN model size, accuracy, latency, and HA utilization. Additional objectives may include, for example, power efficiency, etc. Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250). The same rationale applies as in claim 1.
Regarding claim 11, Kumar discloses a method of generating a [neural network] comprising: providing one or more technical constraints to a control loop that comprises a [search engine], the one or more technical constraints comprising DNN level latency derived from end-to-end radio access network (RAN) latency, hardware/software resources, and DNN-level accuracy ([0058]: Each named model instance (e.g., a speech to text neural network (NN), etc.) has a set of meta-data fields that defines characteristics of the model instance (e.g. accuracy, latency etc.). [0060]. translates the requirements/parameters into a determination of which available AI model instance is suited (e.g., best suited, better suited, etc.) for the particular request [0078]-[0079], [0126]: telemetry information (e.g., related to the network, one or more edge servers/appliances, other infrastructure telemetry information, etc.) can be used as part of a model query to identify an available model instance to select. Telemetry information can be used to organize models in the example table 350 according to use case, type of function, accuracy, recall, latency, etc. The AI-NF execution logic circuitry 540 can leverage the telemetry circuitry 530 to determine whether one or more models available in the table 350 satisfy requirements and/or other parameters provided in a query for a model/model type); and
generating, using the control loop, a certified [neural network architecture] based on the provided technical constraints ([0058],[0078]-[0079], [0126]: telemetry information (e.g., related to the network, one or more edge servers/appliances, other infrastructure telemetry information, etc.) can be used as part of a model query to identify an available model instance to select. Telemetry information can be used to organize models in the example table 350 according to use case, type of function, accuracy, recall, latency, etc. The AI-NF execution logic circuitry 540 can leverage the telemetry circuitry 530 to determine whether one or more models available in the table 350 satisfy requirements and/or other parameters provided in a query for a model/model type).
However, Kumar does not disclose generating a certified deep neural network (DNN) architecture, comprising: a DNN search engine; and generating, using the control loop, a certified DNN architecture based on the provided technical constraints.
In an analogous art, Loh discloses generating a certified deep neural network (DNN) architecture, comprising: a DNN search engine; and generating, using the control loop, a certified DNN architecture based on the provided technical constraints ([0058]: Generating an optimal DNN model requires navigating through the latency and accuracy characteristics of different DNN elements targeting different heterogeneous components…reinforcement learning is used to search through the DNN elements to maximize the accuracy within provided latency constraints. [0063]: Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250. In certain embodiments, controller module 220 adjusts the DNN model elements, or selects a new DNN model, to maximize the reward. The new or adjusted DNN model is provided to trainer module 230, latency/HA utilization predictor module 240 and feedback generator module 250 for another iteration).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Kumar to comprise “generating a certified deep neural network (DNN) architecture, comprising: a DNN search engine; and generating, using the control loop, a certified DNN architecture based on the provided technical constraints” taught by Loh.
One of ordinary skilled in the art would have been motivated because it would have enabled generating an optimal DNN model require for navigating through the latency and accuracy characteristics of different DNN elements targeting different heterogeneous components (Loh, [0058]).
However, Kumar-Loh does not disclose control loop that comprises a hardware synthesis engine.
In an analogous art, Melodia discloses control loop that comprises a hardware synthesis engine ([0036]: Supervised DRL Model Selection and Bootstrap (S-DMSB) technique that combines concepts from transfer learning and high- level synthesis (HLS) circuit design to select a deep neural network architecture that concurrently (a) satisfies hardware and application throughput constraints and (b) improves the DRL algorithm convergence).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Kumar-Loh to comprise “control loop that comprises a hardware synthesis engine” taught by Melodia.
One of ordinary skilled in the art would have been motivated because it would have enabled selects a neural network model as a function of latency and hardware size constraints (Melodia, [0057]).
Regarding claim 12, Kumar-Loh-Melodia discloses the method of claim 11. Loh discloses further comprising (i) selecting, using the DNN search engine, a candidate DNN architecture based on the technical constraints (Loh, [0058]: Generating an optimal DNN model requires navigating through the latency and accuracy characteristics of different DNN elements targeting different heterogeneous components…reinforcement learning is used to search through the DNN elements to maximize the accuracy within provided latency constraints. [0063]: Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250. In certain embodiments, controller module 220 adjusts the DNN model elements, or selects a new DNN model), the hardware architecture comprises a DNN structure and associated weighting coefficients (Loh, [0069]: a weighted-average ensembling technique is used to weight the output of the HA-specific DNN models).
However, Kumar-Loh does not discloses (ii) generating, using the hardware synthesis engine, a hardware architecture corresponding to the selected candidate DNN architecture.
In an analogous art, Melodia discloses ((ii) generating, using the hardware synthesis engine, a hardware architecture corresponding to the selected candidate DNN architecture ([0036]: Supervised DRL Model Selection and Bootstrap (S-DMSB) technique that combines concepts from transfer learning and high- level synthesis (HLS) circuit design to select a deep neural network architecture that concurrently (a) satisfies hardware and application throughput constraints and (b) improves the DRL algorithm convergence).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Kumar-Loh to comprise “(ii) generating, using the hardware synthesis engine, a hardware architecture corresponding to the selected candidate DNN architecture” taught by Melodia.
One of ordinary skilled in the art would have been motivated because it would have enabled selects a neural network model as a function of latency and hardware size constraints (Melodia, [0057]).
Regarding claims 13 and 14; the claim is interpreted and rejected for the same reason as set forth in claim 6.
Regarding claim 15, Kumar-Loh-Melodia discloses the method of claim 14, further comprising revising, by the DNN search engine using the latency and energy consumption associated with the DNN hardware architecture, the selected DNN architecture to produce the certified DNN architecture (Loh, [0062]-[0063]: Feedback generator module 250 provides feedback to controller module 220 regarding the performance of the selected DNN model on each particular HA. In certain embodiments, the feedback is a metric, such as a reward, that is a function of one or more objectives, such as, for example, DNN model size, accuracy, latency, and HA utilization. Additional objectives may include, for example, power efficiency, etc. Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250). The same rationale applies as in claim 11.
Regarding claim 16, Kumar-Loh-Melodia discloses the method of claim 11, wherein the technical constraints comprise one or more of (i) network latency, (ii) available hardware resources, (iii) available software resources, (iv) required DNN accuracy, (iv) computation and/or network slicing allocation, (v) current noise and/or interference levels at an input of the DNN (Loh, [0058]: DNN elements to maximize the accuracy within provided latency constraints). The same rationale applies as in claim 11.
Regarding claim 17, Kumar-Loh-Melodia discloses the method of claim 11, further comprising producing, by the certified DNN architecture, a certified DNN output based on the certified DNN architecture and a dynamic DNN input, wherein the control loop revises the certified DNN architecture based on the certified output (Loh, [0062]-[0063]: Feedback generator module 250 provides feedback to controller module 220 regarding the performance of the selected DNN model on each particular HA. In certain embodiments, the feedback is a metric, such as a reward, that is a function of one or more objectives, such as, for example, DNN model size, accuracy, latency, and HA utilization. Additional objectives may include, for example, power efficiency, etc. Controller module 220 then adjusts the DNN model elements, or selects a new DNN model, based on the feedback received from the feedback generator module 250). The same rationale applies as in claim 11.
Regarding claim 18, Kumar-Loh-Melodia discloses the method of claim 11, further comprising receiving one or more application-level requirements associated with network communications, and translating the one or more application-level requirements into the one or more technical constraints (Melodia, [0058]: HLS translates a software-defined neural network to an FPGA-compliant circuit, by creating Verilog/VHDL code from code written in C++. The process 400 may begin by training a DNN to classify among G spectrum states (e.g., different SNR levels), such as low, medium, and high SNR, as shown in Fig. 10 (1). Once high accuracy (e.g., 95%) is reached through hyper-parameter exploration, the model is translated with a customized HLS library that generates an HDL description of the DNN in Verilog language (410, 415). Finally, the HDL is integrated with the other circuits in the FPGA and the DNN delay is checked against the requirements (420). In other words, if the model does not satisfy the latency constraint or the model occupies too much space in hardware, the model’s number of parameters are decreased until the constraints are satisfied (2). Once the latency/accuracy trade-off has been reached, the parameters are transferred to the TNN/ONN networks and used as a starting point (“bootstrap”) for the DRL algorithm (3)). The same rationale applies as in claim 11.
Regarding claim 19; the claim is interpreted and rejected for the same reason as set forth in claim 11.
Regarding claim 20; the claim is interpreted and rejected for the same reason as set forth in claim 18.
Additional References
The prior art made of record and not relied upon is considered pertinent to applicants disclosure.
Wang et al., US 2021/0342687 A1: Base Station User Equipment Messaging Regarding Deep Neural Networks.
Restuccia et al., US 2022/0343161 A1: Device and Method for Embedded Deep Reinforcement Learning in Wireless Internet of Things Device.
Blinder et al., US 2023/0186074 A1: Fabricating Data Using Constraints Translated From Trained Machine Learning Models.
Saboori et al., US 2021/0350233 A1: System and Method for Automated Precision Configuration for Deep Neural Networks.
Conclusion
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/J.C.T/Examiner, Art Unit 2446
/MICHAEL A KELLER/Primary Patent Examiner, Art Unit 2446