Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim s 1, 3-4 , 6-8 , 10, and 15 - 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki (U.S. Patent Application Publication 20090200072 A1) , and in further view of Zhang et al (U.S. Patent Application Publication 20170301855 A1) hereinafter Zhang . Regarding claim 1, Yamasaki disclo ses a printed wiring board (Title: Wiring Substrate and Method for Manufacturing the Same) , comprising: a first conductor layer (pad 12 in FIG. 9, ¶ 86) ; a resin insulating layer (insulating layer 13 in FIG. 9, ¶ 87) having an opening (opening 21 in FIG. 9, ¶ 87) extending from a first surface (upper surface 13A of the insulating layer 13 in FIG. 9, ¶ 88) to a second surface (upper surface 11A of the substrate main body 11 in FIG. 9, ¶ 87) of the resin insulating layer and laminated on the first conductor layer ( ¶ 86, “The substrate main body 11 is a substrate on which the pad 12 and insulating layer 13 are to be provided”) ; a second conductor layer (Ni-Cu alloy layer 15, a seed layer 16, a wiring pattern 18, and a wiring 19 in FIG. 9, ¶ 85, a second conductor layer comprises of the layer 15, 16, 18, and 19) formed on the first surface of the resin insulating layer such that the first conductor layer is facing the second surface of the resin insulating layer on an opposite side with respect to the first surface ( ¶ 88, “ The Ni--Cu alloy layer 15 is provided on such portions of the upper surface 13A of the insulating layer 13 that respectively correspond to the forming areas of the wiring pattern 18 and wiring 19, on such portion of the surface of the insulating layer 13 that constitutes the side surface of the opening 21, and on such portion of the upper surface of the pad 12 that constitutes the bottom surface of the opening 21 ”) ; and a via conductor (wiring pattern 18 in FIG. 9, ¶ 96, “the wiring pattern 18 includes a via 23 and a wiring 24 formed integrally with the upper portion of the via 23”) formed in the opening of the resin insulating layer ( ¶ 96, “ The via 23 is provided on the seed layer 16 disposed in an opening 21 ”) such that the via conductor is connecting the first conductor layer and the second conductor layer ( ¶ 96, “ The wiring pattern 18 having the above structure is electrically connected to the pad 21 through the Ni--Cu alloy layer 15 and Cu layer 16 ”) and that the via conductor and the second conductor layer include a seed layer and an electrolytic plating layer formed on the seed layer ( ¶ 95, “ The seed layer 16 is disposed in such a manner that it covers the upper surface of the Ni--Cu alloy layer 15. The seed layer 16 is a power supply layer which is used when forming the wiring pattern 18 and wiring 19 according to an electrolytic plating method ” , the seed layer comprises both the Ni—Cu alloy layer 15 and the seed layer 16 ) , wherein the seed layer includes a metal in a range of 5 wt% to 80 wt% ( ¶ 89, “ The content of Ni contained in the Ni--Cu alloy layer 15, preferably, may be, for example, 20 wt % or more ” ). However, Yamasaki fails to disclose the seed layer being made up of an amorphous metal. Zhang discloses a seed layer that is used in magnetic devices (Title: Novel Composite Seed Layer) wherein the seed layer includes an amorphous metal ( amorphous seed layer in FIG. 10, ¶ 25). Yamasaki discloses the printed wiring board comprising a first conductor, a resin insulating layer with an opening, a second conductor, a via conductor formed in the opening, connecting conductors, and a seed layer with 5-80 wt%. Zhang discloses the seed layer being an amorphous metal. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to use Yamasaki’s printed wiring board and make the seed layer an amorphous seed layer, taught by Zhang, to obtain the claimed range of 5-80 wt%, allowing for manufacturing of a seed layer with greater uniform nucleation for enhanced adhesion and diffusion. Yamasaki also discloses ( ¶ 93) that the alloy layer may be removed such that the pure layer may serve as the seed layer rather than the alloy layer. Therefore, it would naturally be expected that both a pure copper layer and copper alloy mixtures with various elements, whether integrated or due to imperfections during manufacturing, function in a similar matter, retaining their properties of being amorphous, providing alternative compositions in a printed wiring board. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date that the disclosed Cu seed layer 16 can be substituted with a Cu alloy as claimed, namely, a composition used such as the Ni-Cu alloy layer 15. Regarding claim 3, Yamasaki further discloses t he printed wiring board according to claim 1, as detailed above, wherein the seed layer has a first layer and a second layer formed on the first layer such that a material of the second layer is different from a material of the first layer ( ¶ 93 , “ a Cu layer is used as the seed layer 16 (see FIG. 16), there can be removed the Ni--Cu alloy layer 15”, layer 15 is an Ni—Cu alloy layer while the seed layer 16 is a Cu layer) . (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 3 in the same manner for the seed layer using various compositions). Regarding claim 4, Yamasaki further discloses t he printed wiring board according to claim 3, as detailed above, wherein the seed layer is formed such that the first layer has a thickness in a range of 10 nm to 500 nm ( ¶ 94, “the thickness of the Ni-Cu alloy layer 15 can be set, for example, in the range of 30 nm. about. 100 nm”) and that the second layer has a thickness in a range of 10 nm to 1,000 ( ¶ 95, “the thickness of the seed layer 16 can be set, for example, in the range of 300 nm. about. 500 nm”). (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 4 in the same manner for the seed layer using various compositions). Regard ing claim 6, Yamasaki further discloses t he printed wiring board according to claim 3 , as detailed above, wherein the seed layer is formed such that the material of the first layer is a copper alloy ( ¶ 93: “ Ni--Cu alloy layer 15 ”) and that the material of the second layer is a copper alloy ( ¶ 93, “ Cu layer is used as the seed layer 16 (see FIG. 16), there can be removed the Ni--Cu alloy layer 15 ”) that is different from the copper alloy of the first layer . (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 6 in the same manner for the seed layer using various compositions). Regar ding claim 7, Yamasaki further discloses t he printed wiring board according to claim 6, as detailed above. However, Yamasaki fails to disclose the printed wiring board, wherein the copper alloy of the first layer has a copper content of 90 wt% or more and the copper alloy of the second layer has a copper content of 90 wt% or more. As explained in claim 6, supra, the functionality of a pure copper layer and a copper alloy layer is interchangeable as either composition can serve as the seed layer. Yamasaki discloses ( ¶ 89) that “ The content of Ni contained in the Ni--Cu alloy layer 15, preferably, may be, for example, 20 wt % or more ”. Though the alloy composition disclosed contains 0-80 wt% copper, the claimed alloy composition of 90 wt% or greater copper falls between both the disclosed alloy and pure copper seed layers and would still function. (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 7 in the same manner for the seed layer using various compositions). Regardi ng claim 8, Yamasaki further discloses t he printed wiring board according to claim 6 , as detailed above, wherein t he copper alloy of the first layer includes at least one element selected from the group consisting of silicon, aluminum, titanium, nickel, chromium, iron, molybdenum, silver, carbon, oxygen, tin, calcium and magnesium ( ¶ 89, “ The content of Ni contained in the Ni--Cu alloy layer 15, preferably, may be, for example, 20 wt % or more ”) . However, Yamasaki fails to disclose the copper alloy of the second layer includes at least one element selected from the group consisting of silicon, aluminum, titanium, nickel, chromium, iron, molybdenum, silver, carbon, oxygen, tin, calcium and magnesium . As explained in claims 6 and 7, a pure copper layer and a copper alloy layer are interchangeable as they can serve the same function and retain their amorphous properties. One of ordinary skill in the art would understand that the second layer (seed layer 16) from Yamasaki’s disclosure can also be an alloy consisting of at least one of the listed elements, namely, nickel, in a similar manner to the first layer (Ni—Cu alloy layer 15). (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 8 in the same manner). Regarding claim 10, Yamasaki further discloses t he printed wiring board according to claim 3, as detailed above, wherein the material of the first layer includes at least one element selected from the group consisting of aluminum, titanium, nickel, chromium, calcium, magnesium, iron, molybdenum and silver (¶93, “Ni-Cu alloy layer 15”) , and the material of the second layer is copper (¶93, “Cu layer is used as the seed layer 16”) . (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 10 in the same manner for the seed layer using various compositions). Regarding claim 15, Yamasaki further discloses t he printed wiring board according to claim 3, as detailed above, wherein the seed layer is formed such that the material of the first layer is a copper alloy (Ni—Cu alloy layer 15 in FIG. 9, ¶93) and that the material of the second layer is copper (seed layer 16 in FIG. 9, ¶93, “Cu layer is used as the seed layer 16”) . (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 15 in the same manner for the seed layer using various compositions). Regardin g claim 16, Yamasaki further discloses t he printed wiring board according to claim 15 , as detailed above. However, Yamasaki fails to disclose the printed wiring board, wherein the copper alloy of the first layer has a copper content of 90 wt% or more. (In view of the disclosure, please refer to claims 1, 6, and 7, supra, as it is applicable to claim 16 in the same manner for the seed layer using various compositions). Regarding claim 17, Yamasaki further discloses t he printed wiring board according to claim 15, as detailed above, wherein the copper alloy of the first layer includes at least one element selected from the group consisting of silicon, aluminum, titanium, nickel, chromium, iron, molybdenum, silver, carbon, oxygen, tin, calcium and magnesium (Ni—Cu alloy layer 15 in FIG. 9, ¶ 93) . (In view of the disclosure, please refer to claim 1, supra, as it is applicable to claim 17 in the same manner for the seed layer using various compositions). Claim s 2, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki , Zhang , and in further view of Asai et al ( J.P. Patent Application Publication H11214828 A ) hereinafter Asai . Regardin g claim 2, Yamasaki further discloses t he printed wiring board according to claim 1, as detailed above. However, Yamasaki fails to disclose the printed wiring board, wherein the seed layer is a sputtering film. Asai discloses a method and apparatus (Title: Printed Wiring of Board and Manufacture Thereof) of a printed wiring board (printed wiring board, p. 3, ll. 4), wherein the seed layer ( Sn metal coating, p. 9, ll. 15-17, “ A roughened layer 11 consisting of a Cu-Ni-P alloy coating layer and a 2 µm thick needle-like Cu-Ni-P alloy layer is formed, and a 0.3 µm thick Sn metal coating is formed on the surface of the roughened layer 11 ”) is a sputtering film (sputtering, p. 6, ll. 34, “In the case of a noble metal, a method such as sputtering or vapor deposition can be adopted”). Though Yamasaki does not disclose a specific type of method of adding the plurality of layers that form the seed layer onto a given substrate, Yamasaki instead refers to the method of adding said layers by the term “provided”. Asai discloses that a specific method of adding layers onto a given substrate could be done by sputtering a film. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date that the disclosed method of sputtering is a n alternative way of providing a film onto a substrate, allowing for variation in adhesion strength between layers, layer thickness control, and physical properties of layers during manufacturing of a printed wiring board. Also, regarding the limited term of sputtering the seed layer, the applicant is advised that, even though a product-by-process claims were limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method production. If the product in the product-by-process claim is the same as, or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In this case, the cited limitation failed to distinguish the claim structure from the providing the plurality of layers to form the seed layer onto a given substrate of Yamasaki. See MPEP § 2113. “As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith." In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). Regarding claim 18, Yamasaki further discloses the printed wiring board according to claim 2, as detailed above, wherein the seed layer has a first layer and a second layer formed (sputtering; from Asai, p. 6, ll. 34) on the first layer such that a material of the second layer is different from a material of the first layer (¶93, “ a Cu layer is used as the seed layer 16 (see FIG. 16), there can be removed the Ni--Cu alloy layer 15”, layer 15 is an Ni—Cu alloy layer while the seed layer 16 is a Cu layer). (Regarding claim 18, the combination of Yamasaki , Zhang, and Asai further discloses the printed wiring board with a two layer seed layer formed by sputtering, as rejected in claim 2). Regarding claim 19, Yamasaki further discloses the printed wiring board according to claim 18 , as detailed above, wherein the seed layer is formed (sputtering; from Asai, p. 6, ll. 34), such that the first layer has a thickness in a range of 10 nm to 500 nm ( ¶ 94, “the thickness of the Ni-Cu alloy layer 15 can be set, for example, in the range of 30 nm. about. 100 nm”) and that the second layer has a thickness in a range of 10 nm to 1,000 ( ¶ 95, “the thickness of the seed layer 16 can be set, for example, in the range of 300 nm. about. 500 nm”) . (Regarding claim 18, the combination of Yamasaki, Zhang, and Asai further discloses the printed wiring board with a two-layer seed layer formed by sputtering, as rejected in claim 2). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki , Zhang , and in further view of Nishimura et al (U.S. Patent Application Publication 20200281076 A1 ) hereinafter Nishimura . Regar ding claim 5, Yamasaki further discloses t he printed wiring board according to claim 1, as detailed above . However, Yamasaki fails to disclose t hat t he resin insulating layer formed has an arithmetic mean roughness Ra in a range of 0.02 μm to 0.08 μm. Nishimura discloses a method and apparatus (Title: High-Frequency Circuit Laminate and Method for Producing Same, and B-Stage Sheet ) of a printed wiring board ( printed wiring board , ¶ 3 ), wherein the resin insulating layer is formed such that the first surface has an arithmetic mean roughness Ra in a range of 0.02 μm to 0.08 μm ( ¶ 104 , “ The surface roughness Ra of the exposed resin layer surface 23 is preferably from 1 to 100 nm ”) . Yamasaki discloses that the insulating layer 13 is provided onto the substrate main body 11, but does not mention the physical properties, roughness, of the first surface. Nishimura does however disclose the physical properties, roughness, of the surface of the exposed resin layer surface 23, detailing that it has an Ra range of 1 to 100 nm. Thus, it would have been obvious that one of ordinary skill in the art before the effective filing date would understand that Nishimura’s disclosed surface roughness may be applied to Yamasaki’s printed wiring board, allowing for variations of improvements in adhesion between the resin layer and the metal layers to be achieved. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki , Zhang , and in further view of Takada et al ( U.S. Patent Application Publication 20200091104 A1 ) hereinafter Takada. Regardin g claim 9, Yamasaki further discloses t he printed wiring board according to claim 3 , as detailed above, wherein the material of the second layer is copper ( ¶ 93, “ Cu layer is used as the seed layer 16 ”) . Yamasaki does disclose the first layer being a copper alloy. However, Yamasaki fails to disclose the printed wiring board, wherein the material of the first layer is a copper alloy including aluminum and silicon . Takada discloses an apparatus and method (Title: Multilayer Wiring Board, Electronic Device and Method for Producing Multilayer Wiring Board) of a printed wiring board (multilayer wiring board, ¶ 56), wherein the material of the first layer is a copper alloy including aluminum and silicon ( ¶ 158, “ Examples of the Sn or Sn alloy included in the conductive paste include a simple substance of Sn and alloys containing Sn and at least one selected from the group consisting of Cu, Ni, Ag, Au, Sb, Zn, Bi, In, Ge, Al, Co, Mn, Fe, Cr, Mg, Mn, Pd, Si, Sr, Te, and P ”). While Yamasaki, in view of Zhang, discloses the printed wiring board wherein the material of the first layer is a copper alloy and a second layer made up of copper, Takada further discloses a copper alloy consisting of several other elements, a copper alloy including aluminum and silicon. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize other elements and integrate them into the copper alloy to achieve an alloy with various arithmetic mean particle sizes to alter production costs, oxidation and reactions, and ease of filling the via hole with conductive pastes ( ¶ 161). Claims 11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki , Zhang , and in further view of Funaya et al (U.S. Patent Application Publication 20110155433 A1) hereinafter Funaya. Regarding claim 11, Yamasaki further discloses t he printed wiring board according to claim 1, as detailed above, further comprising : a conductor layer that includes a seed layer not containing an amorphous metal ( ¶ 93, “ Cu layer is used as the seed layer 16 ”) , a seed layer comprising an amorphous metal in a range of 5 wt% to 80 wt% ( ¶ 93, “Ni—Cu alloy layer 15 is set in the range of 20 wt%. about.75 wt% ; also see rejection of claim 1, supra, for the reason to use various Ni-Cu alloy compositions ), and an electrolytic plating layer formed on the seed layer ( ¶ 95, “ The seed layer 16 is a power supply layer which is used when forming the wiring pattern 18 and wiring 19 according to an electrolytic plating method ”) . However, Yamasaki fails to disclose there being a plurality of insulating layers and a plurality of conductor layers comprising a plurality of first type conductor layers and a plurality of second type conductor layers . Yamasaki also fails to disclose there being a first and second conductor, a first and second seed layer, and a first and second electrolytic planting layer such that all of the listed layers (first conductor layer, second conductor layer, resin insulating layer, plurality of insulating layers, and plurality of conductor layers) may be formed in a build-up layer. Funaya discloses an apparatus and method (Title: Wiring Board Capable of Containing Functional Element and Method for Manufacturing Same) of a printed wiring board (wiring board, ¶ 32) comprising : A plurality of insulating layers (insulating resin layers 21 and 22 in Fig. 15 below , ¶ 119); and A plurality of conductor layers (plurality of conductor wiring layers, ¶ 119) comprising a plurality of first type conductor layers (first conductor wiring layer 3 in FIG. 3C , ¶ 87 ) and a plurality of second type conductor layers (second conductor wiring layer 4 in FI G. 3C , ¶ 87 ), wherein each of the first type conductor layers includes a first type seed layer (seed layer 55 in FIG. 3C , ¶ 75) not containing an amorphous metal ( as disclosed by Yamasaki) , and a first type electrolytic plating layer formed on the first type seed layer ( electrolytic plating, ¶ 16, also as disclosed by Yamasaki ) , each of the second type conductor layers includes a second type seed layer (seed layer 55 in Fig. 3C , ¶ 75, Though Funaya does not disclose the term “second seed layer”, a seed layer is understandably provided before the second con ductor wiring layers ) comprising an amorphous metal in a range of 5 wt% to 80 wt% (Yamasaki) , and a second type electrolytic plating layer formed on the second type seed layer (electrolytic plating, ¶ 16, Though Funaya does not disclose the term “second type electrolytic planting layer”, it is understandably provided after the second seed layer) , the second conductor layer includes the second type seed layer and the second type electrolytic plating layer formed on the second type seed layer, and the first conductor layer, the second conductor layer, the resin insulating layer, the plurality of insulating layers and the plurality of conductor layers form a build-up layer ( ¶ 73, “ a build-up method can be applied to the wiring board relating to the present invention in order to create a multilayer wiring by alternately forming insulating layers and conductor wiring layers on both surfaces and wiring the conductor wiring layers using a via ”) . Yamasaki discloses a printed wiring board, but does not teach that the method can be used to facilitate a plurality of layers in a stacked configuration . Funaya’s disclosure is of a printed wiring board, explaining how these layers may be stacked and having the electrical seed layers be connected using a via between pluralities of printed wiring board layers . Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date that to stack the plurality of conductive layers would allow for higher current carrying capacities. Regarding claim 13, Funaya further discloses t he printed wiring board according to claim 11, as detailed above, wherein each of the first type conductor layers includes a plurality of first conductor circuits, and each of the second type conductor layers includes a plurality of second conductor circuits such that each of the second conductor circuits has a second width that is smaller than a first width of each of the first conductor circuits and that a second distance between two adjacent second conductor circuits is smaller than a first distance between two adjacent first conductor circuits ( ¶ 67, “the line width and distance between lines (line/space) of the wiring is not greater than 15 μm /15 μm ”, annotated FIG. 15 also depicts the first width and distance to be greater than the second width and distance, as claimed in claim 13 ) . (Regarding the rationale for combination of references, please refer to claim 11, supra, as it is applicable to claim 13 in the same manner). Regarding claim 14, Funaya further discloses t he printed wiring board according to claim 13 , as detailed above, wherein the first and second type conductor layers are formed such that the first width is in a range of 8 μm to 12 μm, the second width is in a range of 2 μm to 8 μm, the first distance is in a range of 9 μm to 13 μm, and the second distance is in a range of 3 μm to 10 μm . ( ¶ 67, “the line width and distance between lines (line/space) of the wiring is not greater than 15 μm /15 μm ”, Funaya discloses that both the widths and distances of a conductor circuit may be less than 15 micrometers). (Regarding the rationale for combination of references as well as explanation for disclosed widths and distances between conductor circuits , please refer to claim s 11 and 13 , supra, as it is applicable to claim 14 in the same manner). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki , in view of Zhang and Funaya, and further in view of Asai. Regardi ng claim 12, Yamasaki in view of Funaya teaches the printed wiring board according to claim 11, as detailed above. However, both Yamasaki and Funaya don’t disclose the printed wiring board wherein the first type seed is an electroless plating film. Asai teaches that the first type seed is an electroless plating film (electroless plating film, p. 2, ll. 23-24), and the second type seed layer is a sputtering film (sputtering, p. 6, ll. 34) . One of skill in the art would understand that both manners of providing the film are alternative methods to adding layers onto a printed wiring board, allowing for variation in film layer physical properties. (Regarding the rationale for combination of references, please refer to claims 2 and 11, supra, as it is applicable to claim 12 in the same manner). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki in view of Zhang and Asai, and further in view of Nishimura . Regarding claim 20, Yamasaki in view of Asai teaches the wiring board according to claim 2, as detailed above. However, both Yamasaki and Asai don’t disclose the wiring board wherein the resin insulating layer is formed such that the first surface has an arithmetic mean roughness Ra in a range of 0.02 μm to 0.08 μ m. Nishimura further teaches that the printed wiring board , wherein the resin insulating layer is formed such that the first surface has an arithmetic mean roughness Ra in a range of 0.02 μm to 0.08 μ m ( ¶ 104, “The surface roughness Ra of the exposed resin layer surface 23 is preferably from 1 to 100 nm”) . (Regarding the rationale for combination of references, please refer to claims 2 and 5, supra, as it is applicable to claim 20 in the same manner). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT EUGENE REY D LEGASPI whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-2956 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 8-5PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Thomas Hong can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-0993 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.D.L./ Examiner, Art Unit 3729 /THOMAS J HONG/ Supervisory Patent Examiner, Art Unit 3729