Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/11/2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 11, 15 – 19, 20, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Holenstein (US 20140213209 A1).
Regarding Independent Claim 1, Holenstein teaches,
An amplification circuit (Fig. 7A, 730a), comprising:
a first amplification path (Fig. 7A, path from RFin to RFamp1 through 744) comprising a first amplification transistor (Fig. 7A, 744) and coupled between an input node of the amplification circuit (Fig. 7A, RFin) and an output node of the amplification circuit (Fig. 7A, RFamp1); and
a second amplification path (Fig. 7A, path from RFin to RFamp1 through 764) coupled between the input node and the output node of the amplification circuit (Fig. 7A, RFin and RFamp1) and comprising a second amplification transistor (Fig. 7A, 764) and an attenuator (Fig. 7A, 762) coupled between the input node of the amplification circuit (Fig. 7A, RFin) and a control input of the second amplification transistor (Fig. 7A, gate terminal of 764).
Regarding claim 2,
The amplification circuit of claim 1, wherein the attenuator (Figs. 7A and 9, 762) comprises a first resistive element (Fig. 9, R1) coupled in series between the input node (Fig. 7A, RFin) and the control input of the second amplification transistor (Fig. 7A, gate terminal of 764).
Regarding claim 3,
The amplification circuit of claim 2, wherein the attenuator (Figs. 7A and 9, 762) further comprises an attenuation transistor (Fig. 9, 914) coupled between the first resistive element (Fig. 9, R1) and a reference potential node.
Regarding claim 4,
The amplification circuit of claim 3, wherein the attenuator (Figs. 7A and 9, 762) further comprises a second resistive element (Fig. 9, R2) coupled between the first resistive element (Fig. 9, R1) and the reference potential node.
Regarding claim 5,
The amplification circuit of claim 3, further comprising a bias circuit (Fig. 7A, 720) coupled to a control input of the attenuation transistor (Fig. 7A, 720 is coupled to 762).
Regarding claim 6,
The amplification circuit of claim 5, wherein the bias circuit (Fig. 7A, 720) comprises a bias transistor (Fig. 7A, 724) coupled between a voltage rail and the control input of the attenuation transistor, a control input of the bias transistor being coupled to a current source (Fig. 7A, 726).
Regarding claim 7,
The amplification circuit of claim 5, wherein the attenuation transistor includes a heterojunction bipolar transistor (HBT) [See paragraph [0101], “The amplifiers may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.”].
Regarding claim 8,
The amplification circuit of claim 3, wherein the attenuation transistor (Fig. 9, 914) is on a same semiconductor die [See paragraph [0101], “The amplifiers (e.g., LNAs) with independent gain control per output described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronic device, etc.”] as the first amplification transistor (Fig. 7, 744), and wherein the attenuation transistor (Fig. 9, 914) and the first amplification transistor (Fig. 7, 744) are gallium arsenide (GaAs) transistors [See paragraph [0101], “The amplifiers may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.”].
Regarding claim 9,
The amplification circuit of claim 1, wherein:
the first amplification path (Fig. 7A, path from RFin to RFamp1 through 744) includes a first driver amplifier (DA) segment (Fig. 5, 570a) comprising the first amplification transistor;
the second amplification path includes a second DA segment (Fig. 5, 570b) comprising the second amplification transistor; and
the amplification circuit further comprises a power amplifier (PA) (Fig. 5, 530) having an input coupled to outputs of the first DA segment and the second DA segment (Fig. 5, 530).
Regarding claim 10,
The amplification circuit of claim 1, further comprising:
a first bias circuit (Fig. 9, R1 in series with 912 and 920 in order to separate the respective inherent bias voltage circuits for 744 and 764) coupled to a control input of the first amplification transistor; and
a second bias circuit (Fig. 9, R1 in series with 912 and 920 in order to separate the respective inherent bias voltage circuits for 744 and 764) coupled to the control input of the second amplification transistor.
[See paragraph [0083], “Within programmable attenuator 762, AC coupling capacitors 912 and 920 pass the input RF signal while avoiding disturbing the bias voltages of gain transistors coupled to the input and/or output of programmable attenuator 762.”].
Regarding claim 11,
The amplification circuit of claim 10, wherein:
the first bias circuit [See paragraph [0063], “For cascode-level signal splitting shown in FIG. 7A, the input RF signal may be amplified by gain transistor 744 and split by cascode transistors 746 and 756 to generate up to two amplified RF signals for up to two load circuits. Cascode transistor 746 may be enabled to generate the RFamp1 signal in the HG mode, the HG-HG mode, or the HG-LG mode. Cascode transistor 756 may be enabled to generate the RFamp2 signal in the HG mode, the HG-HG mode, or the HG-LG mode.”] is configured to bias the first amplification transistor based on the amplification circuit operating in a high-power mode (HPM); and
the second bias circuit [See paragraph [0063], “Similarly, the input RF signal may be amplified by gain transistor 764 and split by cascode transistors 766 and 776 to generate up to two amplified RF signals for up to two load circuits. Cascode transistor 766 may be enabled to generate the RFamp1 signal in the LG mode, the HG-LG mode, or the LG-LG mode. Cascode transistor 776 may be enabled to generate the RFamp2 signal in the LG mode, the LG-HG mode, or the LG-LG mode.”] is configured to bias the second amplification transistor based on the amplification circuit operating in a low-power mode (LPM).
Regarding Independent claim 15, Holenstein teaches,
A method for signal amplification, comprising:
determining a power mode [See paragraph [0063], “For cascode-level signal splitting shown in FIG. 7A, the input RF signal may be amplified by gain transistor 744 and split by cascode transistors 746 and 756 to generate up to two amplified RF signals for up to two load circuits. Cascode transistor 746 may be enabled to generate the RFamp1 signal in the HG mode, the HG-HG mode, or the HG-LG mode. Cascode transistor 756 may be enabled to generate the RFamp2 signal in the HG mode, the HG-HG mode, or the HG-LG mode. Similarly, the input RF signal may be amplified by gain transistor 764 and split by cascode transistors 766 and 776 to generate up to two amplified RF signals for up to two load circuits. Cascode transistor 766 may be enabled to generate the RFamp1 signal in the LG mode, the HG-LG mode, or the LG-LG mode. Cascode transistor 776 may be enabled to generate the RFamp2 signal in the LG mode, the LG-HG mode, or the LG-LG mode.”] for an amplification circuit (Fig. 7A, 730a);
selecting a first amplification path (Fig. 7A, path from RFin to RFamp1 through 744) or a second amplification path (Fig. 7A, path from RFin to RFamp1 through 764) based on the determined power mode, wherein the first amplification path (Fig. 7A, path from RFin to RFamp1 through 744) includes a first amplification transistor (Fig. 7A, 744) coupled to an output node of the amplification circuit, and wherein the second amplification path (Fig. 7A, path from RFin to RFamp1 through 764) includes a second amplification transistor (Fig. 7A, 764) coupled to the output node and an attenuator (Fig. 7A, 762) coupled to a control input of the second amplification transistor; and
amplifying an input signal (Fig. 7A, RFin) via the first amplification path (Fig. 7A, path from RFin to RFamp1 through 744) or the second amplification path (Fig. 7A, path from RFin to RFamp1 through 764) based on the selection.
Regarding claim 16,
The method of claim 15, further comprising:
attenuating, via the attenuator (Fig. 7A, 762), the input signal (Fig. 7A, RFin) to yield an attenuated signal (Fig. 7A, signal from 762); and
amplifying the attenuated signal with the second amplification transistor (Fig. 7A, 764).
Regarding claim 17,
The method of claim 16, further comprising:
determining a level of attenuation associated with the attenuator (Fig. 7A, 762);
generating, via a bias circuit (Fig. 9, R1 in series with 912 and 920 in order to separate the respective inherent bias voltage circuits for 744 and 764), a bias signal for an attenuation transistor (Fig. 9, 914) of the attenuator based on the level of attenuation, wherein the attenuator (Fig. 7A, 762) includes a resistive element (Fig. 9, R1) coupled in series between an input node of the amplification circuit and the control input of the second amplification transistor, the attenuation transistor (Fig. 9, 914) being coupled between the resistive element and a reference potential node; and
biasing the attenuation transistor (Fig. 9, 914) with the bias signal.
Regarding claim 18,
The method of claim 17, wherein:
the bias circuit (Fig. 7A, 720) comprises a bias transistor (Fig. 7A, 724) coupled between a voltage rail and a control input of the attenuation transistor (Fig. 9, 914); and
generating the bias signal (Fig. 7A, signal from 720) includes sourcing, via a current source (Fig. 7A, 726), a current to a control input of the bias transistor.
Regarding claim 19,
The method of claim 17, wherein the attenuation transistor includes a heterojunction bipolar transistor (HBT) [See paragraph [0101], “The amplifiers may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.”].
Regarding claim 20,
The method of claim 15, further comprising:
biasing, via a first bias circuit [See paragraph [0063], “For cascode-level signal splitting shown in FIG. 7A, the input RF signal may be amplified by gain transistor 744 and split by cascode transistors 746 and 756 to generate up to two amplified RF signals for up to two load circuits. Cascode transistor 746 may be enabled to generate the RFamp1 signal in the HG mode, the HG-HG mode, or the HG-LG mode. Cascode transistor 756 may be enabled to generate the RFamp2 signal in the HG mode, the HG-HG mode, or the HG-LG mode.”], the first amplification transistor based on the determined power mode being a high-power mode (HPM); or
biasing, via a second bias circuit, the second amplification transistor based on the determined power mode being a low-power mode (LPM).
Regarding Independent claim 22, Holenstein teaches,
An apparatus for signal amplification (Fig. 7A, 730a), comprising:
first means for amplifying an input signal (Fig. 7A, RFin) at an input node (Fig. 7A, RFin node), the first means for amplifying being coupled between the input node and an output node (Fig. 7A, path from RFin to RFamp1 through 744);
means for attenuating (Fig. 7A, 762) the input signal to yield an attenuated signal (Fig. 7A, signal from 762), the means for attenuating being coupled to the input node; and
second means for amplifying the attenuated signal (Fig. 7A, signal from 762), the second means for amplifying being coupled between the means for attenuating and the output node (Fig. 7A, path from RFin to RFamp1 through 764).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Holenstein in view of Kondo et al. (US 20190190455 A1), hereinafter Kondo.
Regarding claim 12, Holenstein is silent regarding:
The amplification circuit of claim 10, wherein:
the first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplification transistor, a control input of the first bias transistor being coupled to a first current source; and
the second bias circuit includes a second bias transistor coupled between the voltage rail and a control input of the second amplification transistor, a control input of the second bias transistor being coupled to a second current source.
Kondo discloses:
the first bias circuit (Fig. 5, 150A) includes a first bias transistor (Fig. 5, Q6) coupled between a voltage rail and a control input of the first amplification transistor (Fig. 5, Q7b), a control input of the first bias transistor (Fig. 5, 150A) being coupled to a first current source (Fig. 5, inherent current source from 140); and
the second bias circuit (Fig. 5, 150B) includes a second bias transistor (Fig. 5, Q9) coupled between the voltage rail and a control input of the second amplification transistor (Fig. 5, Q7b), a control input of the second bias transistor being coupled to a second current source (Fig. 5, inherent current source from 140).
Holenstein and Kondo are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a second bias circuit in Holenstein‘s design in order to optimize performance for dual-band or high-frequency applications in accordance with Kondo‘s design.
Regarding claim 14, Holenstein is silent regarding:
The amplification circuit of claim 1, further comprising:
a first capacitive element coupled between the input node and a control input of the first amplification transistor; and
a second capacitive element coupled between the input node and the control input of the second amplification transistor.
Kondo discloses:
a first capacitive element (Fig. 5, C1) coupled between the input node and a control input of the first amplification transistor (Fig. 5, Q1); and
a second capacitive element (Fig. 5, C2) coupled between the input node and the control input of the second amplification transistor (Fig. 5, Q2).
Holenstein and Kondo are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a capacitive element in Holenstein‘s design in order to couple the transistors respectively in accordance with Kondo‘s design.
Regarding claim 21, Holenstein is silent regarding:
The method of claim 20, wherein:
the first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplification transistor, a control input of the first bias transistor being coupled to a current source;
the second bias circuit includes a second bias transistor coupled between the voltage rail and a control input of the second amplification transistor, a control input of the second bias transistor being coupled to the current source; and
the method further comprises selectively coupling the current source to the first bias transistor or the second bias transistor based on the power mode.
Kondo discloses:
the first bias circuit (Fig. 5, 150A) includes a first bias transistor (Fig. 5, Q6) coupled between a voltage rail and a control input of the first amplification transistor (Fig. 5, Q7b), a control input of the first bias transistor (Fig. 5, 150A) being coupled to a current source (Fig. 5, inherent current source from 140);
the second bias circuit (Fig. 5, 150B) includes a second bias transistor (Fig. 5, Q9) coupled between the voltage rail and a control input of the second amplification transistor (Fig. 5, Q7b), a control input of the second bias transistor being coupled to the current source (Fig. 5, inherent current source from 140);
the method further comprises selectively coupling the current source (Fig. 5, inherent current source from 140) to the first bias transistor (Fig. 5, 150A) or the second bias transistor (Fig. 5, 150B) based on the power mode.
Holenstein and Kondo are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a second bias circuit in Holenstein‘s design in order to optimize performance for dual-band or high-frequency applications in accordance with Kondo‘s design.
Claims 13 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Holenstein in view of Wohlfarth et al. (US 5999044 A), hereinafter Wohlfarth.
Regarding claim 13, Holenstein is silent regarding:
The amplification circuit of claim 12, wherein the first current source and the second current source comprise a same current source selectively coupled to the control input of the first bias transistor or the control input of the second bias transistor.
Wohlfarth discloses:
The amplification circuit of claim 12, wherein the first current source and the second current source comprise a same current source (Fig. 3, switch controlled by RANGE signal being coupled to the current source as a bias selective element) selectively coupled to the control input of the first bias transistor or the control input of the second bias transistor.
Holenstein and Wohlfarth are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a same current source being selectively coupled in Holenstein‘s design in order to have a switch that functions as a selective element for the current source in accordance with Wohlfarth‘s design.
Regarding claim 23, Holenstein discloses:
The apparatus of claim 22, further comprising:
means for determining a power mode for the apparatus [See paragraph [0063], “For cascode-level signal splitting shown in FIG. 7A, the input RF signal may be amplified by gain transistor 744 and split by cascode transistors 746 and 756 to generate up to two amplified RF signals for up to two load circuits. Cascode transistor 746 may be enabled to generate the RFamp1 signal in the HG mode, the HG-HG mode, or the HG-LG mode. Cascode transistor 756 may be enabled to generate the RFamp2 signal in the HG mode, the HG-HG mode, or the HG-LG mode. Similarly, the input RF signal may be amplified by gain transistor 764 and split by cascode transistors 766 and 776 to generate up to two amplified RF signals for up to two load circuits. Cascode transistor 766 may be enabled to generate the RFamp1 signal in the LG mode, the HG-LG mode, or the LG-LG mode. Cascode transistor 776 may be enabled to generate the RFamp2 signal in the LG mode, the LG-HG mode, or the LG-LG mode.”]; and
means for selecting the first means for amplifying the input signal or the second means for amplifying the attenuated signal based on the determined power mode.
Holenstein is silent regarding:
means for selecting the first means for amplifying the input signal or the second means for amplifying the attenuated signal based on the determined power mode.
Wohlfarth discloses:
means for selecting (Fig. 3, switch controlled by RANGE signal being coupled to the current source as a bias selective element) the first means for amplifying the input signal or the second means for amplifying the attenuated signal based on the determined power mode.
Holenstein and Wohlfarth are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a same current source being selectively coupled in Holenstein‘s design in order to have a switch that functions as a selective element for the current source in accordance with Wohlfarth‘s design.
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843