DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The action is in response to the application filed on 6/21/2023. Claims 1-17 are pending and have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/30/2024 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claim 14 is objected to because of the following informalities: “FGPA” should be “FPGA”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1:
Claim 1 recites the limitation "combined with a dimension of the feature vector " in line 12. There is insufficient antecedent basis for this limitation in the claim. There is no feature vector before line 12 in this claim.
Regarding Claims 2-6:
Claims 2-6 are rejected as being dependent on a rejected base claim without curing any of the deficiencies.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 1:
Step 1:
The claim recites a method, which is one of the four statutory categories of patentable subject matter.
Step 2A prong 1:
The claim recites an abstract idea mapping each of a plurality of discrete values… to a plurality of instances of binary code which amounts to a mental process as it can be performed in a human mind.
The claim recites an additional abstract idea stacking a plurality of value vectors associated with one or more of the plurality of discrete values associated with one or more instances of binary code, such a dimension of the stacked plurality of value vectors matches the dimension of the plurality of value vectors combined with a dimension of the feature vector which amounts to a mental process as it can be performed in a human mind.
The claim recites an additional abstract idea performing a matrix multiplication of the stacked value vectors and the feature vector to produce a sample vector which is a mathematical concept.
The claim recites an additional abstract idea generating a comparison result by comparing the sample vector against the plurality of predefined class vectors for similarity checking which amounts to a mental process as it can be performed in a human mind.
The claim recites an additional abstract idea classifying the sample vector based on the comparison results associated with the similarities between the sample vector and the plurality of predefined class vectors which amounts to a mental process as it can be performed in a human mind.
Step 2A prong 2:
The additional element of a circuit is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of an item memory, said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values, and a feature memory configured to store a plurality of query feature positions that are associated with the plurality of binary vectors in the value memory is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of an associative memory configured to store a plurality of predefined class vectors is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of …loaded from the value memory… does not integrate the abstract idea into practical application because storing and retrieving data from memory is considered an insignificant extra solution activity of MPEP 2106.05(g).
Step 2B:
The additional element of a circuit is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of an item memory, said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values, and a feature memory configured to store a plurality of query feature positions that are associated with the plurality of binary vectors in the value memory is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of an associative memory configured to store a plurality of predefined class vectors is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of …loaded from the value memory… does not amount to significantly more because the additional element is an insignificant extra solution activity and further is a well understood routine and conventional activity. See MPEP 2106.05(d)(II)(iv), (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015))
Therefore, the claim is ineligible.
Regarding Claim 2:
Claim 2 which incorporates the rejection of Claim 1, recites further abstract ideas defining a neural network comprising a value layer, a feature layer, and a class layer and defining a sample vector as a product of binding the feature vector and the stacked value vectors which are mental processes as they can be performed in a human mind. This claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. Specifically, the claim recites extracting a plurality of value vectors by inputting a plurality of values to the value layer that converts feature values to bipolar value vectors, and recording output of the value layer which is an insignificant extra solution activity of “mere data gathering” MPEP 2106.05(g) and further is a well understood routine and conventional activity, see MPEP 2106.05(d)(II)(i), (buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network)).
The claim additionally recites extracting a plurality of feature vectors by recording a binary weight associated with each of the plurality of feature vectors in the feature layer, where said plurality of feature vectors have the same dimension as the value vectors and extracting a plurality of class vectors by recording a binary weight associated with each of the plurality of class vectors in the class layer, where said plurality of class vectors have the same dimension as the plurality of value vectors and the plurality of feature vectors which are insignificant extra solution activities of storing and retrieving data from memory MPEP 2106.05(g) and further are well understood routine and conventional activities, see MPEP 2106.05(d)(II)(iv), (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015)). The claim is ineligible.
Regarding Claim 3:
Claim 3 incorporates the rejection of Claim 1. The claim further recites a description of the circuit from Claim 1 and is ineligible for the same reasons as set forth in Claim 1. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 4:
Claim 4 incorporates the rejection of Claim 1. The claim further recites a description of the circuit from Claim 1 and is ineligible for the same reasons as set forth in Claim 1. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 5:
Claim 5 incorporates the rejection of Claim 1. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. Specifically, the claim recites mapping each of the plurality of discrete values associated with the feature vector to a plurality of instances of binary code, is performed by a trainable binary neural network which is generally linked to the abstract idea MPEP 2106.05(h). The claim is ineligible.
Regarding Claim 6:
Claim 6 incorporates the rejection of Claim 5. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. Specifically, the claim recites wherein the binary neural network is trained to optimize the organization of the plurality of instances of binary code by converting the value vectors to a low vector dimension which is generally linked to the abstract idea MPEP 2106.05(h). The claim is ineligible.
Regarding Claim 7:
Step 1:
The claim recites a method, which is one of the four statutory categories of patentable subject matter.
Step 2A prong 1:
The claim recites an abstract idea encoding a class vector for a class of data… encoding the class of data with feature vectors and with value vectors which amounts to a mental process as it can be performed in a human mind.
The claim recites an additional abstract idea calculating a class vector by averaging each of a plurality of hypervectors within the class which is a mathematical concept.
Step 2A prong 2:
The additional element by a processor coupled with an associative memory are generic computer components amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element …the vector being determined by collecting a class of data… does not integrate the abstract idea into practical application because storing and retrieving data from memory is considered an insignificant extra solution activity of MPEP 2106.05(g).
The additional element storing the class vectors in the associative memory does not integrate the abstract idea into practical application because storing and retrieving data from memory is considered an insignificant extra solution activity of MPEP 2106.05(g).
Step 2B:
The additional element by a processor coupled with an associative memory are generic computer components amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element …the vector being determined by collecting a class of data… does not amount to significantly more because the additional element is an insignificant extra solution activity and further is a well understood routine and conventional activity. See MPEP 2106.05(d)(II)(iv), (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015))
The additional element storing the class vectors in the associative memory does not amount to significantly more because the additional element is an insignificant extra solution activity and further is a well understood routine and conventional activity. See MPEP 2106.05(d)(II)(iv), (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015)).
Therefore, the claim is ineligible.
Regarding Claim 8:
Claim 8 incorporates the rejection of Claim 7. The claim further recites a description of the class of data from Claim 7 and is ineligible for the same reasons as set forth in Claim 7. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 9:
Claim 9 which incorporates the rejection of Claim 7, recites a further abstract idea discarding all non-binary weight associated with the extracted value vectors which is a mental process as it can be performed in a human mind. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 10:
Claim 10 which incorporates the rejection of Claim 7, recites a further abstract idea extracting the class vectors from a set of optimized class weight parameters which is a mental process as it can be performed in a human mind. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 11:
Step 1:
The claim recites a system, which is one of the four statutory categories of patentable subject matter.
Step 2A prong 1:
The claim recites an abstract idea map a plurality of discrete values associated with a feature vector which amounts to a mental process as it can be performed in a human mind.
The claim recites an additional abstract idea stack a plurality of value vectors associated with one or more of the plurality of discrete values associated with one or more instances of binary code, such a dimension of the stack of plurality of value vectors matches the dimension of the plurality of value vectors combined with a dimension of the feature vector which amounts to a mental process as it can be performed in a human mind.
The claim recites an additional abstract idea compare a sample vector to each of a plurality of predefined class vectors by performing a matrix multiplication, the sample vector being a product of binding the feature vector and the stacked plurality of value vectors which is a mathematical concept.
The claim recites an additional abstract idea identifying a respective value associated with similarity between the sample vector and each of the plurality of class vectors which amounts to a mental process as it can be performed in a human mind.
The claim recites an additional abstract idea classifying the sample vector based on the maximum value associated with similarity with the plurality of predefined class vectors a mental process as it can be performed in a human mind.
Step 2A prong 2:
The additional element of a circuit is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of an item memory, said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values, and a feature memory configured to store a plurality of query feature positions that are associated with the plurality of binary vectors in the value memory is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of an associative memory configured to store a plurality of predefined class vectors is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
Step 2B:
The additional element of a circuit is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of an item memory, said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values, and a feature memory configured to store a plurality of query feature positions that are associated with the plurality of binary vectors in the value memory is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of an associative memory configured to store a plurality of predefined class vectors is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
Therefore, the claim is ineligible.
Regarding Claim 12:
Step 1:
The claim recites a method, which is one of the four statutory categories of patentable subject matter.
Step 2A prong 1:
The claim recites an abstract idea comparing the sample vector to a plurality of class vectors of a class layer, the comparison of the sample vector to the plurality of class vectors resulting in respective comparison scores for each comparison which amounts to a mental process as it can be performed in a human mind.
Step 2A prong 2:
The additional element of a circuit is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of an item memory, said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values, and a feature memory configured to store a plurality of query feature positions is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of an associative memory configured to store a plurality of predefined class vectors is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not integrate the abstract idea into practical application MPEP 2106.05(f).
The additional element of outputting the comparison scores for classification as an inference label does not integrate the abstract idea into practical application because outputting data is considered an insignificant extra solution activity of “mere data gathering” MPEP 2106.05(g)
Step 2B:
The additional element of a circuit is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of an item memory, said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values, and a feature memory configured to store a plurality of query feature positions is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of an associative memory configured to store a plurality of predefined class vectors is a generic computer component amounting to mere instructions to apply the abstract idea, therefore does not amount to significantly more MPEP 2106.05(f).
The additional element of outputting the comparison scores for classification as an inference label does not amount to significantly more because the additional element is an insignificant extra solution activity and further is a well understood routine and conventional activity. See MPEP 2106.05(d)(II)(i), (buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network)).
Therefore, the claim is ineligible.
Regarding Claim 13:
Claim 13 which incorporates the rejection of Claim 12, recites a further abstract idea multiplying each feature vector with each value vector; and accumulating the result of the multiplying, the accumulation resulting in the sample vector which is a mathematical concept. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 14:
Claim 14 incorporates the rejection of Claim 13. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. Specifically, the claim recites wherein the multiplying and accumulating are performed by an FPGA which amounts to mere instructions to apply abstract idea MPEP 2106.05(f). The claim is ineligible.
Regarding Claim 15:
Claim 15 which incorporates the rejection of Claim 12, recites a further abstract idea multiplying the sample vector with each class vector; and averaging the result of the multiplication to a scalar which is a mathematical concept. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 16:
Claim 16 incorporates the rejection of Claim 12. The claim further recites a description of the value memory, associative memory and feature memory from Claim 12 and is ineligible for the same reasons as set forth in Claim 12. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Regarding Claim 17:
Claim 17 incorporates the rejection of Claim 12. The claim further recites a description of the circuit from Claim 12 and is ineligible for the same reasons as set forth in Claim 12. The claim does not recite any additional elements that integrate the abstract idea into practical application or amount to significantly more. The claim is ineligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-13, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsiao et al. “Hyperdimensional Computing with Learnable Projection for User Adaptation Framework”, hereinafter “Hsiao”.
Regarding Claim 1, Hsiao teaches:
A method for inference classification (p. 3, paragraph 2, “this paper first applies HDC with learnable projection to a user adaptation framework to improve classification”), the method comprising:
by a circuit coupled with (i) an item memory (Hsiao’s method is performed on a cloud server and edge devices demonstrating Hsiao performs their methods on computers in which processor, memory, storage devices, and circuits are inherent, p. 2, Figure 1, p. 3, paragraph 3, “an Item Memory (IM) and a Continuous Item Memory (CIM)”), said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values (p. 3, paragraph 4, “The range between 𝑉𝑚𝑎𝑥 and 𝑉𝑚𝑖𝑛 is then equally quantized to 𝑄 levels… Each scalar in {𝑙1,𝑙2,… 𝑙𝑄} is associated with an HV in 𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑”, bipolar values are stored as binary values as shown when xor is performed, p. 4, paragraph 2, “an element-wise XOR operation (⊗) between two HVs”), and a feature memory configured to store a plurality of query feature positions that are associated with the plurality of binary vectors in the value memory (p. 3, paragraph 3, “Assume there are 𝑚 features in one data sample, 𝐼𝑀={𝐹1,𝐹2,… 𝐹𝑚}∈{+1,−1}𝑑, where 𝐹𝑘 is the projected HV for the 𝑘𝑡ℎ feature ID”, Query feature positions shown in Fm, Fm is associated with Sm generated from Lm, p. 4, paragraph 1, “For each feature, by looking up the nearest quantized level to its actual value, the HV for its value is selected and denoted as 𝑆𝑘 , where 𝑆𝑘∈𝐶𝐼𝑀,𝑘=1,2,…,𝑚. After projecting each feature into HVs, a set of two-vector pairs 𝑃={(𝐹1, 𝑆1),(𝐹2, 𝑆2),…,(𝐹𝑚, 𝑆𝑚)} is generated”); and (ii) an associative memory configured to store a plurality of predefined class vectors (p. 4, paragraph 3, “there are 𝑘 class HVs stored in an Associative Memory 𝐴𝑀={𝐶1,𝐶2,… 𝐶𝑘}∈ℤ𝑑”):
mapping each of a plurality of discrete values, loaded from the value memory to a plurality of instances of binary code (p. 3, paragraph 4, “The range between 𝑉𝑚𝑎𝑥 and 𝑉𝑚𝑖𝑛 is then equally quantized to 𝑄 levels… Each scalar in {𝑙1,𝑙2,… 𝑙𝑄} is associated with an HV in 𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑”);
stacking a plurality of value vectors associated with one or more of the plurality of discrete values associated with one or more instances of binary code, such a dimension of the stacked plurality of value vectors matches the dimension of the plurality of value vectors combined with a dimension of the feature vector (Sm are value vectors selected from and therefore associated with LQ vectors which are associated with discrete scalar values and are instances of binary code, p. 3, paragraph 4, “The range between 𝑉𝑚𝑎𝑥 and 𝑉𝑚𝑖𝑛 is then equally quantized to 𝑄 levels… Each scalar in {𝑙1,𝑙2,… 𝑙𝑄} is associated with an HV in 𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑… For each feature, by looking up the nearest quantized level to its actual value, the HV for its value is selected and denoted as 𝑆k, where 𝑆𝑘 ∈ 𝐶𝐼𝑀,𝑘 = 1, 2,…,m”, value vectors are stacked when the HV value for each value is selected, p. 3, Figure 2 stack of Sm in CIM, the dimension of each of the stacked value vectors matches the dimension of the Tj vectors created after the value vectors are combined with feature vectors because xor can only be done on vectors with matching dimensions, p.4, Equation 1 shows T vectors created from Sm xor Fm)
performing a matrix multiplication of the stacked value vectors and the feature vector to produce a sample vector (Matrix of Sm hypervectors is XORed with matrix of Fm feature vectors, which with bipolar vectors is equivalent to element wise multiplication, p. 4, paragraph 2, “performs the binding operation, an element-wise XOR operation (⊗) between two HVs”, p. 3, Fig 2 showing Sm xor Fm, p. 4, Equation 1, 𝑇=[𝐹1⊗ 𝑆1+𝐹2⊗ 𝑆2+⋯+𝐹𝑚⊗ 𝑆𝑚] Tj is sample vector that is result from xor);
generating a comparison result by comparing the sample vector against the plurality of predefined class vectors for similarity checking (Hamming distance is comparison result, p. 4, paragraph 4, “In the inference phase, a testing data is first transformed by (1) and is encoded as a query HV. Then, HDC computes the Hamming distance between the query HV and the class HVs in the bipolarized AM”); and
classifying the sample vector based on the comparison results associated with the similarities between the sample vector and the plurality of predefined class vectors (p. 4, paragraph 4, “The class with the minimum distance is outputted as a prediction”).
Regarding Claim 2, Hsiao teaches the method of Claim 1 as referenced above. Hsiao further teaches:
defining a neural network comprising a value layer, a feature layer, and a class layer (First layer is value layer(WCIM) and feature layer(WIM), second layer is class layer (WAM), p. 6, Figure 4b, p. 5, paragraph 2, “To transform HDC into a learnable network, L-HDC comprises two layers, as shown in Fig. 4(b). The first layer is tailored to emulate the projection and encoding parts of the original HDC. The parameters of the first layer contain two sets of weights denoted as 𝑊𝐼𝑀∈{+1,−1}𝑚×𝑑 and 𝑊𝐶𝐼𝑀∈{+1,−1}𝑄×𝑑 corresponding to the IM and CIM in the original HDC”);
extracting a plurality of value vectors by inputting a plurality of values to the value layer that converts feature values to bipolar value vectors, and recording output of the value layer (value vector is row in WCIM, p. 5, paragraph 2, “The first layer is tailored to emulate the projection and encoding parts of the original HDC. The parameters of the first layer contain two sets of weights denoted as 𝑊𝐼𝑀 ∈ {+1,−1}𝑚×𝑑 and W𝐶𝐼𝑀 ∈ {+1,−1}𝑄×𝑑 corresponding to the IM and CIM in the original HDC”, p. 2, paragraph 4, “CIM is used as a look-up table to project the actual value into an HV”);
extracting a plurality of feature vectors by recording a binary weight associated with each of the plurality of feature vectors in the feature layer, where said plurality of feature vectors have the same dimension as the value vectors (feature vector is row in WIM, vectors have same dimensions as shown with d, p. 5, paragraph 2, “𝑊𝐼𝑀∈{+1,−1}𝑚×𝑑 and 𝑊𝐶𝐼𝑀∈{+1,−1}𝑄×𝑑 … 𝑊𝐼𝑀[𝑖][𝑗]… symbolize the entry of the 𝑖𝑡ℎ row and the 𝑗𝑡ℎ column of the 𝑊𝐼𝑀, 𝑊𝐶𝐼𝑀”, p. 3, paragraph 3, “𝐼𝑀={𝐹1,𝐹2,… 𝐹𝑚}∈{+1,−1}𝑑, where 𝐹𝑘 is the projected HV for the 𝑘𝑡ℎ feature ID”); and
extracting a plurality of class vectors by recording a binary weight associated with each of the plurality of class vectors in the class layer, where said plurality of class vectors have the same dimension as the plurality of value vectors and the plurality of feature vectors (p. 5, paragraph 2, “The second layer is a fully connected (FC) layer whose weights represent the AM in the original HDC and are denoted as 𝑊𝐴𝑀∈{+1,−1}𝑘×𝑑”, p. 4, paragraph 3, “For a 𝑘-class classification task, there are 𝑘 class HVs stored in an Associative Memory 𝐴𝑀={𝐶1,𝐶2,… 𝐶𝑘}∈ℤ𝑑. To perform efficient inference on devices, HDC bipolarizes each class HV in 𝐴𝑀 into a bipolarized one and generate a corresponding bipolarized AM 𝐴𝑀𝑏={𝐶1𝑏,𝐶2𝑏,… 𝐶𝑘𝑏}∈{+1,−1}𝑑, where 𝐶𝑖𝑏=[𝐶𝑖]”); and defining a sample vector as a product of binding the feature vector and the stacked value vectors (p. 4, paragraph 2, 𝑇=[𝐹1⊗ 𝑆1+𝐹2⊗ 𝑆2+⋯+𝐹𝑚⊗ 𝑆𝑚] and “HDC performs the binding operation, an element-wise XOR operation (⊗) between two HVs, to each two-vector pair”).
Regarding Claim 3, Hsiao teaches the method of Claim 1 as referenced above. Hsiao further teaches:
wherein the circuit is implemented on a tiny device (tiny device is edge device, p. 7, paragraph 1, “after completing training L-HDC in the cloud, we transform the architecture of L-HDC back to that of the original HDC to efficiently adapt to user’s data”, p. 2, paragraph 1, “These advantages make HDC suitable for on-device user adaptation framework, as depicted in Fig. 1(b)”).
Regarding Claim 5, Hsiao teaches the method of Claim 1 as referenced above. Hsiao further teaches:
wherein the mapping each of the plurality of discrete values associated with the feature vector to a plurality of instances of binary code, is performed by a trainable binary neural network (L-HDC is binarized neural network, p. 5, paragraph 1, “The architecture of L-HDC is similar to a binarized neural network (BNN) [19] since both models compute with bipolar weights. When training on cloud, L-HDC learns a better feature-aware projection by backpropagation”).
Regarding Claim 6, Hsiao teaches the method of Claim 5 as referenced above. Hsiao further teaches:
wherein the binary neural network is trained to optimize the organization of the plurality of instances of binary code by converting the value vectors to a low vector dimension (organization of instances of binary code are optimized through backpropagation, p. 10, paragraph 1, “For the learned 𝐼𝑀, L-HDC can learn the feature correlations during the training process. Therefore, the histogram of the learned 𝐼𝑀 is more diverse and provides HDC with a better projection for higher performance”, value vectors are converted to a low dimension in this process when weight vectors are input through layers with lower dimension kxd as shown in p. 6, Figure 4(b)).
Regarding Claim 7, Hsiao teaches:
A method for inference classification, the method comprising:
by a processor coupled with an associative memory (Hsiao’s method is performed on a cloud server and edge devices demonstrating Hsiao performs their methods on computers in which processor, memory, and storage devices are inherent, p. 2, Figure 1, p. 3 Figure 2 shows Associative Memory used in Hsiao):
encoding a class vector for a class of data vectors, the vector being determined by collecting a class of data and encoding the class of data with feature vectors and with value vectors (p. 4, paragraph 3, “After encoding, we denote 𝑇𝑖𝑗 as the encoded HV of the 𝑗𝑡ℎ data sample corresponding to the 𝑖𝑡ℎ class”, Tj was found with feature and value vectors, p. 4, Equation 1, Feature vectors are Fm and value vectors are Sm);
calculating a class vector by averaging each of a plurality of hypervectors within the class (class vector is calculated through averaging by summing over ni samples, p. 4, paragraph 3, “Then, HVs belonging to the 𝑖𝑡ℎ class are accumulated to form a class HV 𝐶𝑖∈ℤ𝑑, which is computed as: 𝐶𝑖= 𝑇𝑖1+𝑇𝑖2+⋯+𝑇𝑖𝑛𝑖. (2)”); and
storing the class vector in the associative memory (p. 4, paragraph 4, “For a 𝑘-class classification task, there are 𝑘 class HVs stored in an Associative Memory 𝐴𝑀={𝐶1,𝐶2,… 𝐶𝑘}∈ℤ𝑑”).
Regarding Claim 8, Hsiao teaches the method of Claim 7 as referenced above. Hsiao further teaches:
wherein the class of data is a class of data of a plurality of classes of data (p. 4, paragraph 4, “For a 𝑘-class classification task, there are 𝑘 class HVs stored in an Associative Memory).
Regarding Claim 9, Hsiao teaches the method of Claim 7 as referenced above. Hsiao further teaches:
further comprising: discarding all non-binary weight associated with the extracted value vectors (Value vectors are only bipolar so all non-binary weight is implicitly discarded, p. 3, paragraph 4, “𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑”, p. 5, paragraph 1, “the HV for its value is selected and denoted as 𝑆𝑘 , where 𝑆𝑘∈𝐶𝐼𝑀”).
Regarding Claim 10, Hsiao teaches the method of Claim 7 as referenced above. Hsiao further teaches:
extracting the class vectors from a set of optimized class weight parameters (p. 4, paragraph 3, “Then, HVs belonging to the 𝑖𝑡ℎ class are accumulated to form a class HV 𝐶𝑖∈ℤ𝑑, which is computed as: 𝐶𝑖= 𝑇𝑖1+𝑇𝑖2+⋯+𝑇𝑖𝑛𝑖. (2)”).
Regarding Claim 11, Hsiao teaches:
A system for inference classification (p. 3, paragraph 2, “this paper first applies HDC with learnable projection to a user adaptation framework to improve classification”), the system comprising:
(i) an item memory (p. 2, Figure 1, p. 3, paragraph 3, “an Item Memory (IM) and a Continuous Item Memory (CIM)”), said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values (p. 3, paragraph 4, “The range between 𝑉𝑚𝑎𝑥 and 𝑉𝑚𝑖𝑛 is then equally quantized to 𝑄 levels… Each scalar in {𝑙1,𝑙2,… 𝑙𝑄} is associated with an HV in 𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑”, bipolar values are stored as binary values as shown when xor is performed, p. 4, paragraph 2, “an element-wise XOR operation (⊗) between two HVs”), and a feature memory configured to store a plurality of query feature positions that are associated with the plurality of binary vectors in the value memory (p. 3, paragraph 3, “Assume there are 𝑚 features in one data sample, 𝐼𝑀={𝐹1,𝐹2,… 𝐹𝑚}∈{+1,−1}𝑑, where 𝐹𝑘 is the projected HV for the 𝑘𝑡ℎ feature ID”, Query feature positions shown in Fm, Fm is associated with Sm generated from Lm, p. 4, paragraph 1, “For each feature, by looking up the nearest quantized level to its actual value, the HV for its value is selected and denoted as 𝑆𝑘 , where 𝑆𝑘∈𝐶𝐼𝑀,𝑘=1,2,…,𝑚. After projecting each feature into HVs, a set of two-vector pairs 𝑃={(𝐹1, 𝑆1),(𝐹2, 𝑆2),…,(𝐹𝑚, 𝑆𝑚)} is generated”); and (ii) an associative memory configured to store a plurality of predefined class vectors (p. 4, paragraph 3, “there are 𝑘 class HVs stored in an Associative Memory 𝐴𝑀={𝐶1,𝐶2,… 𝐶𝑘}∈ℤ𝑑”):
a circuit coupled with the value memory, the feature memory, and the associative memory (Hsiao’s method is performed on a cloud server and edge devices demonstrating Hsiao performs their methods on computers in which processor, memory, storage devices, and circuits are inherent, p. 2, Figure 1, p. 3, Figure 2 shows value memory, feature memory, and associative memory), the circuit configured to:
map a plurality of discrete values associated with a feature vector (p. 3, paragraph 4, “The range between 𝑉𝑚𝑎𝑥 and 𝑉𝑚𝑖𝑛 is then equally quantized to 𝑄 levels… Each scalar in {𝑙1,𝑙2,… 𝑙𝑄} is associated with an HV in 𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑”, feature vector is associated with discrete values when xord, Equation 1);
stack a plurality of value vectors associated with one or more of the plurality of discrete values associated with one or more instances of binary code, such a dimension of the stack of plurality of value vectors matches the dimension of the plurality of value vectors combined with a dimension of the feature vector (Sm are value vectors selected from and therefore associated with LQ vectors which are associated with discrete scalar values and are instances of binary code, p. 3, paragraph 4, “The range between 𝑉𝑚𝑎𝑥 and 𝑉𝑚𝑖𝑛 is then equally quantized to 𝑄 levels… Each scalar in {𝑙1,𝑙2,… 𝑙𝑄} is associated with an HV in 𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑… For each feature, by looking up the nearest quantized level to its actual value, the HV for its value is selected and denoted as 𝑆k, where 𝑆𝑘 ∈ 𝐶𝐼𝑀,𝑘 = 1, 2,…,m”, value vectors are stacked when the HV value for each value is selected, p. 3, Figure 2 stack of Sm in CIM, the dimension of each of the stacked value vectors matches the dimension of the Tj vectors created after the value vectors are combined with feature vectors because xor can only be done on vectors with matching dimensions, p.4, Equation 1 shows T vectors created from Sm xor Fm)
compare a sample vector to each of a plurality of predefined class vectors by performing a matrix multiplication, the sample vector being a product of binding the feature vector and the stacked plurality of value vectors (Matrix of Sm hypervectors is XORed with matrix of Fm feature vectors, which with bipolar vectors is equivalent to element wise multiplication, p. 4, paragraph 2, “performs the binding operation, an element-wise XOR operation (⊗) between two HVs”, p. 3, Fig 2 showing Sm xor Fm, p. 4, Equation 1, 𝑇=[𝐹1⊗ 𝑆1+𝐹2⊗ 𝑆2+⋯+𝐹𝑚⊗ 𝑆𝑚] Tj is sample vector that is result from xor);
identifying a respective value associated with similarity between the sample vector and each of the plurality of class vectors (p. 4, paragraph 4, “In the inference phase, a testing data is first transformed by (1) and is encoded as a query HV. Then, HDC computes the Hamming distance between the query HV and the class HVs in the bipolarized AM”); and
classifying the sample vector based on the maximum value associated with similarity with the plurality of predefined class vectors (Minimum Hamming distance is maximum similarity p. 4, paragraph 4, “The class with the minimum distance is outputted as a prediction”).
Regarding Claim 12, Hsiao teaches:
A method for inference classification (p. 3, paragraph 2, “this paper first applies HDC with learnable projection to a user adaptation framework to improve classification”), the method comprising:
by a circuit coupled with (i) an item memory (Hsiao’s method is performed on a cloud server and edge devices demonstrating Hsiao performs their methods on computers in which processor, memory, storage devices, and circuits are inherent, p. 2, Figure 1, p. 3, paragraph 3, “an Item Memory (IM) and a Continuous Item Memory (CIM)”), said item memory comprises a value memory configured to store a plurality of binary vectors representing discrete values (p. 3, paragraph 4, “The range between 𝑉𝑚𝑎𝑥 and 𝑉𝑚𝑖𝑛 is then equally quantized to 𝑄 levels… Each scalar in {𝑙1,𝑙2,… 𝑙𝑄} is associated with an HV in 𝐶𝐼𝑀={𝐿1,𝐿2,… 𝐿𝑄}∈{+1,−1}𝑑”, p. 4, paragraph 1, “HV for its value is selected and denoted as 𝑆𝑘 , where 𝑆𝑘∈𝐶𝐼𝑀”, bipolar values are stored as binary values as shown when xor is performed, p. 4, paragraph 2, “an element-wise XOR operation (⊗) between two HVs”), and a feature memory configured to store a plurality of query feature positions(p. 3, paragraph 3, “Assume there are 𝑚 features in one data sample, 𝐼𝑀={𝐹1,𝐹2,… 𝐹𝑚}∈{+1,−1}𝑑, where 𝐹𝑘 is the projected HV for the 𝑘𝑡ℎ feature ID”, Query feature positions shown in Fm); and (ii) an associative memory configured to store a plurality of predefined class vectors (p. 4, paragraph 3, “there are 𝑘 class HVs stored in an Associative Memory 𝐴𝑀={𝐶1,𝐶2,… 𝐶𝑘}∈ℤ𝑑”): combining the plurality of binary vectors with the plurality of query feature positions, resulting in a sample vector (vectors are combined in p. 4, Equation 1, 𝑇=[𝐹1⊗ 𝑆1+𝐹2⊗ 𝑆2+⋯+𝐹𝑚⊗ 𝑆𝑚] Tj is sample vector that is result from combination)
comparing the sample vector to a plurality of class vectors of a class layer, the comparison of the sample vector to the plurality of class vectors resulting in respective comparison scores for each comparison (p. 4, paragraph 4, “In the inference phase, a testing data is first transformed by (1) and is encoded as a query HV. Then, HDC computes the Hamming distance between the query HV and the class HVs in the bipolarized AM”); and
outputting the comparison scores for classification as an inference label (p. 4, paragraph 4, “The class with the minimum distance is outputted as a prediction”).
Regarding Claim 13, Hsiao teaches the method of Claim 12 as referenced above. Hsiao further teaches:
multiplying each feature vector with each value vector (xor of bipolar vectors is equivalent to element wise multiplication, p. 4, paragraph 2, “HDC performs the binding operation, an element-wise XOR operation (⊗) between two HVs, to each two-vector pair in the set 𝑃”); and
accumulating the result of the multiplying, the accumulation resulting in the sample vector (p. 4, Equation 1 𝑇=[𝐹1⊗ 𝑆1+𝐹2⊗ 𝑆2+⋯+𝐹𝑚⊗ 𝑆𝑚]).
Regarding Claim 16, Hsiao teaches the method of Claim 12 as referenced above. Hsiao further teaches:
wherein one or more of the value memory, associative memory, and feature memory are 1MB or less (feature memory is less than 1mb, p. 4, paragraph 3, “𝑘 class HVs stored in an Associative Memory 𝐴𝑀”, p. 7, paragraph 3, “ISOLET dataset… 26 letters of the alphabets”, p. 8, paragraph 5, “𝑑 = 3,000”, Hypervectors are stored as binary as established above and associative memory contains 26 class hypervectors, p. 9, Table 1 Isolet # of classes, p. 4, paragraph 3, “Associative Memory 𝐴𝑀={𝐶1,𝐶2,… 𝐶𝑘}∈ℤ𝑑”, to calculate MB in associative memory 3,000bits*26classes = 0.00975MB which is less than 1MB).
Regarding Claim 17, Hsiao teaches the method of Claim 12 as referenced above. Hsiao further teaches:
wherein the circuit includes less than 10,000 look up tables (LUTs) (Hsiao uses standard processor and computer implementation without an FPGA circuit, Claim 12 which Claim 17 is dependent on does not require an FPGA circuit and uses 0 LUTs, therefore Hsiao’s circuit uses 0 LUTs which is less than 10,000 LUTs, Fig 1 showing cloud server and edge device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao in view of Imani et al. “Revisiting HyperDimensional Learning for FPGA and Low-Power Architectures”, from applicant IDS, hereinafter “Imani”.
Regarding Claim 4, Hsiao teaches the method of Claim 1 as referenced above. Hsiao does not teach but Imani teaches:
wherein the circuit is a field programmable gate array (FPGA) (Imani, p. 222, col. 2, paragraph 1, “FPGA based LookHD is implemented on Kintex-7 FPGA KC705”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an FPGA circuit as does Imani with the hardware of Hsiao. The motivation to do so would be to be more energy efficient for resource limited devices (Imani, p. 231, col. 1, paragraph 2, “As compared to CPU-based implementation of LookHD, the FPGA-based implementation is, on average, 122.9× faster and 238.6× more energy efficient”, p. 231, col. 1, last paragraph, “All proposed algorithm-hardware operations are general and can be implemented on any platform with bit-level granularity, including low-power or high-performance FPGA/ASIC”).
Regarding Claim 14, Hsiao teaches the method of Claim 13 as referenced above. Hsiao does not teach but Imani teaches:
wherein the multiplying and accumulating are performed by an FGPA(Imani, p. 222, col. 2, paragraph 1, “FPGA based LookHD is implemented on Kintex-7 FPGA KC705”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Imani’s FPGA circuit for hdc operations such as the multiplying and accumulating of Hsiao. The motivation to do so would be to be more energy efficient for resource limited devices (Imani, p. 231, col. 1, paragraph 2, “As compared to CPU-based implementation of LookHD, the FPGA-based implementation is, on average, 122.9× faster and 238.6× more energy efficient”, p. 231, col. 1, last paragraph, “All proposed algorithm-hardware operations are general and can be implemented on any platform with bit-level granularity, including low-power or high-performance FPGA/ASIC”).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiao in view of Leung, “Fixed Weight Competitive Nets: Hamming Net”, hereinafter “Leung”.
Regarding Claim 15, Hsiao teaches the method of Claim 12 as referenced above. Hsiao does not expressly teach, but Leung teaches:
wherein comparing the sample vector to the plurality of class vectors further includes: multiplying the sample vector with each class vector; and averaging the result of the multiplication to a scalar (Hsiao shows calculating a hamming distance between bipolar vectors which involves element wise multiplication and averaging to a scalar inherently, Hsiao, p. 4, paragraph 4, “HDC computes the Hamming distance between the query HV and the class HVs”, Leung, shows this where bits that are the same or different contribute +1 or -1 to dot product and the result is divided by a scalar, Leung, p.15-16, “we will be working with bipolar vectors and denote the Hamming distance between the vectors (defined to be the number of corresponding bits that are different between the vectors) by H(a,b), and the number of corresponding bits that agrees with each other by A(a,b). It is clear that for bipolar vectors a· b =A(a,b)−H(a,b), because the corresponding bits are either the same, and so they contribute 1 to the dot-product, or they are different and so contribute −1 to the dot-product. A corresponding pair of bits must either agree or disagree, and so N =A(a,b)+H(a,b). We eliminate the Hamming between these two equations and solve for A(a,b) to get A(a,b) = a· b/2 + N/2”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Leung’s formula for bipolar hamming distance in Hsiao. The motivation to do so would be that Hsiao does not explicitly say how they calculate their hamming distance therefore a mathematical formula to do so is needed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE CHEN COULSON whose telephone number is (571)272-4716. The examiner can normally be reached Monday-Friday 8:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kakali Chaki can be reached at (571) 272-3719. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JESSE C COULSON/
Examiner, Art Unit 2122
/KAKALI CHAKI/Supervisory Patent Examiner, Art Unit 2122
Prosecution Insights