Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8-11, 18-20, 25, and 27-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rallabandi (US 7545214 B2), hereafter referred to as “Rallabandi”.
Regarding Claims 1, 10, 11, 20, 25 and 29, in the embodiment of Figs. 2A, 2B and 3, Rallabandi discloses:
An amplifier, comprising:
a first transconductance (Gm) path (sources of transistors 1 and 4 forms the first transconductance path) coupled between a differential output pair (first and second nodes 181 and 182 is coupled to the output stage, per claim 11), the first Gm path including
a first pair of input transistors (NMOS transistors 1 and 4, as per claims 10 and 29) with gates coupled to a positive input and a negative input (input terminals 151 and 153 are differential inputs per column 6 lines 47-54, differential inputs are known in the art to be positive and negative, as per claim 25), respectively;
a first pair of cascode transistors (PMOS transistors 8 and 9) coupled in cascode with the first pair of input transistors, respectively;
a second Gm path (sources of transistors 2 and 3 forms the second transconductance path, per claim 11) coupled between the differential output pair, the second Gm path including
a second pair of input transistors (NMOS transistors 2 and 3, as per claims 10 and 29) with gates coupled to the positive input and the negative input (input terminals 151 and 153, as per claim 25), respectively;
a second pair of cascode transistors (PMOS transistors 10 and 11) coupled in cascode with the second pair of input transistors, respectively; and
a third Gm path (sources of transistors 15 and 16 forms the second transconductance path per claim 11) comprising
a third pair of input transistors (PMOS transistors 15 and 16, as per claims 10 and 29) coupled to the second pair of cascode transistors, respectively, the third pair of input transistors comprising gates coupled to the positive input and the negative input (transistors 15 and 16 gates are connected to input terminals 151 and 153, as per claim 25), respectively, the third Gm path being coupled to the second pair of cascode transistors, and generates differential output signals at the differential output pair, respectively, based on the differential input signals (column 3 lines 25-34, in response to activating the first differential input circuits a current is provided to nodes 181 and 182 coupled to the output stage, per claim 20), wherein the differential output pair is coupled to the first pair of cascode transistors, respectively.
Regarding claims 8, 9, 18, and 19, in the embodiment of Figs. 2A, 2B and 3, Rallabandi discloses:
a current source coupled to the first pair of input transistors, comprising the first Gm path and the second pair of input transistors, comprising the second Gm path (current source 101, per claims 8 and 18), and further comprising a current source coupled to the third pair of input transistors, comprising the third Gm path (Fig. 3, Imirror connected to transistors 15 and 16, per claims 9 and 19).
Regarding claims 27 and 28, in the embodiment of Figs. 2A, 2B and 3, Rallabandi discloses:
sinking, via a current source (i.e. current source 101), a current from a node coupled to the first pair of input transistors and the second pair of input transistors per claim 27, and
sourcing a current, via a current source (i.e. current source Imirror), to a node coupled to the third pair of input transistors per claim 28 (column 2 lines 38-40, Operational amplifier may be designed to go rail to rail (e.g. voltage rails 154 and 156 that connected to current sources 101 and Imirror) at its input and output while sourcing and sinking current at the output).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 17, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Rallabandi (US 7545214 B2) .
Regarding claims 7, 17, and 26, in the embodiment of Fig. 2A, 2B and 3, Rallabandi discloses:
the first and second pair of cascode transistors (PMOS transistors 8-10), the first, second, third pair of input transistors (NMOS transistors 1-4 and PMOS transistors 15 and 16), the first and second pair of input transistors are n-channel metal-oxide-semiconductor (NMOS) transistors (column 2 lines 55-58, transistors 1-4 are NMOS transistors), and third pair of input transistors (PMOS transistors 15 and 16) are p-channel metal-oxide-semiconductor (PMOS) transistors (column 4, lines 32-35, transistors 15 and 16 are PMOS transistors).
However, Rallabandi does not teach that the first and second pair of cascode transistors are NMOS.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to consider modifying the transistors in Rallabandi (Figs. 2A, 2B, and 3) for the first and second pair of cascode transistors to be NMOS transistor to be turned on by a positive voltage, as is known in the art, thereby suggesting the obviousness of such a configuration.
Allowable Subject Matter
Claims 2-5, 12-15, 21-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2, 12, and 21:
the cited prior art of record, Rallabandi (US 7545214 B2), either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “a fourth pair of cascode transistors, a first transistor of the fourth pair of cascode transistors is coupled to a first transistor of the pair of bias transistors; and a second transistor of the fourth pair of cascode transistors is coupled to a second transistor of the pair of bias transistors”
Claims 3-5, 13-15, and 22-24 are objected to due to dependence on objected claims 2, 12, and 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Malane Lieng/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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