DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Regarding claims 1 and 12, the claim(s) recite(s) a mental process that "can be performed in the human mind, or by a human using a pen and paper" [MPEP, 2106.04(a)(2), III]. For example, paragraph 69 (fig. 5A) of the specification discloses a high-level representation of the example quantum circuit. A user can look at the figure and perform the claimed “identifying” steps by using pen and paper. The "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. The “identifying” steps are nothing more than observations, evaluations, judgments, or opinions, hence said steps recite a mental process.
“Generating a parsed circuit structure representation” can be performed by a human using pen and paper, and therefore is considered a mental process (thinking). For example, paragraphs [0173] - [0174] state “a parsed circuit structure representation can be generated by parsing the circuit structure data identified at 320. The parsed circuit structure representation may be a circuit structure object” and “FIG. 5F illustrates an example of a circuit structure object.” Figure 5F is code. Hence a user can observe code and performing parsing by using pen and paper to write fig. 5F.
“Generating a parsed parameter representation by parsing the parameter data, wherein the parameter data is parsed separately from the circuit structure data” can be performed by a human using pen and paper, and therefore is considered a mental process (thinking). For example, paragraphs [0151] states “defining the parameter data in an .npz format can facilitate subsequent parsing.” Figure 5C is nothing more than code. Hence a user can observe code and performing parsing by using pen and paper.
The step of “combining the parsed circuit structure representation and the parsed parameter representation into a combined quantum circuit” can also be performed by a human using pen and paper, and therefore is considered a mental process (thinking).
For example, paragraph [0011] discloses “[c]ombining the parsed circuit structure representation and the parsed parameter representation into the combined quantum circuit can include, for each parameter in the plurality of parameters: determining a corresponding parameter location in the parsed circuit structure representation; and inserting a parameter value of that parameter at the corresponding parameter location.” This step can be performed by observing the code and inserting the parameter at the corresponding location in the code, hence a human using pen and paper can perform this step.
This judicial exception is not integrated into a practical application because the first limitation states “to be executed by a quantum simulator or quantum hardware,” which amounts to implementing an abstract idea on a computer.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because “a quantum circuit to be executed by a quantum simulator or quantum hardware” alludes to mere physicality or tangibility of an additional elements that are not a relevant consideration in Step 2B [MPEP, 2106.05, A]. Also see Alice Corp., 573 U.S. at 224, 110 USPQ2d at 1983-84 (alterations in original) and Genetic Technologies Ltd. v. Merial LLC, 818 F.3d 1369, 1377, 118 USPQ2d 1541, 1547 (Fed. Cir. 2016) (steps of DNA amplification and analysis "do not, individually or in combination, provide sufficient inventive concept to render claim 1 patent eligible" merely because they are physical steps).
Claim 12 is rejected under the same rationale as claim 1.
Dependent claims 2-11 and 13-20 further elaborate upon the recited abstract idea in claims 1 and 12. Accordingly, claims 1-20 recite at least one abstract idea.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Naveh et al, US 11281988 B1, discloses gate-level implementation may be dynamically generated using a predefined set of construction rules for parsing an arithmetic functional formula. Additionally, or alternatively, the gate-level implementation may be generated using stochastic methods, using genetic algorithms, using brute force enumeration on potential implementations, or the like [col. 46, lines 25-31] and fig. 3.
Kasprowicz et al, US 20210158425 A1, discloses quantum computing service 102 includes quantum hardware provider recommendation/selection module 120. In some embodiments, quantum hardware recommendation/selection module 120 may make a recommendation to a quantum computing service customer as to which type of quantum computer or which quantum hardware provider to use to execute a quantum object submitted by the customer. Additionally, or alternatively, the quantum hardware provider recommendation/selection module 120 may receive a customer selection of a quantum computer type and/or quantum hardware provider to use to execute the customer's quantum object, such as a quantum task, quantum algorithm, quantum circuit, etc [paragraph 94].
Yu et al, US 20230186130 A1, discloses circuits 213 in the bucket 215 can be combined and/or compiled into a composite circuit 217 and mapped and/or remapped to a physical qubit layout 219, which can be based on at least a portion of qubits 227 of the quantum logic circuit 228 [paragraph 63]. Yu discloses A bucket 215 can be a storage unit employed for temporary storage of a quantum circuit 213 or a copy thereof. A bucket 215 can be comprised by the memory 204 and/or can be separate therefrom. A bucket 215 can be “emptied” of a quantum circuit 213 upon compilation of the quantum circuit 213 into a composite circuit 217. In one or more embodiments, buckets 215 can be employed to temporarily store composite circuits 217. A composite circuit 217 can be a quantum circuit that consists of multiple smaller quantum circuits 213, thus allowing for maximizing usage of a quantum logic circuit 228 [paragraph 62].
Ducore et al, US 20200394027 A1, discloses Further, in a TCQPL context, a circuit may be regarded as a data type that stores a logical representation of a quantum circuit. A directed acyclic graph (DAG) is an example of an internal data structure used to store the quantum circuit information [paragraph 27]. Ducore discloses quantum compiler 120 includes at least receiver 205, memory manager 210, parse tree generator 215, function arbiter 220, source code manager 225, and annotator 230 [paragraph 51].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Farley Abad/ Primary Examiner, Art Unit 2181
Prosecution Insights