Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 are presented for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/26/25 has been entered.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The following is an explanation of the interpretation of the structures from Applicant’s specification that correspond to the claimed means plus function limitations of claim 11:
“means for issuing…” corresponds to scheduling stage circuit (see fig. 1 element 106(3), para. [0007]).
“means for identifying…” corresponds to execution stage circuit (see fig. 1 element 106(4), para. [0012]).
“means for retrieving…” corresponds to execution stage circuit (see fig. 1 element 106(4), para. [0012]).
“means for broadcasting…” corresponds to execution stage circuit (see fig. 1 element 106(4), para. [0012]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 14, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Hughes et al., US Patent Application Publication 2001/0037434 (hereinafter Hughes) in view of Sander et al., US Patent 7,937,569 (hereinafter Sander).
Regarding claim 1, Hughes teaches:
A processor-based device, comprising: a processor comprising an instruction processing circuit comprising a plurality of pipeline stage circuits including a scheduling stage circuit and an execution stage circuit (see e.g. fig. 1, 2, para. [0054], reservation unit and functional unit); the scheduling stage circuit comprising a reservation station circuit (see e.g. fig. 1, 2, para. [0054], reservation station); the execution stage circuit comprising a physical register (PR) swap table storing a plurality of PR swap table entries (see e.g. fig. 11, dependency link file); the scheduling stage circuit configured to issue a first instruction that is associated with a store dependency identifier (ID) (see e.g. para. [0054], [0069], [0143], a store instruction or an arithmetic instruction that implicitly includes a store memory operation); and the execution stage circuit configured to, responsive to the issuing of the first instruction: identify a PR swap table entry corresponding to the store dependency ID among the plurality of PR swap table entries of the PR swap table (see e.g. para. [0006], [0069], [0143], an entry corresponding to a store tag is identified in the dependency link file); retrieve a load dependency ID of the PR swap table entry (see e.g. para. [0143], a load tag is retrieved from the dependency link file); and broadcast the load dependency ID to the reservation station circuit to wake a second instruction that is associated with the load dependency ID (see e.g. para. [0055], [0057], [0070], [0143], tags and data are sent from result buses).
Hughes fails to explicitly teach forwarding data upon detection of the issuing of the first instruction.
Sander teaches forwarding data as a speculative operand source tag upon dispatching an instruction (see e.g. col. 8 lines 16-25).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Hughes and Sander to include forwarding data upon detection of the issuing of the first instruction. This type of speculative forwarding would have provided an advantage such as discussed by Sander: “Since speculation allows execution to proceed without waiting for dependency checking to complete, significant performance gains may be achieved if the performance gained from correct speculations exceeds the performance lost to incorrect speculations.” (see col. 1 lines 56-60).
Regarding claim 2, Hughes in view of Sander teaches or suggests:
The processor-based device of claim 1, wherein: the execution stage circuit further comprises a load-store unit (LSU) circuit comprising a load queue; and the LSU circuit is configured to: detect an address dependency between a store instruction and a load instruction; determine that the load instruction is resident in the load queue and is awaiting store data; and responsive to detecting the address dependency and determining that the load instruction is resident in the load queue, allocate the PR swap table entry in the PR swap table by being configured to: determine the store dependency ID based on the store instruction; determine the load dependency ID based on the load instruction; and store the store dependency ID and the load dependency ID as part of the PR swap table entry (see e.g. fig. 11, para. [0142-3]).
Regarding claim 10, Hughes in view of Sander teaches or suggests:
The processor-based device of claim 1, integrated into a device comprising one of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (see e.g. para. [0227], computer system).
Claim 11 is rejected for reasons corresponding to those given above for claim 1.
Claims 12-13 are rejected for reasons corresponding to those given above for claims 1-2.
Claims 21-22 are rejected for reasons corresponding to those given above for claims 1-2.
Claims 3, 14, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Hughes in view of Sander, further in view of Kanapathipillai et al., US Patent 10,437,595 (hereinafter Kanapathipillai).
Regarding claim 3, Hughes in view of Sander teaches or suggests:
The processor-based device of claim 1, wherein: the plurality of pipeline stage circuits further includes a decode stage circuit and a rename stage circuit (see e.g. para. [0053], para. [0143], reorder buffer in combination with dependency link file); the execution stage circuit further comprises a load-store unit (LSU) circuit (see e.g. fig. 1, 2, para. [0143]); the rename stage circuit is configured to allocate the PR swap table entry in the PR swap table by being configured to: determine the store dependency ID based on the store instruction; determine the load dependency ID based on the load instruction; and store the store dependency ID and the load dependency ID as part of the PR swap table entry (see e.g. para. [0143]).
Hughes in view of Sander fails to explicitly teach one of the decode stage circuit and the rename stage circuit is configured to predict an address dependency between a store instruction and a load instruction, and the LSU circuit is configured to verify the prediction of the address dependency during one of issuance of the load instruction and replay of the load instruction.
Kanapathipillai teaches predicting an address dependency between a store instruction and a load instruction, and verifying the prediction that a load receives its data from the store queue to increase the confidence of the prediction (see e.g. col. 8 line 65 – col. 9 line 4).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Hughes, Sander, and Kanapathipillai such that one of the decode stage circuit and the rename stage circuit is configured to predict an address dependency between a store instruction and a load instruction, and the LSU circuit is configured to verify the prediction of the address dependency during one of issuance of the load instruction and replay of the load instruction. This would have helped in the training of the dependency predictor to more accurately make predictions and improve processing efficiency.
Claim 14 is rejected for reasons corresponding to those given above for claim 3.
Claim 23 is rejected for reasons corresponding to those given above for claim 3.
Claims 4, 6-7, 15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hughes in view of Sander, further in view of Al-Otoom et al., US Patent 10,838,729 (hereinafter Al-Otoom).
Regarding claim 4, Hughes in view of Sander teaches or suggests:
The processor-based device of claim 2, wherein: the store dependency ID of the PR swap table entry comprises a store data PR tag of the store instruction (see e.g. fig. 11, para. [0143]).
Hughes in view of Sander fails to explicitly teach wherein the load dependency ID of the PR swap table entry comprises a load data PR tag of the load instruction.
Al-Otoom teaches a register file load-store dependence (RF-LSD) predictor table with load data register ID tags (see e.g. fig. 5, 9, col. 11 line 56 – col. 12 line 17, col. 18 lines 28-45).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Hughes, Sander, and Al-Otoom such that the load dependency ID of the PR swap table entry comprises a load data PR tag of the load instruction. This would have provided a way of tracking the operands of load instructions to better predict dependencies such as discussed by Al-Otoom (see col. 11 line 56 – col. 12 line 17).
Regarding claim 6, Hughes in view of Sander teaches or suggests:
The processor-based device of claim 1, wherein: the plurality of pipeline stage circuits further includes a writeback stage circuit; the execution stage circuit is further configured to execute the first instruction; and the writeback stage circuit is configured to: write a result of the execution of the first instruction into a first PR indicated by the first instruction in a register file; and write the result of the execution of the first instruction into a second PR in the register file, based on the load data PR tag of the PR swap table entry (see e.g. fig. 1, para. [0056], [0060], [0076]).
Hughes in view of Sander fails to explicitly teach wherein the PR swap table entry comprises a load data PR tag of a load instruction.
Al-Otoom teaches a register file load-store dependence (RF-LSD) predictor table with load data register ID tags (see e.g. fig. 5, 9, col. 11 line 56 – col. 12 line 17, col. 18 lines 28-45)
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Hughes, Sander, and Al-Otoom such that the load dependency ID of the PR swap table entry comprises a load data PR tag of the load instruction. This would have provided a way of tracking the operands of load instructions to better predict dependencies such as discussed by Al-Otoom (see col. 11 line 56 – col. 12 line 17).
Regarding claim 7, Hughes in view of Sander and Al-Otoom teaches or suggests:
The processor-based device of claim 6, wherein the scheduling stage circuit is further configured to: issue the second instruction; and read data corresponding to the second PR from one of the register file and an intermediate bypass stage of the instruction processing circuit (see e.g. Hughes para. [0055], [0143]).
Claims 15, 17 are rejected for reasons corresponding to those given above for claims 4, 6-7.
Claims 5, 16, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hughes in view of Sander, further in view of Meier et al., US Patent Application Publication 2013/0298127 (hereinafter Meier).
Regarding claim 5, Hughes in view of Sander teaches or suggests:
The processor-based device of claim 2.
Hughes in view of Sander fails to explicitly teach wherein: the store dependency ID of the PR swap table entry comprises one of a reorder buffer (ROB) ID and a scheduler ID of the store instruction; and the load dependency ID of the PR swap table entry comprises one of a ROB ID and a scheduler ID of the load instruction.
Meier teaches including a reorder buffer ID (RNUM) in a load-store dependency predictor table (see e.g. para. [0042], [0061-2]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Hughes, Sander, and Meier such that the store dependency ID of the PR swap table entry comprises one of a reorder buffer (ROB) ID and a scheduler ID of the store instruction; and the load dependency ID of the PR swap table entry comprises one of a ROB ID and a scheduler ID of the load instruction. This would have provided a way of uniquely identifying instructions such as discussed by Meier (see para. [0067]) to prevent acting on incorrect instruction/dependency information.
Claims 16, 18 are rejected for reasons corresponding to those given above for claim 5.
Allowable Subject Matter
Claims 8-9, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments regarding the amended “upon detection of” language have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sander.
Applicant's further arguments have been fully considered but they are not persuasive.
Applicant argues a lack of teaching to “broadcast the load dependency ID to the reservation station circuit to wake a second instruction that is associated with the load dependency ID”.
Examiner respectfully disagrees. Hughes teaches that tags are forwarded from the dependency link file (see e.g. para. [0143]). These tags are necessary for forwarding data to the proper location or reservation station entry, and are sent through result buses to the reservation station (see e.g. para. [0055], [0057], [0070], [0143]). “Reservation station 22A captures the operand tags and/or data and awaits delivery of any remaining operand data (identified by the operand tags) from result buses 38” (see para. [0070]). Sander also describes such broadcasting of a tag/ID (see e.g. col. 7 lines 54-62).
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183