DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C.
102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 17-20 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable in view of Peretz et al. US 20200343739.
Regarding claim 17, Peretz et al. discloses an
a first transistor [Figs. 2 and 3 (see reproduced), S1] coupled [note: coupled is interpreted to mean with or without intervening components] between a first battery terminal [top of Vcell1] and a capacitor terminal [Cr], the first transistor having a first transistor control terminal [par. 0073];
a second transistor [S2] coupled between the capacitor terminal [Cr] and a second battery terminal [top of Vcell2], the second transistor having a second transistor control terminal [par. 0073];
a third transistor [S3] coupled between a third battery terminal [bottom of Vcell2] and an inductor terminal [Lr], the third transistor having a third transistor control terminal, the third battery terminal coupled to the second battery terminal [Vcell1 and Vcell2 are in series]; and
a fourth transistor [S4] coupled between the inductor terminal [Lr] and a fourth battery terminal [top of Vcell3], the fourth transistor having a fourth transistor control terminal [par. 0073]; and
a control circuit [par. 0014 controller] having a control input and first, second, third, and fourth control outputs, in which the first control output is coupled to the first transistor control terminal, the second control output is coupled to the second transistor control terminal, the third control output is coupled to the third transistor control terminal, and the fourth control output is coupled to the fourth transistor control terminal [pars. 0014, 0033. See also: pars. 0080-0083]; and
a switch [Fig. 3, S5 or S6]; and
and a capacitor [Cr] and an inductor [Lr] coupled between the capacitor terminal and the inductor terminal [as seen in Fig. 3 below. Par. 0014],
wherein the switch [S5 or S6] is coupled between the capacitor terminal and the capacitor [Fig. 3 switch S5/S6 is coupled to all points in the circuit from the left-side terminal of capacitor Cr through capacitor Cr to the right-side terminal of Cr] or between the inductor terminal and the inductor.
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Peretz is silent regarding the balancing circuit being in Integrated Circuit (IC) form.
Examiner takes Official Notice, IAW MPEP 2144.03, as to the common knowledge of the recited subject matter.
Utilizing balancing circuits in IC form is well-known in the art of battery charging. It would have been obvious to one of ordinary skill in the art prior to the effective filing to utilize Peretz’s balancer in the form of an IC for the intrinsic benefit of being able to easily and cost-effectively apply it to real word applications requiring an operative balancer.
Regarding claim 19, Peretz discloses: wherein the control circuit is configured to, responsive to a control signal: within a first portion of a first switching cycle, provide a first driver signal having a first state at the first control output and a second driver signal having a second state at the second control output; within a second portion of the first switching cycle, provide the first driver signal having a second state at the first control output and the second driver signal having a first state at the second control output; within a first portion of a second switching cycle, provide a third driver signal having a first state at the third control output and a fourth driver signal having a second state at the fourth control output; within a second portion of the second switching cycle, provide the third driver signal having a second state at the third control output and the fourth driver signal having a first state at the fourth control output; and wherein: the first transistor is enabled responsive to the first driver signal having the first state and is disabled responsive to the first driver signal having the second state; the second transistor is enabled responsive to the second driver signal having the first state and is disabled responsive to the second driver signal having the second state; the third transistor is enabled responsive to the third driver signal having the first state and is disabled responsive to the third driver signal having the second state; and the fourth transistor is disabled responsive to the fourth driver signal having the second state and is enabled responsive to the fourth driver signal having the first state [pars. 0082-0083].
Regarding claims 20, 22, Peretz discloses: wherein the inductor terminal is a first inductor terminal, the capacitor terminal is a first capacitor terminal, the fourth transistor is coupled between a second capacitor terminal and the fourth battery terminal, the second capacitor terminal coupled to the first inductor terminal, and the transistor coupled between a fifth battery terminal and a second inductor terminal, the fifth transistor having a fifth transistor control terminal, in which the fifth battery terminal is coupled to the fourth battery terminal; and a sixth transistor coupled between the second inductor terminal and a sixth battery terminal, the sixth transistor having a sixth transistor control terminal; wherein the control circuit has fifth and sixth control outputs, in which the fifth control output is coupled to the fifth transistor control terminal, the sixth control output is coupled to the sixth transistor control terminal, and the control circuit is configured to, responsive to the control signal: within a first portion of a third switching cycle, provide a fifth driver signal having a first state at the fifth control output and a sixth driver signal having a second state at the sixth control output; within a second portion of the third switching cycle, provide the fifth driver signal having a second state at the fifth control output and the sixth driver signal having a first state at the fifth control output; wherein the fifth transistor is enabled responsive to the fifth driver signal having the first state and is disabled responsive to the fifth driver signal having the second state; and wherein the sixth transistor is enabled responsive to the sixth driver signal having the first state and is disabled responsive to the sixth driver signal having the second state [Fig. 9 (see reproduced) discloses the balancer with 8 half bridges comprising 16 controlled switches, coupled to two LC balancing modules, as well as all of the required switch control states. Pars. 0082-0084].
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15, 16, 17, 19, 20, 21, 22, 24, 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peretz et al. US 20200343739.
Regarding claim 15, Peretz discloses a method [par. 0001] comprising:
connecting a capacitor [Fig. 3 (see reproduced), Cr] and an inductor [Lr] between a first battery terminal [top of Vcell1] and a second battery terminal [bottom of Vcell1] of a first battery cell [at Vcell1] to provide a first voltage across the capacitor, in which a capacitor terminal of the capacitor is connected to the first battery terminal, and an inductor terminal of the inductor is connected to the second battery terminal [par. 0073];
disconnecting the inductor terminal [Lr] from the second battery terminal [when S1/S2 is opened];
connecting the inductor terminal [Lr] to the first battery terminal to provide the first voltage across the inductor [when S1/S2 is closed]; disconnecting the capacitor terminal from the first battery terminal [when S1/S2 is opened]; and
connecting the capacitor terminal to a third battery terminal [top of Vcell2] of a second battery cell [at Vcell2] to transfer charge from the capacitor [Cr] to the second battery cell at a rate based on the first voltage and an inductance of the inductor [pars. 0074-0075].
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Regarding claim 16, Peretz discloses the method of claim 15, further comprising: determining a delay interval based on a target amount of current to be from the first battery cell to the second battery cell; and delaying the connecting of the capacitor terminal to the third battery terminal with respect to the connecting of the inductor terminal to the first battery terminal by the delay interval [pars. 0074, 0075].
Regarding claim 21, Peretz discloses the system of claim 20, wherein the inductor is a first inductor, the capacitor is a first capacitor, and the system further comprises a second capacitor and a second inductor coupled between the second capacitor terminal and the second inductor terminal, and a third capacitor and a third inductor coupled between the third capacitor terminal and the third inductor terminal; and wherein the second capacitor is coupled to the first inductor, and the third capacitor is coupled to the second inductor [two sets of LC modules are embodied in Fig. 9].
Regarding claims 24, 26, Peretz discloses a system comprising: a first module [Fig. 9, reproduced; S11 and S12 is one module] including one or more pairs of first half bridge circuits [S1 and S12] coupled between a first terminal and a second terminal [at Vcell1], each of the one or more pairs of first half bridge circuits having a respective first current terminal, and the first module including a first inductor [Lr] and a first capacitor [Lc] coupled between the first current terminals of each pair of the first half bridge circuits; a second module [S13 and S14] including one or more pairs of second half bridge circuits coupled between a third terminal and a fourth terminal, the third terminal coupled to the second terminal, each of the one or more pairs of second half bridge circuits having a respective current terminal, and the second module including a second inductor and a second capacitor coupled between the second current terminals of each pair of the second half bridge circuits; a third half bridge circuit [S15 and S16] coupled between the first terminal and the second terminal, the third half bridge circuit having a third current terminal and a first control terminal; a fourth half bridge circuit coupled between the third terminal and the fourth terminal, the fourth half bridge circuit [S17 and S18] having a fourth current terminal and a second control terminal; an inductor and capacitor (LC) network [Lr and Cr] coupled between the third and fourth current terminals; a control circuit [par. 0014 controller] having a control input and first and second control outputs, in which the first control output is coupled to the first control terminal, and the second control output is coupled to the second control terminal [pars. 0014, 0033. See also: pars. 0080-0083].
Note: claims 17, 19 and 20 are rejected under 102(a)(1)- this section. For purposes of itemization expediency, they appear in the 103 section.
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Allowable Subject Matter
Claims 1, 2, 4-8 and 9-14 are allowed as currently presented.
Claims 23, 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not disclose or suggest, “23. The system of claim 22, wherein the control circuit is configured to, responsive to the control signal indicating a transfer of charge from the first battery terminal to the fifth battery terminal and from the second battery terminal to the sixth battery terminal: provide a first transition of the first driver signal from the second state to the first state at an interval before a second transition of the fifth driver signal from the second state to the first state; and provide a third transition of the fifth driver signal from the second state to the first state at a second interval after the second transition of the third driver signal from the second state to the first state”.
The prior art does not disclose or suggest, “25. The system of claim 24, further comprising: a first switch coupled between the third current terminal and the capacitor and inductor network; and a second switch coupled between the fourth current terminal and the capacitor and inductor network”.
Response to Arguments
Applicant's arguments filed 7/15/2026 have been fully considered but they are not persuasive.
Regarding claim 15, applicant argues: “In the cited FIG. 3 of Peretz (reproduced on the left), it is unclear how the capacitor Cr and inductor Lr can be connected between the first and second battery terminal of Vcell₁ to provide a first voltage across capacitor Cr. It is also unclear how opening S1/S2 can disconnect Lr from the bottom battery terminal of Vcel11, and how closing S1/S2 can provide the first voltage across inductor Lr.”
Examiner respectfully notes that the intersection between Cr and S3 is a node, which connects to Csw1 and therefore to S1 and Vcell1 (note that the intersection between Csw2 and S5 is NOT a node, as evidenced by the “jump over” schematic symbol used). Read in that context, with pars. 0074 and 0075, all limitations of claim 15 are met.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD V MURALIDAR whose telephone number is (571)272- 8933. The examiner can normally be reached M - W 9:30 am to 6:30 PM.
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unsuccessful, the examiner’s supervisor, Drew Dunn can be contacted at 571-272-2312. The fax phone number for the organization where this application or proceeding is assigned is 571-273- 8300.
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RICHARD V. MURALIDAR
Primary Examiner Art Unit 2859
/RICHARD V MURALIDAR/
Primary Examiner, Art Unit 2859
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