DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/26/2025 has been entered.
Response to Arguments
Applicant's arguments filed on 12/26/2025 have been fully considered but they are not persuasive.
Regarding independent claims 1 and 14, the applicant argues: “…the combination of Yamashita and Mabuchi does not teach, suggest, or render obvious at least, for example, the features of “the interconnect line is between the first boost line and the second boost line,” as recited in amended independent claim 1”, on page 8, paragraph 3 of the remarks; and “Yamashita describes that the intermediate interconnect 50 is provided between the capacitance interconnect 40 and the signal detection line FDL. However, Yamashita does not describe a signal detection line FDL that is between a first boost line and a second boost line”, on page 9, paragraph 2 of the remarks.
In response, the examiner has changed the interpretation of the reference Yamashita and mapping of the elements, since the claims do not clearly define “the first boost line”, “the second boost line”, and “the interconnect”. In the previous rejection, the capacitance interconnect 40 corresponds to the claimed first boost line; the intermediate interconnect 50 corresponds to the claimed second boost line; and the signal detection line FDL corresponds to the claimed interconnect. In the rejection below, the mapping of elements has been changed, such that the capacitance interconnect 40 corresponds to the claimed first boost line; the signal detection line FDL corresponds to the claimed second boost line; and the intermediate interconnect 50 corresponds to the claimed interconnect. Therefore, the interconnect (intermediate interconnect 50) is provided between the first boost line (capacitance interconnect 40) and the second boost line (signal detection line FDL).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 and 16-17 of U.S. Patent No. 11,722,793 B2 in view of Yamashita et al. (US 2015/0077611 A1, cited in IDS).
Instant Application
U.S. Patent No. 11,722,793 B2
1. An imaging device, comprising:
a pixel unit of a plurality of pixels, wherein each pixel of the plurality of pixels includes:
a photoelectric conversion unit;
a holding unit;
a plurality of floating diffusions shared among the plurality of pixels;
a plurality of boost lines that includes a first boost line and a second boost line, wherein
the first boost line has a different shape from the second boost line in a plan view; and
an interconnect line,
wherein the first boost line and the second boost line are adjacent to the interconnect line, and
the interconnect line is between the first boost line and the second boost line.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit;
a holding unit;
a plurality of floating diffusions shared among the plurality of pixels; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
the first boost line is different from the second boost line, and
the second boost line is in contact with a gate of the amplification transistor; and
an interconnect line configured to connect the plurality of floating diffusions, wherein the interconnect line is parallel to the first boost line.
7. The imaging device according to claim 1, wherein the first boost line is within a proximity of the interconnect line.
2. The imaging device according to claim 1, wherein the photoelectric conversion unit is configured to:
receive light;
convert the received light into electric charge; and
output the electric charge.
2. The imaging device according to claim 1, wherein the photoelectric conversion unit is configured to:
receive light;
convert the received light into electric charge; and
output the electric charge.
3. The imaging device according to claim 2, wherein the holding unit is configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge.
3. The imaging device according to claim 2, wherein the holding unit is configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge.
4. The imaging device according to claim 3, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit.
4. The imaging device according to claim 3, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit.
5. The imaging device according to claim 1, wherein each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions.
5. The imaging device according to claim 1, wherein each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions.
6. The imaging device according to claim 1, wherein the imaging device is configured to capture an image based on a global shutter system.
6. The imaging device according to claim 1, wherein the imaging device is configured to capture an image based on a global shutter system.
7. The imaging device according to claim 1, wherein the first boost line and the interconnect line are in a same layer of the imaging device.
8. The imaging device according to claim 7, wherein the first boost line and the interconnect line are in the same layer of the imaging device.
8. The imaging device according to claim 1, wherein the first boost line and the interconnect line are in different layers of the imaging device.
9. The imaging device according to claim 7, wherein the first boost line and the interconnect line are in different layers of the imaging device.
9. The imaging device according to claim 1, wherein
each pixel of the plurality of pixels further includes an amplification transistor, and
the amplification transistor is configured to output a voltage signal corresponding to a potential of a floating diffusion of the plurality of floating diffusions.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit;
a holding unit;
a plurality of floating diffusions shared among the plurality of pixels; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
the first boost line is different from the second boost line, and
the second boost line is in contact with a gate of the amplification transistor; and
an interconnect line configured to connect the plurality of floating diffusions, wherein the interconnect line is parallel to the first boost line.
10. The imaging device according to claim 1, wherein the amplification transistor is configured to output a voltage signal corresponding to a potential of a floating diffusion of the plurality of floating diffusions.
10. The imaging device according to claim 1, further comprising a switching unit configured to switch a capacitance of the plurality of floating diffusions.
11. The imaging device according to claim 1, further comprising a switching unit configured to switch a capacitance of the plurality of floating diffusions.
11. The imaging device according to claim 3, further comprising a readout gate configured to read out the electric charge from the holding unit, wherein the readout gate is in a vertical direction relative to the photoelectric conversion unit and in a horizontal direction relative to the photoelectric conversion unit.
12. The imaging device according to claim 3, further comprising a readout gate configured to read out the electric charge from the holding unit, wherein the readout gate is in a vertical direction and in a horizontal direction relative to the photoelectric conversion unit.
12. The imaging device according to claim 2, wherein each pixel of the plurality of pixels is configured to read out the electric charge from the photoelectric conversion unit based on a charge coupled device (CCD) system.
13. The imaging device according to claim 2, wherein each pixel of the plurality of pixels is configured to read out the electric charge from the photoelectric conversion unit based on a CCD system.
13. The imaging device according to claim 1, further comprising:
a conversion interconnect outside the first boost line; and
a switching unit configured to:
control a connection between the interconnect line and the conversion interconnect; and
control capacitance of the plurality of floating diffusions.
16. The imaging device according to claim 7, further comprising:
a conversion interconnect outside the first boost line; and
a switching unit configured to:
control a connection between the interconnect line and the conversion interconnect, and
control capacitance of the plurality of floating diffusions.
14. An electronic device, comprising:
an imaging device that includes:
a pixel unit of a plurality of pixels, wherein each pixel of the plurality of pixels includes:
a photoelectric conversion unit;
a holding unit;
a plurality of floating diffusions shared among the plurality of pixels;
a plurality of boost lines that includes a first boost line and a second boost line, wherein
the first boost line has a different shape from the second boost line in a plan view; and
an interconnect line,
wherein the first boost line and the second boost line are adjacent to the interconnect line; and
the interconnect line is between the first boost line and the second boost line; and
a processing unit configured to process a signal from the imaging device.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit;
a holding unit;
a plurality of floating diffusions shared among the plurality of pixels; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
the first boost line is different from the second boost line, and
the second boost line is in contact with a gate of the amplification transistor; and
an interconnect line configured to connect the plurality of floating diffusions, wherein the interconnect line is parallel to the first boost line.
7. The imaging device according to claim 1, wherein the first boost line is within a proximity of the interconnect line.
15. The imaging device according to claim 1, further comprising a control line orthogonal to a part of the interconnect line, wherein the control line is configured to control application of a voltage to the first boost line.
14. The imaging device according to claim 7, further comprising a control line orthogonal to the interconnect line, wherein the control line is configured to control application of a voltage to the first boost line.
*Please note that the underlined portions represent the limitations not encompassed by the claims of the referenced patent.
Claim 1 is encompassed by claims 1 and 7 of U.S. Patent No. 11,722,793 B2, except for the limitation “the first boost line has a different shape from the second boost line in a plan view; and… wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line”.
Yamashita et al. teaches that the first boost line has a different shape from the second boost line in a plan view (Fig.8: capacitance interconnect 40 corresponds to the claimed first boost line; signal detection line FDL corresponds to the claimed second boost line. As shown in Fig.8, the capacitance interconnect 40 and the signal detection line FDL have different shapes); and …wherein the first boost line and the second boost line are adjacent to the interconnect line (Fig.8: the intermediate interconnect 50 corresponds to the claimed second boost line; [0183]: “The arrangement position of the intermediate interconnect 50 in a pixel array 12 overlaps the capacitance interconnect 40 and signal detection line FDL in a direction perpendicular to the front surface of the semiconductor substrate 30”. That is, both capacitance interconnect 40/first boost line and the signal detection line FDL/second boost line are adjacent to the intermediate interconnect 50/interconnect line), and the interconnect line is between the first boost line and the second boost line ([0183]: “An intermediate interconnect 50 is provided between the capacitance interconnect 40 and signal detection line FDL”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1 and 7 of U.S. Patent No. 11,722,793 B2 with the teaching of Yamashita et al. such that the first boost line has a different shape from the second boost line in a plan view; and wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line, so as to form capacitive coupling between the boost lines and the interconnect line, thereby properly boosting the floating diffusion.
Claim 14 is encompassed by claims 1 and 7 of U.S. Patent No. 11,722,793 B2, except for the limitation “the first boost line has a different shape from the second boost line in a plan view; and … wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line; and a processing unit configured to process a signal from the imaging device”.
Yamashita et al. teaches that the first boost line has a different shape from the second boost line in a plan view (Fig.8: capacitance interconnect 40 corresponds to the claimed first boost line; signal detection line FDL corresponds to the claimed second boost line. As shown in Fig.8, the capacitance interconnect 40 and the signal detection line FDL have different shapes); and …wherein the first boost line and the second boost line are adjacent to the interconnect line (Fig.8: the intermediate interconnect 50 corresponds to the claimed second boost line; [0183]: “The arrangement position of the intermediate interconnect 50 in a pixel array 12 overlaps the capacitance interconnect 40 and signal detection line FDL in a direction perpendicular to the front surface of the semiconductor substrate 30”. That is, both capacitance interconnect 40/first boost line and the signal detection line FDL/second boost line are adjacent to the intermediate interconnect 50/interconnect line), and the interconnect line is between the first boost line and the second boost line ([0183]: “An intermediate interconnect 50 is provided between the capacitance interconnect 40 and signal detection line FDL”); and a processing unit configured to process a signal from the imaging device (Fig.1; [0029]: signal processing circuit 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1 and 7 of U.S. Patent No. 11,722,793 B2 with the teaching of Yamashita et al. such that the first boost line has a different shape from the second boost line in a plan view; and wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line; and a processing unit configured to process a signal from the imaging device, so as to form capacitive coupling between the boost lines and the interconnect line, thereby properly boosting the floating diffusion; it would also have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1 and 7 of U.S. Patent No. 11,722,793 B2 with the teaching of Yamashita et al. to have a processing unit configured to process a signal from the imaging device, so as to perform various image processing tasks to enhance image quality within the camera.
Claims 1-15 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 and 13 of U.S. Patent No. 11,330,203 B2 in view of Yamashita et al. (US 2015/0077611 A1, cited in IDS).
Instant Application
U.S. Patent No. 11,330,203 B2
1. An imaging device, comprising:
a pixel unit of a plurality of pixels, wherein each pixel of the plurality of pixels includes:
a photoelectric conversion unit;
a holding unit;
a plurality of floating diffusions shared among the plurality of pixels;
a plurality of boost lines that includes a first boost line and a second boost line, wherein
the first boost line has a different shape from the second boost line in a plan view; and
an interconnect line,
wherein the first boost line and the second boost line are adjacent to the interconnect line, and
the interconnect line is between the first boost line and the second boost line.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit configured to:
receive light;
convert the received light into electric charge; and
output the electric charge;
a holding unit configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge;
a plurality of floating diffusions shared among the plurality of pixels, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit;
an interconnect line configured to connect the plurality of floating diffusions; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions,
the first boost line is different from the second boost line,
the first boost line is parallel to the interconnect line, and
the second boost line is in contact with a gate of the amplification transistor.
3. The imaging device according to claim 1, wherein the first boost line is within a proximity of the interconnect line.
2. The imaging device according to claim 1,
wherein the photoelectric conversion unit is configured to:
receive light;
convert the received light into electric charge; and
output the electric charge.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit configured to:
receive light;
convert the received light into electric charge; and
output the electric charge;
a holding unit configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge;
a plurality of floating diffusions shared among the plurality of pixels, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit;
an interconnect line configured to connect the plurality of floating diffusions; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions,
the first boost line is different from the second boost line,
the first boost line is parallel to the interconnect line, and
the second boost line is in contact with a gate of the amplification transistor.
3. The imaging device according to claim 2,
wherein the holding unit is configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit configured to:
receive light;
convert the received light into electric charge; and
output the electric charge;
a holding unit configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge;
a plurality of floating diffusions shared among the plurality of pixels, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit;
an interconnect line configured to connect the plurality of floating diffusions; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions,
the first boost line is different from the second boost line,
the first boost line is parallel to the interconnect line, and
the second boost line is in contact with a gate of the amplification transistor.
4.The imaging device according to claim 3,
wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit configured to:
receive light;
convert the received light into electric charge; and
output the electric charge;
a holding unit configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge;
a plurality of floating diffusions shared among the plurality of pixels, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit;
an interconnect line configured to connect the plurality of floating diffusions; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions,
the first boost line is different from the second boost line,
the first boost line is parallel to the interconnect line, and
the second boost line is in contact with a gate of the amplification transistor.
5.The imaging device according to claim 1,
wherein each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit configured to:
receive light;
convert the received light into electric charge; and
output the electric charge;
a holding unit configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge;
a plurality of floating diffusions shared among the plurality of pixels, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit;
an interconnect line configured to connect the plurality of floating diffusions; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions,
the first boost line is different from the second boost line,
the first boost line is parallel to the interconnect line, and
the second boost line is in contact with a gate of the amplification transistor.
6. The imaging device according to claim 1, wherein the imaging device is configured to capture an image based on a global shutter system.
2. The imaging device according to claim 1, wherein the imaging device is configured to capture an image based on a global shutter system.
7. The imaging device according to claim 1, wherein the first boost line and the interconnect line are in a same layer of the imaging device.
4. The imaging device according to claim 3, wherein the first boost line and the interconnect line are in the same layer of the imaging device.
8. The imaging device according to claim 1, wherein the first boost line and the interconnect line are in different layers of the imaging device.
5. The imaging device according to claim 3, wherein the first boost line and the interconnect line are in different layers of the imaging device.
9. The imaging device according to claim 1, wherein
each pixel of the plurality of pixels further includes an amplification transistor, and
the amplification transistor is configured to output a voltage signal corresponding to a potential of a floating diffusion of the plurality of floating diffusions.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit configured to:
receive light;
convert the received light into electric charge; and
output the electric charge;
a holding unit configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge;
a plurality of floating diffusions shared among the plurality of pixels, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit;
an interconnect line configured to connect the plurality of floating diffusions; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions,
the first boost line is different from the second boost line,
the first boost line is parallel to the interconnect line, and
the second boost line is in contact with a gate of the amplification transistor.
6. The imaging device according to claim 1, wherein the amplification transistor is configured to output a voltage signal corresponding to a potential of a floating diffusion of the plurality of floating diffusions.
10. The imaging device according to claim 1, further comprising a switching unit configured to switch a capacitance of the plurality of floating diffusions.
7. The imaging device according to claim 1, further comprising a switching unit configured to switch a capacitance of the plurality of floating diffusions.
11. The imaging device according to claim 3, further comprising a readout gate configured to read out the electric charge from the holding unit, wherein the readout gate is in a vertical direction relative to the photoelectric conversion unit and in a horizontal direction relative to the photoelectric conversion unit.
8. The imaging device according to claim 1, further comprising a readout gate configured to read out the electric charge from the holding unit, wherein the readout gate is in a vertical direction and in a horizontal direction relative to the photoelectric conversion unit.
12. The imaging device according to claim 2, wherein each pixel of the plurality of pixels is configured to read out the electric charge from the photoelectric conversion unit based on a charge coupled device (CCD) system.
9. The imaging device according to claim 1, wherein each pixel of the plurality of pixels is configured to read out the electric charge from the photoelectric conversion unit based on a CCD system.
13. The imaging device according to claim 1, further comprising:
a conversion interconnect outside the first boost line; and
a switching unit configured to:
control a connection between the interconnect line and the conversion interconnect; and
control capacitance of the plurality of floating diffusions.
13. The imaging device according to claim 1, further comprising:
a conversion interconnect outside the first boost line; and
a switching unit configured to:
control a connection between the interconnect line and the conversion interconnect, and
control capacitance of the plurality of floating diffusions.
14. An electronic device, comprising:
an imaging device that includes:
a pixel unit of a plurality of pixels, wherein each pixel of the plurality of pixels includes:
a photoelectric conversion unit;
a holding unit;
a plurality of floating diffusions shared among the plurality of pixels;
a plurality of boost lines that includes a first boost line and a second boost line, wherein
the first boost line has a different shape from the second boost line in a plan view; and
an interconnect line,
wherein the first boost line and the second boost line are adjacent to the interconnect line; and
the interconnect line is between the first boost line and the second boost line; and
a processing unit configured to process a signal from the imaging device.
1. An imaging device, comprising:
a plurality of pixels, wherein each pixel of the plurality of pixels includes:
an amplification transistor;
a photoelectric conversion unit configured to:
receive light;
convert the received light into electric charge; and
output the electric charge;
a holding unit configured to:
receive the electric charge output from the photoelectric conversion unit; and
hold the received electric charge;
a plurality of floating diffusions shared among the plurality of pixels, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and
hold the electric charge received from the holding unit;
an interconnect line configured to connect the plurality of floating diffusions; and
a plurality of boost lines that includes a first boost line and a second boost line, wherein
each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions,
the first boost line is different from the second boost line,
the first boost line is parallel to the interconnect line, and
the second boost line is in contact with a gate of the amplification transistor.
3. The imaging device according to claim 1, wherein the first boost line is within a proximity of the interconnect line.
15. The imaging device according to claim 1, further comprising a control line orthogonal to a part of the interconnect line, wherein the control line is configured to control application of a voltage to the first boost line.
10. The imaging device according to claim 3, further comprising a control line orthogonal to the interconnect line, wherein the control line is configured to control application of a voltage to the first boost line.
*Please note that the underlined portions represent the limitations not encompassed by the claims of the referenced patent.
Claim 1 is encompassed by claims 1 and 3 of U.S. Patent No. 11,330,203 B2, except for the limitation “the first boost line has a different shape from the second boost line in a plan view; and… wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line”.
Yamashita et al. teaches that the first boost line has a different shape from the second boost line in a plan view (Fig.8: capacitance interconnect 40 corresponds to the claimed first boost line; signal detection line FDL corresponds to the claimed second boost line. As shown in Fig.8, the capacitance interconnect 40 and the signal detection line FDL have different shapes); and …wherein the first boost line and the second boost line are adjacent to the interconnect line (Fig.8: the intermediate interconnect 50 corresponds to the claimed second boost line; [0183]: “The arrangement position of the intermediate interconnect 50 in a pixel array 12 overlaps the capacitance interconnect 40 and signal detection line FDL in a direction perpendicular to the front surface of the semiconductor substrate 30”. That is, both capacitance interconnect 40/first boost line and the signal detection line FDL/second boost line are adjacent to the intermediate interconnect 50/interconnect line), and the interconnect line is between the first boost line and the second boost line ([0183]: “An intermediate interconnect 50 is provided between the capacitance interconnect 40 and signal detection line FDL”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1 and 7 of U.S. Patent No. 11,330,203 B2 with the teaching of Yamashita et al. such that the first boost line has a different shape from the second boost line in a plan view; and wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line, so as to form capacitive coupling between the boost lines and the interconnect line, thereby properly boosting the floating diffusion.
Claim 14 is encompassed by claims 1 and 3 of U.S. Patent No. 11,330,203 B2, except for the limitation “the first boost line has a different shape from the second boost line in a plan view; and … wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line; and a processing unit configured to process a signal from the imaging device”.
Yamashita et al. teaches that the first boost line has a different shape from the second boost line in a plan view (Fig.8: capacitance interconnect 40 corresponds to the claimed first boost line; signal detection line FDL corresponds to the claimed second boost line. As shown in Fig.8, the capacitance interconnect 40 and the signal detection line FDL have different shapes); and …wherein the first boost line and the second boost line are adjacent to the interconnect line (Fig.8: the intermediate interconnect 50 corresponds to the claimed second boost line; [0183]: “The arrangement position of the intermediate interconnect 50 in a pixel array 12 overlaps the capacitance interconnect 40 and signal detection line FDL in a direction perpendicular to the front surface of the semiconductor substrate 30”. That is, both capacitance interconnect 40/first boost line and the signal detection line FDL/second boost line are adjacent to the intermediate interconnect 50/interconnect line), and the interconnect line is between the first boost line and the second boost line ([0183]: “An intermediate interconnect 50 is provided between the capacitance interconnect 40 and signal detection line FDL”); and a processing unit configured to process a signal from the imaging device (Fig.1; [0029]: signal processing circuit 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1 and 7 of U.S. Patent No. 11,330,203 B2 with the teaching of Yamashita et al. such that the first boost line has a different shape from the second boost line in a plan view; and wherein the first boost line and the second boost line are adjacent to the interconnect line, and the interconnect line is between the first boost line and the second boost line; and a processing unit configured to process a signal from the imaging device, so as to form capacitive coupling between the boost lines and the interconnect line, thereby properly boosting the floating diffusion; it would also have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1 and 7 of U.S. Patent No. 11,330,203 B2 with the teaching of Yamashita et al. to have a processing unit configured to process a signal from the imaging device, so as to perform various image processing tasks to enhance image quality within the camera.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 12, 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2015/0077611 A1, cited in IDS) in view of Mabuchi (US 2011/0242378 A1, cited in IDS).
As to claim 1, Yamashita et al. discloses an imaging device (Fig.1: image sensor 10), comprising:
a pixel unit of a plurality of pixels (Fig.3: unit cells UC), wherein each pixel of the plurality of pixels includes:
a photoelectric conversion unit (Fig.3; [0060]: photodiodes (pixels) 21A, 21B);
a plurality of floating diffusions (Fig.3: floating diffusion FD 6) shared among the plurality of pixels (Fig.3; [0061]: FD 6 is commonly used for the two photodiodes 21A an 21B);
a plurality of boost lines that includes a first boost line (Fig. 8: capacitance interconnect 40) and a second boost line (Fig.8: signal detection line FDL), wherein
the first boost line has a different shape from the second boost line in a plan view (Fig.8: capacitance interconnect 40 corresponds to the claimed first boost line; signal detection line FDL corresponds to the claimed second boost line. As shown in Fig.8, the capacitance interconnect 40 and the signal detection line FDL have different shapes); and
an interconnect line (Fig.8: intermediate interconnect 50 corresponds to the claimed interconnect line), wherein the first boost line and the second boost line are adjacent to the interconnect line (Fig.8; [0183]: “The arrangement position of the intermediate interconnect 50 in a pixel array 12 overlaps the capacitance interconnect 40 and signal detection line FDL in a direction perpendicular to the front surface of the semiconductor substrate 30”. That is, both capacitance interconnect 40/first boost line and the signal detection line FDL/second boost line are adjacent to the intermediate interconnect 50/interconnect line), and
the interconnect line is between the first boost line and the second boost line ([0183]: “An intermediate interconnect 50 is provided between the capacitance interconnect 40 and signal detection line FDL”).
Yamashita et al. fails to disclose a holding unit.
However, Mabuchi teaches a holding unit (Fig.3: memory section 172 and memory section 174).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamashita et al. with the teaching of Mabuchi to have a holding unit, so as to improve the image quality of moving image imaging using a global shutter ([0011]).
As to claim 2, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, wherein the photoelectric conversion unit is configured to:
receive light (Yamashita et al.: [0039]: “…light incident on the photodiode 21”);
convert the received light into electric charge (Yamashita et al.: [0064]: “Each of the photodiodes 21A, 21B converts light that passes the microlens and color filter and is made incident on the photodiode into signal charges (electrical signal) and stores the charges”); and
output the electric charge (Yamashita et al.: [0063-0068]: the read transistors 22A and 22B control the readout of the signal charges of the photodiodes 21A and 21B, and store the signal charges in FD 6).
As to claim 3, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 2, wherein the holding unit is configured to:
receive the electric charge output from the photoelectric conversion unit (Mabuchi: [0091]: the signal electric charge S1 accumulated in the photodiode 141 is transferred to the memory section 172 of the first CCD 142); and
hold the received electric charge (Mabuchi: [0093]: at time t10, “the signal electric charge S1 accumulated in the memory section 172 of the first CCD 142 is transferred to the memory section 174 of the second CCD 143”. [0103]: at time t15, “the signal electric charge S1 accumulated in the memory section 174 of the second CCD 143 is transferred to the floating diffusion region 145”. In other words, the memory sections 172 and 174 temporarily hold the received electric charge).
As to claim 4, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 3, wherein each floating diffusion of the plurality of floating diffusions is configured to:
receive the electric charge from the holding unit; and hold the electric charge received from the holding unit (Mabuchi: [0103]: at time t15, “the signal electric charge S1 accumulated in the memory section 174 of the second CCD 143 is transferred to the floating diffusion region 145”).
As to claim 5, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, wherein each boost line of the plurality of boost lines is configured to boost the plurality of floating diffusions (Yamashita et al.: [0079]: “if voltage Vboost is supplied to the capacitance interconnects 40, and the potentials of the capacitance interconnects 40 are boosted”. [0117]: “the potential of the floating diffusion 6 is boosted to a relatively high voltage according to a variation in the potential of vertical signal line VSL by the capacitance element 40A provided between the capacitance interconnect 40 and the floating diffusion 6”. In other words, the voltage Vboost supplied to the capacitance interconnects 40 boosts the potential of the floating diffusion 6. On the other hand, [0184] discloses that “Capacitive coupling occurring between the intermediate interconnect 50 and signal detection line FDL functions as the capacitive element 40A connected between the floating diffusion and the capacitance interconnect 40”; that is, intermediate interconnect 50 also helps boosting the floating diffusion).
As to claim 6, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, wherein the imaging device is configured to capture an image based on a global shutter system (Yamashita et al.: [0011]).
As to claim 7, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, wherein the first boost line and the interconnect line are in a same layer of the imaging device (Yamashita et al.: Fig.2; [0049]: the interlayer insulating film 90 has a multilayer interconnect structure. Fig.9; [0180-0181], [0183]: the first boost line/capacitance interconnect 40 is provided at third interconnect level M3 of the interlayer insulating film 90; the interconnect line/intermediate interconnect 50 is provided at second interconnect level M2 of the interlayer insulating film 90. That is, they are both in the interlayer insulating film 90).
As to claim 8, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, wherein the first boost line and the interconnect line are in different layers of the imaging device (Yamashita et al.: Fig.9; [0181]: capacitance interconnect 40 is provided at third interconnect level M3, and the interconnect line/intermediate interconnect 50 is provided at second interconnect level M2).
As to claim 9, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, wherein
each pixel of the plurality of pixels further includes an amplification transistor (Yamashita et al.: Fig.3: amplifier transistor 26), and
the amplification transistor is configured to output a voltage signal corresponding to a potential of a floating diffusion of the plurality of floating diffusions (Yamashita et al.: [0068]: “The amplifier transistor 26 amplifies a signal from the photodiode 21 stored by the floating diffusion 6”).
As to claim 10, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, further comprising a switching unit configured to switch a capacitance of the plurality of floating diffusions (Yamashita et al.: Fig.3; [0079]: the transistor 43 corresponds to the claimed switching unit).
As to claim 12, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 2, wherein each pixel of the plurality of pixels is configured to read out the electric charge from the photoelectric conversion unit based on a charge coupled device (CCD) system (Mabuchi: Fig.3: the signal electric charge is read out from the photodiode to the first CCD 142, and then transferred to the second CCD 143).
As to claim 14, Yamashita et al. discloses an electronic device (Fig.1: solid-state imaging device 5), comprising:
an imaging device (Fig.1: image sensor 10) that includes:
a pixel unit of a plurality of pixels (Fig.3: unit cells UC), wherein each pixel of the plurality of pixels includes:
a photoelectric conversion unit (Fig.3; [0060]: photodiodes (pixels) 21A, 21B);
a plurality of floating diffusions shared among the plurality of pixels (Fig.3: floating diffusion FD 6) shared among the plurality of pixels (Fig.3; [0061]: FD 6 is commonly used for the two photodiodes 21A an 21B);
a plurality of boost lines that includes a first boost line and a second boost line (Fig. 8: capacitance interconnect 40) and a second boost line (Fig.8: signal detection line FDL), wherein
the first boost line has a different shape from the second boost line in a plan view (Fig.8: capacitance interconnect 40 corresponds to the claimed first boost line; signal detection line FDL corresponds to the claimed second boost line. As shown in Fig.8, the capacitance interconnect 40 and the signal detection line FDL have different shapes); and
an interconnect line (Fig.8: intermediate interconnect 50 corresponds to the claimed interconnect line), wherein the first boost line and the second boost line are adjacent to the interconnect line (Fig.8; [0183]: “The arrangement position of the intermediate interconnect 50 in a pixel array 12 overlaps the capacitance interconnect 40 and signal detection line FDL in a direction perpendicular to the front surface of the semiconductor substrate 30 That is, both capacitance interconnect 40/first boost line and the signal detection line FDL/second boost line are adjacent to the intermediate interconnect 50/interconnect line), and
the interconnect line is between the first boost line and the second boost line ([0183]: “An intermediate interconnect 50 is provided between the capacitance interconnect 40 and signal detection line FDL”)
a processing unit configured to process a signal from the imaging device (Fig.1; [0029]: signal processing circuit 11).
Yamashita et al. fails to disclose a holding unit.
However, Mabuchi teaches a holding unit (Fig.3: memory section 172 and memory section 174).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamashita et al. with the teaching of Mabuchi to have a holding unit, so as to improve the image quality of moving image imaging using a global shutter ([0011]).
As to claim 17, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 1, wherein
a part of the first boost line is parallel to the interconnect line (Yamashita et al.: Fig.8: the first boost line/capacitance interconnect 40 is parallel to the interconnect line/intermediate interconnect 50),
a first part of the second boost line is parallel to the interconnect line (Yamashita et al.: Fig.8: the vertical portion of the second boost line/signal detection line FDL is parallel to the interconnect line/intermediate interconnect 50), and
a second part of the second boost line is orthogonal to the interconnect line (Yamashita et al.: Fig.8: the horizontal portion of the second boost line/signal detection line FDL is orthogonal to the interconnect line/intermediate interconnect 50).
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 2015/0077611 A1, cited in IDS) in view of Mabuchi (US 2011/0242378 A1, cited in IDS) as applied to claim 1 above, and further in view of Zheng et al. (US 2019/0355778 A1, cited in previous Office Action).
As to claim 11, Yamashita et al. in view of Mabuchi discloses the imaging device according to claim 3, further comprising a readout gate (Mabuchi: Fig.3: transfer gate 44) configured to read out the electric charge from the holding unit (Mabuchi: [0077]: “the floating diffusion region 145 holds the electric charge transferred from the memory section 174 by the transfer gate 44 to be read out as a signal”).
The above combination fails to disclose wherein the readout gate is in a vertical direction relative to the photoelectric conversion unit and in a horizontal direction relative to the photoelectric conversion unit.
However, Zheng et al. teaches the readout gate is formed in a vertical direction relative to the photoelectric conversion unit and in a horizontal direction relative to the photoelectric conversion unit (Fig.1; [0016]: “As illustrated, vertical transfer transistor 109 extends into the frontside of semiconductor material 101, and the gate terminal of vertical transfer transistor 115 is substantially "T"-shaped”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yamashita et al. and Mabuchi with the teaching of Zheng et al. to have the readout gate formed in a vertical direction relative to the photoelectric conversion unit and in a horizontal direction relative to the photoelectric conversion unit, so as to reduce blooming, reduce electrical crosstalk, improved global reset, and reduce pulse time, thereby improving the image sensor performance ([0012]).
Allowable Subject Matter
Claims 13 and 15 would be allowable if the double patenting rejection set forth in this Office action is overcome and include all of the limitations of the base claim and any intervening claims.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Manabe (US 2014/0299925 A1) discloses mechanisms to improve potential well characteristics in a pixel cell, which has a reset shield line that operate as a floating diffusion boost line, where shielding characteristics of the shield line are improved by a boost signal being carried in the reset shield line.
Kim et al. (US 2006/0261431 A1) discloses a unit pixel of a complementary metal-oxide semiconductor (CMOS) image sensor includes a photoelectric conversion element, a transfer transistor, a boosting capacitor and a signal transfer circuit, where the photoelectric conversion element generates a charge based on incident light, the transfer transistor transfers the charge to a floating diffusion node in response to a transfer control signal, the boosting capacitor is disposed between a gate of the transfer transistor and the floating diffusion node.
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/ZHENZHEN WU/Examiner, Art Unit 2637
/SINH TRAN/Supervisory Patent Examiner, Art Unit 2637