DETAILED ACTION
This action is responsive to the Applicant’s response filed 9/30/26.
As indicated in Applicant’s response, claims 1, 18-20, 22-23 have been amended, claims 14-17, 24-31 cancelled and claim 32 added. Claims 1-13, 18-23, and 32 remain and are pending prosecution by an office action, as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 9-10, 32, 18 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner) in view of Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman) and Wu, Muh, USPN: 6,427,200 (herein Wu) and KR 101516580 (translation), 05-11-2015, 19 pgs (herein '580), further in view of Liu, USPubN: 2022/0391280 (herein Liu) and Chow et al, USPubN: 2008/0250195 (herein Chow)
As per claim 1, Rosner discloses a system, comprising:
memory including a first physical address space (locations are accessible via physical address (PA) - para 0028) that includes a first physical address (starting at Pax - para 0034; base physical address - para 0069) and a second physical address space that includes a second physical address (PA0, PA1 432 - Fig. 4; physical addresses starting at - para 0037);
a processor coupled to the memory;
a first address mapper circuit (remap 110 – Figs 1) coupled between the memory and the processor, the first address mapper circuit configured to map a first logical address to the first physical address (LA PA mapping – para 0059; LA PA mapping - para 0031; LA PA mapping 1564-8; 1564-10 - Fig. 15);
wherein the processor is configured to
produce a first value (control circuitry 112 in response to one or more instructions from controller 104 – para 0037) at the control terminal to pass the first physical address (Physical address Pax - para 0035; NOVO array: current image 114, PAx – Fig. 1A) so the processor executes a first resource (current firmware image is read … which can start at Pax – pare 0035) during a first time, and
while executing a firmware update resource, produce a second value (one or more instructions from controller 104 – para 0037; “LA_FW=PAy” being programmed into 110-1 – para 0038) at the control terminal to pass the second physical address (new firmware image 118 can occupy a physical address starting at PAy – para 0037; image at PAx becomes invalid … firmware image 118 at PAy becomes the current … image – para 0039) so the processor executes a second resource (image 118 – Fig. 1C, 1D) during a second time after the first time (controller 104 can program the new firmware image 118 – para 0037; 110-1: VAL| LA_FW= PAy – Fig. 1D).
Rosner does not explicitly disclose address mapper circuit in terms of
a first address mapper circuit and a second address mapper circuit coupled between the memory and the processor in parallel with the first address mapper circuit, the second address mapper circuit configured to map the first logical address to a second physical address that differs from the first physical address; and
a multiplexor having a first input, a second input, a control input, and an output, the first data input coupled to an output of the first address mapper circuit, the second data input coupled to an output of the second address mapper circuit, and the control terminal coupled to the processor
'580 discloses non-volatile memory device as comprising non-volatile memory cells, EEPROM,, flash memory, etc. coupled to a solid state drive controller including itself plurality of address translation units, in form of address conversion CPUs, each of which receiving a plurality of
channels included in the nonvolatile memory device (bottom pg. 5 to pg. 6) and use an address mapping table to contain all logical-physical address conversion to support plurality of address
conversion CPUs whose processing can be performed in parallel per a single flash translation layer
configured to solve potential bottleneck phenomenon; where accordingly, the ranges of channels controlled by the plurality of address conversion CPUs may not overlap each other (middle pg. 6), each address translation CPU performing a logical-to-physical address translation for at least one of the plurality of channels (pg. 4); where the simultaneous operation of the plurality of address translation CPUs or flash memory controllers of the nonvolatile memory device has a multi-channel parallel array structure enabling the address translation entities to perform in parallel (pg. 8)
Venkatraman discloses a plurality of memory mappers (mappers 802a 802n - Fig. 8) coupled in parallel to input of a multiplexer (para 0051), each mapper with outgoing pins whose lower bits are used to generate address for corresponding memory locations (para 0047), under selection by select chip (para 0050) which uses the upper bits from each respective mapper - in conjunction with a reconfigurable memory controller (para 0052-0055) per intermediary of bus keepers - to issue a MUX control signal as to which address bits being selected from a given mapper to be outputted onto the bus line (Fig. 9). Hence, first and second address mapper separately connected from their output to input lines of a multiplexer so that control signal by a controller selects which selected address bits from either first mapper or a second mapper to be released from the MUX is recognized
Wu also discloses plural address bits being passed from pin outs of one or more address
mappers to input of a multiplexer (Fig. 4) such that the output from the latter (e.g. address range) is
enabled by a selector's output control (priority encoder 34) - i.e. via a mask-based comparator
processing the high-bits supplied from each address mapper (col.6, li. 58 to col. 7 li. 26), whereby,
based on the signal bit from the selector, the multiplexer knows exactly the physical address of a
pertinent mapper to pass to its output. Hence first and second address mapper connected at their output to lines into a multiplexer SO that output from the MUX under control by a selector/encoder enable a selected address bits from either first mapper or a second mapper to be released from the MUX is recognized
Therefore, based on the possibility of large scale address translation or multiple memory
mappers forming a LP address conversion workload into Rosner's NV memory environment and
associated burden for handling plurality of simultaneous channels of address translation with
minimized bottleneck and channel overlap as set forth above in 580, it would have been obvious for
one of ordinary skill in the art before the effective filing date of the invention to implement
capability of perform logical-physical address translation in Rosner so that memory mapper entities
associated with the NV memory environment would include:
at least two or more memory mapper units - as per the plurality of address translation
processors in '580 - including at least a first address mapper circuit and a second address mapper
circuit, both coupled to the processor; and aligned into a multiplexor - as per Wu's MUX system - having a first data input, a second data input, and an output - as illustrated in the parallel mappers setup by Venkatraman multiplexer setting - in that the first data input coupled to an output of the first address mapper circuit, and the second data input coupled to an output of the second address mapper circuit, with a control line coupled to the processor – as in Venkatraman; because
large scale of address conversion workflow associated with plural NV memory operations
such as rewriting address ranges per a firmware replacement most often incur simultaneous and
overwhelming demand for address conversions as set forth above '580, wherein a plurality of incoming requests for L2P directed at a NV memory controller can risk to overflow capacity of the controller without use of accelerator implementation as well as parallelization of the address translation channels, and use of HW implemented with multiple memory mappers operating connected simultaneously into a multiplexed selector as set forth above would not only alleviate overlapping issue caused by size of request channels or solve any overflow effect on a NV controller capability; but would also equip the NV memory controller with a control capacity such that the controller would be able process data in/out between the concurrent mappers and the multiplexer, and decide, via issuing a proper selector signal which among translated address lines from mapper instances can be outputted from the multiplexor, the selective arrangement thereof imparting a level of synchronization that avert bottlenecks and undesirable request contention, improving throughput of the address translation demand for NV 1/O operations as well as preserving the independency with which each memory (L2P) mapper operates in its own channel prior to their being subjected under a multiplexed data selector.
Nor does Rosner explicitly disclose executing a firmware update wherein the processor is configured to
produce a first value at the control terminal of the multiplexor instructing the multiplexer to pass the first physical address to the output of the multiplexor so the processor executes a first resource (during a first time); and
while executing a firmware update resource, produce a second value at the control terminal of the multiplexor instructing the multiplexer to pass the second physical address to the output of the multiplexor so the processor executes a second resource (during a second time after the first time).
Use of a selector to obtain a physical address mapped to a desired portion of a non-volatile memory banks as set forth in Rosner firmware update (para 0036-0037) entails a logical-to-physical (L2P) mapping instance performed using physical address of a current firmware starting at a particular range memory bank (Fig. 1A) and L2P re-mapping (Fig. 1C) after storing the new firmware at a different range (Fig. 1B, 1D; LA_FW=PAy” being programmed into 110-1 – para 0038) of the memory bank; hence a different physical address of a resource in memory can be mapped by a controller (via a remap structure) in relation to second stage of a update process entails distributing of a resource (e.g. firmware image) to different memory ranges as a way to alleviate wear imposed unnecessarily on one memory range location.
Similar to the above, Chow, for instance, discloses a wear leveling algorithm that allows a memory controller to remap logical address to different physical addresses so that data writes can be evenly distributed thereby extending endurance of the multi-level-cell Flash memory (para 0011) using different pages of the flash memory to foster the wear-leveling associated with data writes (para 0042)
Liu discloses memory chip with multiple channels in support of firmware repair (Fig. 1-2) under a controller for running the firmware, including a management scheme by the controller to avert defective memory blocks via remapping the logical address to different physical addresses, using a chip enable signal (para 0065-0066)
Hence, implementing firmware repair via a controller effect of memory remap via translating a logical address to plurality and distinct physical addresses to even out distribution of memory usage, mitigate wear-and-tear or extend usability of physical memory banks is recognized.
Based on possibility to align more than one memory address mapping (L2P) circuitries and selective activation of a range of physical address from one of the L2P mapper unit as set forth above in rationale A, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement the multi L2P mapper arrangement to support firmware repair/update in Rosner so that selection of the desired physical address (PA) can use a multiplexor – as per rationale A from above using Wu and Venkatraman - to pass a given PA outputted from the mapper units, including programming the host processor in the course of firmware update as in Rosner with control capability to
produce a first value (e.g. selector signal as per Wu) at the control terminal of the multiplexor instructing the multiplexer to pass the first physical address to the output of the multiplexor – per Wu and Venkatraman - so the processor executes a first resource during a first time - i.e. address start of the current firmware when no new firmware is identified;
while executing a firmware update resource (as in Rosner), produce a second value (e.g. selector signal as per Wu) at the control terminal of the multiplexor instructing the multiplexer – per Wu and Venkatraman - to pass the second physical address – i.e. different physical address per a remap effect as shown in Liu, Chow - to the output of the multiplexor so the processor executes a second resource – new firmware image at PAy in Rosner NV memory - during a second time after the first time; because
in a scenario where large contention can overwhelm I/O state of physical NV memory, equipping a NV memory controller with a control capacity such that the controller would be able process data in/out between the concurrent mappers and the multiplexer (as set forth above), and decide, via issuing a proper selector signal, which among translated address lines from mapper instances can be outputted from the multiplexor, the selective arrangement thereof to spread out I/O traffic and distributing reads over various physical memory locations would reduce stress on (extend physical lifetime of) particular portions of the memory, alleviate likelihood of bottlenecks and undesirable similar target reads contention, improving thereby throughput of the address translation demand for NV I/O operations as well as preserving the independency with which each memory (L2P) mapper operates in its own channel prior to their being subjected under a multiplexed data selector, which ultimately reduce latency of transition between old firmware and new firmware according to which a continuous and fault free runtime of the system firmware is transparently realized before and after the update.
As per claim 2, Rosner discloses system of claim 1, wherein the memory further
includes the firmware update resource at a a third physical address (in controller memory - para 0036; at memory device 1462-0 - Fig. 14; store in system memory 1564-2 - Fig. 15).
As per claim 9, Rosner discloses system of claim 1, wherein the first physical address
corresponds to the first instruction of the first resource (current firmware - para 0096), and the second physical address corresponds to a first instruction of the second resource (new FW image into non-volatile sectors - para 0098).
As per claim 10, Tasher discloses system of claim 1, wherein a size of the first physical
address space (current firmware image stored in sectors "C" - para 0057) is different from a size
of the second physical address space (new firmware image stored in sectors "N" understood to
be different from and not overlap with sectors "C" - para 0059).
As per claim 32, Rosner discloses a circuit, comprising: a processor; and a memory mapper configured to receive logical addresses from the processor and convert the logical addresses to physical addresses, the memory mapper comprising:
a first address mapper circuit configured to receive a first logical address from the processor and output a first physical address based on the first logical address;
a second address mapper circuit configured to receive the first logical address from the processor and output a second physical address based on the first logical address, the second physical address differing from the first physical address; and
a multiplexor having a first input, a second input, a control input, and an output, the first input configured to receive the first physical address from the first address mapper circuit, the second input configured to receive the second physical address from the second address mapper circuit, and the control terminal coupled to the processor,
wherein the processor is configured to provide a first value to the control terminal of the multiplexor to pass the first physical address to the output of the multiplexor so a first resource can be executed by the processor during a first time, and
while executing a firmware update resource, the processor is configured to provide a second value to the control terminal of the multiplexor to pass the second physical address to the output of the multiplexor so a second resource can be executed by the processor during a second time after the first time.
( All of which having been addressed in claim 1)
As per claim 18, Rosner discloses circuit of claim 32, wherein the circuit comprises memory coupled to the memory mapper (para 0029, 0031-0032).
Claims 3-7, 19-20 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner) in view of Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman) and Wu, Muh, USPN: 6,427,200 (herein Wu) and KR 101516580(translation), 05-11-2015, 19 pgs (herein '580), further in view of Liu, USPubN: 2022/0391280 (herein Liu) and Chow et al, USPubN: 2008/0250195 (herein Chow) and further of Tasher et al, TW I676116B, (translation) 11-01-2019, 20 pgs (herein Tasher)
As per claims 3-4, Rosner does not explicitly disclose system of claim 1,
wherein the processor is configured to perform an authentication of the second resource before remapping the first logical address to the second physical address.
wherein the processor is configured to perform an integrity validation of the second resource before remapping the first logical address to the second physical address.
Rosner discloses a verification process in which FW version at address data pointed by a
logical address (flash memory array having an address range designated for the new firmware - para
0092) is pre-checked to be proper or valid for use (e.g. control circuit can use the remap structure to
determine with LA-PA mapping is valid - para 003 para 0094) using a program to check the NV status to ensure that the latest FW targeted for a remapping is the correct FW version (step 1462-6 -
Fig. 14; para 0094) in that as long as a invalid status persists (INV 110-1 - Fig. IC) in the remap
table structure, the mapping following this check will not take effect (para 0038). Hence a validation of FW data stored at a physical location to be recorded in a remap table prior to commit a relevant remap entails a last check prior to commit a LA PA entry into a remap table.
Tasher discloses performing an authentication of the second resource (signature of APP1,
step 100, step 112, receives an updated version APP 1', security key KEYI calculate signature on
APPI' and VERI; VERI' VERI- pg. 13-14; top pg. 15) before remapping the first LA to a second PA and performing a integrity check (replaces the current version with the received version only after
confirming the integrity and authenticity of the received version - pg. 12) of the second resource
before the LA1-PA1 remapping.
Therefore, as software obtained via a network or download is typically subjected to security
check or integrity verification before use (remap table look-up), it would have been obvious for one
of ordinary skill in the art before the effective filing date of the invention to implement a controller
associated with a firmware update and a remap setup in Rosner so that address information resulting from a remap (LA1-PA1) should first be subjected to verification by the processor, including the latter
performing an authentication of the second resource - as set forth in Tasher – before remapping the first logical address to a second physical address,
performing an integrity validation of the second resource - as set forth in Tasher - before
remapping the first logical address to the second physical address; because
authentication of a new download or acquired firmware targeted to provide functionality to a
system as in Rosner that relies on software-based memory mapping prior to a remap, would ensure
that the prospect software (firmware) is consistent with its identity, version called for by the acquisition so to avoid activation or incorporation of wrong product into core of the host functional
system; and verifying the prospect software with integrity check prior to a remap would ensure that
the intended software when activated for a runtime has retained all of its original content and characteristics in the course of transport/data writing into the memory sectors of the host system, thereby guaranteeing that no undesirable data tampering effects would demise short-term usability of the software or demise long term reliability of the system memory.
As per claim 5, Rosner discloses system of claim 1, wherein the processor is configured to perform a functional validation of the second resource before remapping the first logical address to the second physical address (refer to authentication and integrity check per rationale in claims 3-4 from above)
As per claim 6, Rosner discloses system of claim 5, wherein the processor is configured to:
execute a validation resource (before remapping the first logical address to the second physical address) using a second logical address (e.g. flash memory array having an address range designated for the new firmware - para 0092) to perform the functional validation (see below) of the second resource (new firmware) at the second physical address; and
in response to a successful functional validation (e.g. INV 110-1 - Fig. 1C; mapping will not
be of effect - para 0038) of the second resource (first status value to indicate that the logical address
to physical address for the new firmware image is a valid firmware image - see Abstract; step 1462-6
- Fig. 14; para 0094), remap the first logical address to the second physical address (LA_FW=PAy - Fig. 1D).
As per claim 7, Rosner does not explicitly disclose system of claim 1, wherein the processor is configured to remap the first logical address from the second physical address back to the first physical address in response to a fault during execution of the second resource.
Tasher discloses provision of "rollback" commands in configuring resources for recovery
protection associated with a firmware update according to which logical-physical address mappings
generated under a update "package" carried out by the NV memory controller are used to replace the
stored data items with updated version of the data ("rollback protection" commands - pg. 11)
Hence, a rollback in terms of reverting to a FW version by remapping a logical address back to the physical location in which a previous FW version is stored would have been obvious.
Thus, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement firmware update and remapping of memory associated therewith in Rosner so that the NV memory controller/processor would be configured to perform a recovery rollback - as set forth in Tasher - and remap the first logical address from the second physical address back to the first physical address - where a old/current version of FW is stored - in response to a fault - as in Tasher - during execution of the second resource; because
configuring a system with preventive measure to be able to instantly recover from a firmware update failure such as activating a rollback in which new firmware L2P mapping is logically remapped to address where old firmware is being stored would make the overall functioning of the system transparent with advent of the failure or errors incurred by the firmware update process, since only software-based remapping of physical address is being effected without enlisting of substantial amount of discrete resources from the HW processor, the OS and physical storage to go about keeping the normal flow of the system operation unaffected by a unsuccessful update to the system core firmware; that is, a failed complete process not accomplishing logical-to-physical translation of addresses by a memory remap underlying memory section rewrites as set forth above cannot be left in the state of improper logical-to-physical addresses conversion as this indirection effect can create dire runtime pointer crash at the lower level I/O or BIOS of the operating system, whereas a successful rollback that properly remaps software entity from its current logical memory address to its initial physical address would at least reset the system back to their restored known or seemingly status-quo state.
As per claim 19, Rosner discloses circuit of claim 32, wherein the processor is configured to perform an authentication, an integrity validation, or a functional validation of the second resource before remapping the first logical address to the second physical address.
(refer to rationale of claims 3-4)
As per claim 20, Rosner discloses circuit of claim 32, wherein the processor is configured to perform an authentication, an integrity validation, or a functional validation (para 0031) of the
second resource after configuring the memory mapper to remap the first logical address to the second physical address (Note2: check a FW resource status in accordance with a mapping inside a remap structure - Fig. 1C - reads on performing a functional validation of a FW resource - new firmware image becomes valid, para 0040 - after configuring a remap structure indicative of a first LA pointing to a PA different from the initial PA at which a current FW is stored - see Fig. 1D);
while executing the firmware update resource (refer to claim 1), remap the first logical address back to the first physical address in response to a fault of the authentication, integrity validation, or functional validation of the second resource (refer to rationale of claim 7 using Tasher rollback); and execute the first resource using the first logical address (see remap per Fig 1C, 1D from above).
Claim 8 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner) in view of Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman) and Wu, Muh, USPN: 6,427,200 (herein Wu) and KR 101516580(translation), 05-11-2015, 19 pgs (herein '580), further in view of Liu, USPubN: 2022/0391280 (herein Liu) and Chow et al, USPubN: 2008/0250195 (herein Chow) and further of Tasher et al, TW I676116B, (translation) 11-01-2019, 20 pgs (herein Tasher) and Barczak et al, USPubN: 2023/0139729 (herein Barczak)
As per claim 8, Rosner does not explicitly disclose system of claim 1, wherein the processor is configured to cause freeing of memory locations associated with the first resource after remapping the first logic address to the second physical address.
Barczak discloses translation layer associated with flash memory representing blocks
exposed for virtual machines implementation, the translation layer to map logical addresses of
virtual machines to physical addresses in the non-volatile memory (para 0034), the translation layer
equipped with formation of a mapping table that map logical address with actual clusters in the non -
volatile cache (para 0044) such that a check of a entry in the table indicative of a logical block
address being unrepresented by a cluster will have for effect to free (para 0043) the cluster from the
mapping followed with updating the table as part of managing free chunks (Fig. 6; Deallocate
clusters 704 - Fig. 7) in the non-volatile cache (para 0041); hence, memory resources unused in
accordance with mapping of logical addresses to their physical address being subjected to
deallocation or free release by a controller is recognized.
Thus, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement firmware update and remapping of memory associated therewith in Rosner so that the NV memory controller/processor would be configured to perform a recovery rollback - as set forth in Tasher - where configuration of the rollback by the processor includes deallocating of unused resources or perform freeing of memory locations associated with the first resource after remapping the first logic address to the second physical address, the freeing based on logical resources that has not corresponding physical resource therefor - as in Barczak; because
freeing of previously allocated resources that are no longer logically bound with execution of
code under coordination of a memory mapper as in Tasher would increase the pool of reusable
memory while reducing size of physical resources to be monitored and managed by the system in
relation to continual control that check states of newly introduced resources and make adjusts to dynamic changes or logical reallocation of resources in non-volatile memory.
Claim 11 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner) in view of Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman) and Wu, Muh, USPN: 6,427,200 (herein Wu) and KR 101516580(translation), 05-11-2015, 19 pgs (herein '580), further in view of Liu, USPubN: 2022/0391280 (herein Liu) and Chow et al, USPubN: 2008/0250195 (herein Chow) and further of Talagata et al, USPubN: 2013/0332660 (herein Talagata)
As per claim 11, Rosner does not explicitly disclose system of claim 1, wherein the second resource is a duplicate of the first resource.
Talagata discloses management and extension of non-volatile memory/media for checkpointing purposes, including controller command to increment references to a same block via a
duplicate write (Fig. 3G) using an index that may reference duplicated data (para 0169) stored as different location of the media, where extension of the memory includes a module configure to map copies or clones of data/object, range or the like in response to mmap commands for the same data, the extension module by way of the clone functionality configured to update, merge or make changes or alterations to the copies etc. in response to a checkpoint trigger event (para 0107), the management of extended memory pages to support logical-to-physical (L2P) mapping and tracking whether the stored bits have been modified, referenced in predefined periods (para 0080); hence configuration of additional features to clone and duplicate stored data or updates thereof to accommodate checkpointing or L2P mapping is recognized.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective
filing date of the invention to implement Rosner's NV memory controller system SO that a stored
resource such as an updated version can be referenced by one index to more than one location(s) via a duplicate write command, or via a extension module that copies the stored resource into a clone
(duplicate version) at a different location of a non-volatile memory - as in Talagata; because
duplicate copy provided as multiple sectors referencing directed at a same data in a NV
memory storage per Rosner may mitigate exposure time required for unlocking a memory location to
permit a given operation by the controller over data at that location; whereas a clone established a
copy of the same data at a different location can boost parallel action of a validation scheme by a non-volatile memory controller, which in part can also reduce wait time imposed upon the systematic process to track or verify integrity of all addresses of identified sectors that would be required to validate data associated with the address mapping associated with SW update, checkpointing as set forth in Talagata, or data synchronization purposes.
Claims 12, 22-23 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner) in view of Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman) and Wu, Muh, USPN: 6,427,200 (herein Wu) and KR 101516580(translation), 05-11-2015, 19 pgs (herein '580), further in view of Liu, USPubN: 2022/0391280 (herein Liu) and Chow et al, USPubN: 2008/0250195 (herein Chow) and further of Seater et al, USPubN: 2020/0257517 (herein Seater)
As per claim 12, Rosner does not explicitly disclose system of claim 1, wherein the processor includes a reset input, wherein the processor is configured to reset responsive to an assertion of the reset input, and wherein the processor is configured to remap the first logical address to the second physical address and use the second resource while the reset input of the processor remains de-asserted.
Seater discloses firmware update in terms of a host device receiving a notification of a
firmware update based on which, an associated memory logic controller triggers a Reset via an
"Assert" signal to cause the host device to power-down and enable a subsequent power-up to reach a
stable level, upon which a de-assert Reset signal is provided by the logic controller to indicate that a
proper Reset and power up has been completed without fail, so that the device can execute thereafter
operations related to the updated firmware (para 0029)
Thus, it would have been obvious for one of ordinary skill in the art before the effective
filing date of the invention to implement processor controller upon a notification to update firmware
so that a reset input is invoked as part of sequence actions taken by the controller, according to
which, the processor is configured to reset responsive to an assertion of the reset input, and further
configured to invoke a mapper to remap the first logical address to the second physical address as
part of the update sequence that uses the second resource (update firmware) to replace a first
resource(firmware) while the reset input of the processor remains de-asserted - as shown in Seater
Reset assert followed with DEASSERT signal; because
reset assert followed immediately by a Reset De-assert represents a stable situation where a
current host is regenerated with sufficient power and stabilized state throughout all layers and
components associated with the system in line with a host intent of conducting operations or making
further manipulation on the state of data as well as protected blocks in non-volatile memory, since a
de-asserted Reset will be indicative the host system in a stable state for sustaining operations that
require sufficient energy to activate software and I/O transactions and can only be disrupted by
asynchronous events as unlikely as fault-induced interruption.
As per claim 22, Rosner discloses circuit of claim 32, wherein the processor includes a reset
input, wherein the processor is configured to reset responsive to an assertion of the reset input, and
wherein the processor is configured to remap the first logical address to the second physical address
while the reset input of the processor remains de-asserted.
(refer to rationale of claim 12)
As per claim 23, Rosner discloses circuit of claim 22, wherein the circuit further includes a reset input, and wherein the processor is configured to remap the first logical address to the second physical address while the reset input of the circuit remains de-asserted.
(refer to rationale of claim 12)
Claim 13 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner) in view of Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman) and Wu, Muh, USPN: 6,427,200 (herein Wu) and KR 101516580(translation), 05-11-2015, 19 pgs (herein '580), further in view of Liu, USPubN: 2022/0391280 (herein Liu) and Chow et al, USPubN: 2008/0250195 (herein Chow) and further of Zamir et al, USPubN: 2019/0164610 (herein Zamir)
As per claim 13, Rosner does not explicitly disclose system of claim 1, wherein the processor is configured to execute instructions based on a clock, and wherein the processor is configured to remap the first logic address to the second physical address within 1 clock cycle of the clock.
Zamir discloses initializing a logical to physical (L2P) map of logical address space (para 0033) according to a physical memory space which includes a first single-port and a second single- port memory being written with fresh data at respective single-port during the initial mapping period followed by subsequent writing of fresh data (Figure 16; para 0104) on a clock cycle to whichever of the first or second single-port memory is not busy with a read command during that clock cycle (para 0109). Hence, remapping associated with a logical to physical translation by a memory mapper so that each L2P operation during the initial mapping is directed to a respective port of physical emory space so that data being written thereto is within one cycle of clock is recognized.
Hence, as remapping a second resource (update version) per a L2P translation in Rosner requires initial write of said second resource into sectors of a corresponding NV memory (step 1564- 6, Fig. 15; step 1462-2, Fig. 14; para 0037) occupied by the current resource, prior to constructing pointer to the remap conversion (program new LA PA mapping 1462-4, Fig. 14; step 1564-8, Fig. 15), it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement time-based configuration for initializing a remapping as in Rosner so that
NV controller software thereof is configured to execute instructions based on a clock, to remap the
first logic address to the second physical address in which the second resource is to reside within 1 clock cycle of the clock according to initializing technique of mapping in Zamir; because
use of a mapping technique that relies on available and non-busy port of each target address space to map within each clock cycle would require low energy/bias for initializing each entry writing onto single port of a physical address space, the low bias of said write operation due to exploitation of non-busy port within each a clock cycle averting thereby pre-emptive contention by any ongoing operation (e.g. a new read or new write) that might block the intended write operation to a same physical address.
Claim 21 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner) in view of Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman) and Wu, Muh, USPN: 6,427,200 (herein Wu) and KR 101516580(translation), 05-11-2015, 19 pgs (herein '580), further in view of Liu, USPubN: 2022/0391280 (herein Liu) and Chow et al, USPubN: 2008/0250195 (herein Chow) and further of Tasher et al, TW I676116B, (translation) 11-01-2019, 20 pgs (herein Tasher) and Bohannon et al, USPubN: 2002/0091718 (herein Bohannon)
As per claim 21, Rosner does not explicitly disclose circuit of claim 20, wherein,
in response to a success of the authentication, integrity validation, or functional validation of the second resource, the processor is configured to change a rollback protection value.
Tasher discloses a package that includes a prevention against a verification failure in form of
a rollback check (receives a verification identifier a complete update "package" and subsequent
"rollback protection" - pg. 11); hence a protection status included with a rollback is recognized.
Bohannon discloses protected region of physical storage under checkpointing, preventive
precheck and recovery system provided with implementation of codeword Scheme (Fig. 3) associated with update of contents (e.g. images) in the database, where a flag under an applied codeword can be used to indicate a rollback between a begin and end point of a physical update (para 0096) which include possibility of an UNDO or REDO action (para 0098-0099, 0101), such that if modification of a region covered by a codeword results in no rollback where rollback is not occurring, the flag can be dispensed (para 0105); hence rollback protection in form of codeword flag being re-adjusted with discard of a flag in case of a update operation deemed successful is recognized.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement rollback protection - as per Tasher - with a update package in Rosner's NV memory system so that the NV memory control processor in response to a successful
state of the authentication, integrity, validation - as per Tasher - or functional validation of the second resource, is configured to change a rollback protection value - per a flag remove as set forth in Bohannon when there has been no occurrence of rollback happening; because
performing an authentication, an integrity validation, or a functional validation of the second
resource after remapping the first logical address to the second physical address coupled with roll- -
back flag setting as a form of programmatic means would enable a extra layer of precaution added to
the host system prior for the system to allow ultimate access to the set of physical memory space following a L2P redirection, such that in case of no-fault incurred as part of validating state of recently mapped to physical address, clearing a roll-back (by setting the flag to another value) as set
forth above would enable instant disarm the rollback mechanism, which in turn would obviate
extraneous resources or effort by the system to initiate recovery of a memory payload to its previous stable state along with the costly undoing of all existing memory references required as part of a physical and logical memory operational roll-back.
Response to Arguments
Applicant's arguments filed 9/30/26 have been fully considered but they are not persuasive. Following are the Examiner’s observations in regard thereto.
(A) The Applicant has submitted that the multiplexor cited in Venkatraman does not have a first physical address or second physical address passed to its output; nor does the control line selector in Venkatraman multiplexing (para 0030, 0059) to put out bad memory addresses show selected memory block from taking logical address in and passing out physical addresses (Applicant's Remarks -pg.8-9). First, the mapper circuits in Venkatraman convert inputted logical addresses and generate physical addresses (Fig. 3), where the chip select in Venkatraman with use of registers support passing of valid physical addresses after defective sectors have been mapped out, where each of the mappers translate logical addresses into physical addresses, which then are subjected to comparator logic so that only certain address bit can be selected and directed to the MUX. Clearly, arrangement of parallel mappers to provide physical addresses to a MUX circuit via intermediary of a sophisticated bit selection gate and attached register (of a reconfigurable memory map-out mechanism) is implemented to avoid outputting of bad physical addresses and contaminating a runtime. This arrangement shown in Venkatraman nevertheless teaches multiple L2P mappers aligned in parallel into this map-out circuitry to activate only certain physical address lines (see Venkatraman: para 0032-0034) to be passed through via a MUX into the CPU runtime. As well-understood in the art of using a MUX combined to address translation (L2P mapping) units, any output from one or more L2P mappers feeding into a CPU-controlled MUX necessarily undergoes some filtering and activation signaling so that no lines of data into a MUX input pass unattended or unchecked out to its output. The claim language (e.g. claim 1) makes it very vague about a control signal governing how physical addresses from a L2P mapper pass out through the multiplexor. At least, the map out mechanism in Venkatraman demonstrates usefulness of this filtering stage before physical addresses generated from L2P mappers can be allowed to be MUX-out into the runtime stream; and accusing this filtering stage in Venkatraman as not teaching direct passing of mapped physical addresses to output of a MUX would be deemed a clear refute to how a state of the art operates.
Moreover, the alleged questioning of Venkatraman in regard to “inputs to mux 906 carry two different physical addresses which are selectively passed through to the output of the mux based on a control signal” (Applicant's Remarks pg. 9) is found as having no relevance to the Office Action now provided to match the latest state of claim 1, in reference to the now-amended language describing “first and second mapper circuit coupled in parallel between the memory and the processor, a multiplexor coupled to output of the first mapper and output of the second mapper”. The alleged Ventrakaman’s deficiency, if any, appears to raise patentability merits of a newly recited language while analyzing the very grounds of rejection that prosecutes another claim language not even mentioned herein with the rebuttal. The argument about any failure of a reference to meet the new added language is deemed largely inconclusive.
The claim language currently submitted will stand rejected in view of the latest executed Office Action which has been necessitated by the amendment.
(B) The Applicant has submitted that rejection to claims 3-7, 19-20; 8, 11, 12, 22-23, 13, 21, 25-27 would have to be withdrawn because of the deficiency over Rosner among other references. (Applicant's Remarks pg. 9-11) for at least the above points of deficiencies. This allegation is deemed largely misplaced as set forth above.
In all, the claims submitted with this amendment will stand rejected.
Conclusion
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/Tuan A Vu/
Primary Examiner, Art Unit 2193
Octobre 10, 2026
