DETAILED ACTION
This action is responsive to the Applicant’s response filed 5/27/26.
As indicated in Applicant’s response, claims 1-9, 13, 16-24, 26 have been amended, claims14-15, 28-29 cancelled, and claims 30-31 added. Claims 1-13, 16-27, 30-31 are pending prosecution by a next office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites the limitation "IC" in lines 1 and 3. There is no sufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 9-10, 16-18, 30-31 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of KR 101516580 (translation), 05-11-2015, 19 pgs (herein ‘580), Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman), and Wu, Muh, USPN: 6,427,200(herein Wu)
As per claims 1 and 2, Rosner discloses a system, comprising:
memory including a first physical address space (locations are accessible via physical address (PA) – para 0028) that includes a first physical address (starting at Pax – para 0034; base physical address – para 0069) and a second physical address space that includes a second physical address (PA0, PA1 432 – Fig. 4; physical addresses starting at Pay – para 0037);
a memory mapper ( (LA[Wingdings font/0xE0]PA ) mapping – para 0029) coupled to the memory, the memory mapper configured to convert logical addresses to physical addresses (LA[Wingdings font/0xE0] PA mapping – para 0059; LA[Wingdings font/0xE0] PA mapping – para 0031; LA[Wingdings font/0xE0] PA mapping 1564-8; 1564-10 – Fig. 15); and
a processor coupled to the memory mapper (para 0059; para 0098), the processor configured to:
execute a first resource (address ranges which stores current firmware – para 0092; current firmware - para 0096; look-up structure 1564-16 – Fig. 15) using a first logical address mapped by the memory mapper to the first physical address (control circuit 112 translate logical addresses to physical addresses which start at Pax – para 0034; see data structure 110 …records a logical address to physical address mapping of firmware images … entry 110-0 stores LA_FW=PAx – para 0029); and
while executing a firmware update (receive new firmware (FW) image 1564-0, initiate program 1564-4 – Fig. 15) resource:
cause a second resource (new FW image into non-volatile sectors – para 0098) to be stored in the second physical address (e.g. NV sectors of the memory device at locations different from those that store a current FW image – 1564-6 – Fig. 15; steps 1564-8, 1564-10 – Fig. 15);
remap the first logical address to the second physical address (Fig. 4, can store LA[Wingdings font/0xE0]PA mapping data for each new firmware image – para 0049; LA->PA mapping for the newest firmware version – para 0053-0054) using the memory mapper (Note1: remap structure containing remapping information repointing the LA initially mapped to the PA of the current FW to the physical addresses of the new FW reads on remap the first logical address to the second physical address using the memory mapper);
execute the second resource (new firmware image 118 into a remap data structure – para 0038; remap 310 … enable access to a latest firmware image – para 0049) using the first logical address (e.g. use remap data structure 110 to determine which LA[Wingdings font/0xE0]PA mapping is valid and then use such a mapping to direct logical addresses to physical addresses of the valid firmware image – para 0031);
wherein the memory further includes the firmware update resource at a third physical address (in controller memory – para 0036; at memory device 1462-0 – Fig. 14; store …in system memory 1564-2 – Fig. 15)
Nor does Rosner explicitly disclose wherein the memory mapper comprises:
a first address mapper circuit coupled to the processor;
a second address mapper circuit coupled to the processor; and
a multiplexor having a first data input, a second data input, and an output, the first data input coupled to an output of the first address mapper circuit, and the second data input coupled to an output of the second address mapper circuit.
Similar to Rosner’s use NV memory to support update and related L[Wingdings font/0xE0]P memory address translation, ‘580 discloses non-volatile memory device as comprising non-volatile memory cells, EEPROM,, flash memory, etc. coupled to a solid state drive controller including itself plurality of address translation units, in form of address conversion CPUs, each of which receiving a plurality of channels included in the nonvolatile memory device (bottom pg. 5 to pg. 6) and use an address mapping table to contain all logical-physical address conversion to support plurality of address conversion CPUs whose processing can be performed in parallel per a single flash translation layer configured to solve potential bottleneck phenomenon, e.g. the ranges of channels controlled by the plurality of address conversion CPUs may not overlap each other (middle pg. 6), each address translation CPU performing a logical-to-physical address translation for at least one of the plurality of channels (pg. 4); where the simultaneous operation of the plurality of address translation CPUs or flash memory controllers of the nonvolatile memory device has a multi-channel parallel array structure enabling the address translation entities to perform in parallel (pg. 8) improving IOPS performance. Hence provision of a NV memory system with plurality of address translation units for mapping logical-to-physical memory address in a manner that the translation can be done without bottleneck or overlap issues is recognized.
Similar to ‘580 use plurality of units to perform address translation, Venkatraman discloses a plurality of memory mappers (mappers 802a…802n – Fig. 8) coupled in parallel to input of a multiplexer (para 0051), each mapper with outgoing pins whose lower bits are used to generate address for corresponding memory locations (para 0047), under selection by select chip (para 0050) which uses the upper bits from each respective mapper - in conjunction with a reconfigurable memory controller (para 0052-0055) per intermediary of bus keepers - to issue a MUX control signal as to which address bits being selected from a given mapper to be outputted onto the bus line (Fig. 9). Hence, first and second address mapper separately connected from their output to input lines of a multiplexer so that control signal by a controller selects which selected address bits from either first mapper or a second mapper to be released from the MUX is recognized.
Wu also discloses plural address bits being passed from pin outs of one or more address mappers to input of a multiplexer (Fig. 4) such that the output from the latter (e.g. address range) is enabled by a selector’s output control (priority encoder 34) – i.e. via a mask-based comparator processing the high-bits supplied from each address mapper (col.6, li. 58 to col. 7 li. 26), whereby, based on the signal bit from the selector 34, the multiplexer knows exactly the physical address of a pertinent mapper to output. Hence first and second address mapper connected at their output to lines into a multiplexer so that output from the MUX under control by a selector/encoder enable a selected address bits from either first mapper or a second mapper to be released from the MUX is recognized.
Therefore, based on the possibility of large scale address translation or multiple memory mappers forming a L[Wingdings font/0xE0]P address conversion workload into Rosner’s NV memory environment and associated burden for handling plurality of simultaneous channels of address translation with minimized bottleneck and channel overlap as set forth above in’580 , it would have been obvious for Tasone of ordinary skill in the art before the effective filing date of the invention to implement capability of perform logical-physical address translation in Rosner so that memory mapper entities associated with the NV memory environment would include:
at least two or more memory mapper units – as per the plurality of address translation processors in ‘580 – including at least a first address mapper circuit and a second address mapper circuit, both coupled to the processor; and
a multiplexor – as per Wu’s MUX system - having a first data input, a second data input, and an output - as illustrated in the setup by Venkatraman multiplexer output configuration -, in that the first data input coupled to an output of the first address mapper circuit, and the second data input coupled to an output of the second address mapper circuit; because
large scale of address conversion workflow associated with plural NV memory operations such as rewriting address ranges per a firmware replacement most often incur simultaneous and overwhelming demand for address conversions as set forth above ‘580, where plurality of incoming requests for L2P directed at a NV memory controller would risk to overflow capacity of the controller without use of accelerator implementation as well as parallelization of the address translation channels, and use of HW implemented with multiple memory mappers operating connected simultaneously into a multiplexed selector as set forth above would not only alleviate overlapping issue caused by size of request channels or solve any overflow effect on a NV controller capability; but would also equip the NV controller with a control capacity such that the controller would be able process data in/out between the concurrent mappers and the multiplexer, and decide, via issuing a proper selector signal which among translated address lines from mapper instances can be outputted from the multiplexor, the selective arrangement thereof imparting a level of synchronization that avert bottlenecks and undesirable request contention, improving throughput of the address translation demand for NV I/O operations as well as preserving the independency with which each memory (L2P) mapper operates in its own channel prior to their being subjected under a multiplexed data selector.
As per claim 9, Rosner discloses system of claim 1, wherein the first physical address corresponds to a first instruction of the first resource (current firmware - para 0096), and the second physical address corresponds to a first instruction of the second resource (new FW image into non-volatile sectors – para 0098).
As per claim 10, Tasher discloses system of claim 1, wherein a size of the first physical address space (current firmware image … stored in sectors “C” – para 0057) is different from a size of the second physical address space (new firmware image … stored in sectors “N” … understood to be different from and not overlap with sectors “C” – para 0059).
As per claim 16, Rosner discloses system of claim 1 wherein the processor is configured to
remap the first logical address to the second physical address by:
providing an address in the second physical address (starting at PAY that do not overlap with the physical addresses storing the current firmware - para 0037) to the memory mapper (Fig. 1B); and
asserting a swap signal (predetermined actions (e.g. Reset POR ….can access remap data structure – para 0032; step 1564-12, Fig. 15) to cause the memory mapper to select a conversion of the first logical address to the address in the second physical address space (step 1564-10, 1564-12, 1564-14, 1564-16, 1464-18 – Fig. 15) instead of a conversion of the first logical address to an address in the first physical address (firmware image at PAy becomes the current firmware image, to be accessed by the system – para 0039; controller 104[Wingdings font/0xE0]110-1 VAL. LA_FW = PAy – Fig. 1D).
As per claims 17-18, Rosner discloses a circuit (para 0030), comprising: a memory mapper configured to convert logical addresses to physical addresses (refer to claim 1); and
a processor coupled to the memory mapper, the processor configured to:
execute a first resource using a first logical address mapped by the memory mapper to a first physical address of a memory (refer to claim 1); and
while executing a firmware update resource (refer to claim 1):
remap the first logical address to a second physical address (refer to claim 1) of a second resource using the memory mapper; and
execute the second resource using the first logical address (refer to claim 1);
wherein the memory mapper comprises:
a first address mapper circuit coupled to the processor (refer to rationale of claim 1);
a second address mapper circuit coupled to the processor (refer to rationale of claim 1); and
a multiplexor (refer to rationale of claim 1) having a first data input, a second data input, a control input, and an output,
the first data input coupled to an output of the first address mapper circuit, the second data input coupled to an output of the second address mapper circuit, and the control input coupled to the processor. (refer to rationale A of claim 1)
wherein the circuit comprises memory coupled to the memory mapper (para 0059; para 0098).
As per claim 30, Rosner does not explicitly disclose system of claim 1:
wherein at least one input of the first address mapper circuit is configured to receive the first logical address from the processor, and the output of the first address mapping circuit is configured to provide the first physical address;
wherein at least one input of the second address mapper circuit is configured to receive the first logical address from the processor, and the output of the second address mapping circuit is configured to provide the second physical address; and
wherein the multiplexor includes a control input coupled to the processor,
wherein the multiplexor is configured to pass the first physical address provided by the first address
mapper circuit to the output of the multiplexor when a first state is provided to the control input; and the multiplexor is further configured to pass the second physical address provided by the second address mapper circuit to the output of the multiplexor when a second state is provided to the control input.
But based on the continuous and large scale demand of L2P requests flow into a NV controller – as illustrating in ‘580 method for parallelizing address translations - configuring a multiplexor to output lines of a first and second mapper unit set in parallel into the MUX circuitry so that the multiplexing effect would be able to output one or more physical address ranges supplied from a given L2P mapper, such that the multiplexer will dispatch a specific the physical address range received from output lines of either the first or the second mapper responsive to control of a select chip or signal by a processor (first or second select status) would be deemed an obvious configuration of parallel mappers into a multiplexing circuit - under control of a processor – as this has been set forth in rationale A in claim 1, using the teaching by Wu and Venkatraman, as set forth in claim 1.
Therefore, based on parallelization of L2P translation requests as set forth per the teachings by ‘580 , configuring parallel lines of logical addresses into first and second L2P mapper set in parallel into a multiplexor circuitry so that the multiplexor includes a control input coupled to the processor, and wherein the multiplexor is configured to a) either pass the first physical address provided by the first address mapper circuit to the output of the multiplexor when a first state is provided to the control input; or b) pass the second physical address provided by the second address mapper circuit to the output of the multiplexor when a second state is provided to the control input; and so for the same reasons set forth with rationale A of claim 1.
As per claim 31, Rosner discloses IC of claim 17: wherein at least one input of the first address mapper circuit is configured to receive the first logical address from the processor, and the output of the first address mapping circuit is configured to provide the first physical address;
wherein at least one input of the second address mapper circuit is configured to receive the first logical address from the processor, and the output of the second address mapping circuit is configured to provide the second physical address; and
wherein the control input of the multiplexor is coupled to the processor and configured to pass the first physical address provided by the first address mapper circuit to the output of the multiplexor when a first state is provided to the control input, and is further configured to pass the second physical address provided by the second address mapper circuit to the output of the multiplexor when a second state is provided to the control input.
( All of which having been addressed in claim 30)
Claims 3-7, 19-20 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of KR 101516580 (translation), 05-11-2015, 19 pgs (herein ‘580), Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman), and Wu, Muh, USPN: 6,427,200(herein Wu), further in view of Tasher et al, TW I676116B, (translation) 11-01-2019, 20 pgs (herein Tasher)
As per claims 3-4, Rosner does not explicitly disclose system of claim 1,
wherein the processor is configured to perform an authentication of the second resource before remapping the first logical address to the second physical address.
wherein the processor is configured to perform an integrity validation of the second resource before remapping the first logical address to the second physical address.
Rosner discloses a verification process in which FW version at address data pointed by a logical address (flash memory array having an address range designated for the new firmware – para 0092) is pre-checked to be proper or valid for use (e.g. control circuit can use the remap structure to determine with LA-PA mapping is valid – para 0031; para 0094) using a program to check the NV status to ensure that the latest FW targeted for a remapping is the correct FW version (step 1462-6 – Fig. 14; para 0094) in that as long that a invalid status persists (INV 110-1 – Fig. 1C) in the remap table structure, the mapping subsequent to that check will not be of effect (para 0038). Hence a validation of FW data stored at a physical location to be recorded in a remap table prior to commit a relevant remap entails a last check prior to commit a LA[Wingdings font/0xE0]PA entry into a remap table.
Tasher discloses performing an authentication of the second resource (signature of APP1, step 100, step 112, receives an updated version APP 1', security key KEYI calculate signature on APPI' and VERI ; VERI' VERI- pg. 13-14; top pg. 15) before remapping the first LA to a second PA and performing a integrity check (replaces the current version with the received version only after confirming the integrity and authenticity of the received version - pg. 12) of the second resource before the LA1[Wingdings font/0xE0] PA1 remapping.
Therefore, as software obtained via a network or download is typically subjected to security check or integrity verification before use (remap table look-up), it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement a controller associated with a firmware update and a remap setup in Rosner so that address information resulting from a remap (LA1[Wingdings font/0xE0]PA1) should first be subjected to a verification by the processor, including the latter
performing an authentication of the second resource – as set forth in Tasher - before remapping the first logical address to the second physical address.
performing an integrity validation of the second resource – as set forth in Tasher - before remapping the first logical address to the second physical address; because
authentication of a new download or acquired firmware targeted to provide functionality to a system as in Rosner that relies on software-based memory mapping prior to a remap, would ensure that the prospect software (firmware) is consistent with its identity, version called for by the acquisition so to avoid activation or incorporation of wrong product into core of the host functional system; and verifying the prospect software with integrity check prior to a remap would ensure that the software when activated for a runtime has retained all of its original content and characteristics in the course of transport/data writing into the memory sectors of the host system, thereby guaranteeing that no undesirable data tampering effects would demise short-term usability of the software or demise long term reliability of the system memory.
As per claim 5, Rosner discloses system of claim 1, wherein the processor is configured
to perform a functional validation of the second resource before remapping the first logical address to the second physical address. (refer to authentication and integrity check per rationale of claims 3-4)
As per claim 6 system of claim 5, wherein the processor is configured to:
before remapping the first logical address to the second physical address, execute a validation resource using a second logical address (e.g. flash memory array having an address range designated for the new firmware – para 0092) to perform the functional validation (see below) of the second resource at the second physical address; and
in response to a successful functional validation (e.g. INV 110-1 – Fig. 1C; mapping will not be of effect - para 0038) of the second resource (first status value to indicate that the logical address to physical address for the new firmware image is a valid firmware image – see Abstract; step 1462-6 – Fig. 14; para 0094), remap the first logical address to the second physical address.
As per claim 7, Rosner does not explicitly disclose system of claim 1, wherein the processor is configured to
remap the first logical address from the second physical address back to the first physical address in response to a fault during execution of the second resource.
Tasher discloses provision of “rollback” commands in configuring resources for recovery protection associated with a firmware update according to which logical-physical address mappings generated under a update “package” carried out by the NV memory controller are used to replace the stored data items with updated version of the data (“rollback protection” commands – pg. 11)
Hence, rollback in terms of reverting to a FW version by remapping a logical address back to the physical location in which a previous FW version is stored would have been obvious.
Thus, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement firmware update and remapping of memory associated therewith in Rosner so that the NV memory controller/processor would be configured to perform a recovery rollback – as set forth in Tasher – and remap the first logical address from the second physical address back to the first physical address – where a old/current version of FW is stored - in response to a fault – as in Tasher - during execution of the second resource; because
configuring a system with preventive measure to be able to instantly recover from a firmware update failure such as activating a rollback in which new firmware L2P mapping is logically remapped to address where old firmware is being stored would make the overall functioning of the system transparent with advent of the failure or errors incurred by the firmware update process, since only software-based remapping of physical address is being effected without enlisting of substantial amount of discrete resources from the HW processor, the OS and physical storage to go about keeping the normal flow of the system operation unaffected by a unsuccessful update to the system core firmware; that is, a incomplete process not accomplishing logical-to-physical translation of addresses by a memory remap underlying memory section rewrites as set forth above cannot be left in the state of improper logical-to-physical addresses conversion as this indirection effect can create dire runtime pointer crash at the lower level I/O or BIOS of the operating system, whereas a successful rollback that properly remaps software entity from its current logical memory address to its initial physical address would at least reset the system back to their restored known or seemingly status-quo state.
As per claim 19, Rosner discloses circuit of claim 17, wherein the processor is configured to perform an authentication, an integrity validation, or a functional validation of the second resource before remapping the first logical address to the second physical address.
(refer to rejection of claims 3-4)
As per claim 20, Rosner discloses circuit of claim 17, wherein the processor is configured to:
perform an authentication, an integrity validation, or a functional validation (para 0031) of the second resource after configuring the memory mapper to remap the first logical address to the second physical address(Note2: check a FW resource status in accordance with a mapping inside a remap structure – Fig. 1C - reads on performing a functional validation of a FW resource – new firmware image becomes valid, para 0040 - after configuring a remap structure indicative of a first LA pointing to a PA different from the initial PA at which a current FW is stored – see Fig. 1D);
while executing the firmware update resource (refer to claim 1), remap the first logical address back to the first physical address in response to a fault of the authentication, integrity validation, or functional validation of the second resource (refer to rationale of claim 7 using Tasher rollback); and execute the first resource using the first logical address (see remap per Fig .1C, 1D from above).
Claim 8 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of KR 101516580 (translation), 05-11-2015, 19 pgs (herein ‘580), Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman), and Wu, Muh, USPN: 6,427,200(herein Wu), further in view of Tasher et al, TW I676116B, (translation) 11-01-2019, 20 pgs (herein Tasher) and Barczak et al, USPubN: 2023/0139729 (herein Barczak)
As per claim 8, Rosner does not explicitly disclose system of claim 1, wherein the processor is configured to
cause freeing of memory locations associated with the first resource after remapping the first logic address to the second physical address
Barczak discloses translation layer associated with flash memory representing blocks
exposed for virtual machines implementation, the translation layer to map logical addresses of
virtual machines to physical addresses in the non-volatile memory (para 0034), the translation layer
equipped with formation of a mapping table that map logical address with actual clusters in the non-
volatile cache (para 0044) such that a check of a entry in the table indicative of a logical block
address being unrepresented by a cluster will have for effect to free (para 0043) the cluster from the
mapping followed with updating the table as part of managing free chunks (Fig. 6; Deallocate
clusters 704 - Fig. 7) in the non-volatile cache (para 0041); hence, memory resources unused in
accordance with mapping of logical addresses to their physical address being subjected to
deallocation or free release by a controller is recognized.
Thus, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement firmware update and remapping of memory associated therewith in Rosner so that the NV memory controller/processor would be configured to perform a recovery rollback – as set forth in Tasher – where configuration of the rollback by the processor includes deallocating of unused resources or perform freeing of memory locations associated with the first resource after remapping the first logic address to the second physical address, the freeing based on logical resources that has not corresponding physical resource therefor - as in Barczak; because
freeing of previously allocated resources that are no longer logically bound with execution of
code under coordination of a memory mapper as in Tasher would increase the pool of reusable
memory while reducing size of physical resources to be monitored and managed by the system in
relation to continual control that check states of newly introduced resources and make adjusts to
dynamic changes or logical reallocation of resources in non-volatile memory.
Claim 11 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of KR 101516580 (translation), 05-11-2015, 19 pgs (herein ‘580), Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman), and Wu, Muh, USPN: 6,427,200(herein Wu), further in view of Talagata et al, USPubN: 2013/0332660 (herein Talagata)
As per claim 11, Rosner does not explicitly disclose system of claim 1, wherein the second resource is a duplicate of the first resource.
Talagata discloses management and extension of non-volatile memory/media for checkpointing purposes, including controller command to increment references to a same block via a duplicate write (Fig. 3G) using an index that may reference duplicated data (para 0169) stored as different location of the media, where extension of the memory includes a module configure to map copies or clones of data/object, range or the like in response to mmap commands for the same data, the extension module by way of the clone functionality configured to update, merge or make changes or alterations to the copies etc. in response to a checkpoint trigger event (para 0107), the management of extended memory pages to support logical-to-physical (L2P) mapping and tracking whether the stored bits have been modified, referenced in predefined periods (para 0080); hence configuration of additional features to clone and duplicate stored data or updates thereof to accommodate checkpointing or L2P mapping is recognized.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement Rosner’s NV memory controller system so that a stored resource such as an updated version can be referenced by one index to more than one location(s) via a duplicate write command, or via a extension module that copies the stored resource into a clone (duplicate version) at a different location of a non-volatile memory - as in Talagata; because
duplicate copy provided as multiple sectors referencing directed at a same data in a NV memory storage per Rosner may mitigate exposure time required for unlocking a memory location to permit a given operation by the controller over data at that location; whereas a clone established a copy of the same data at a different location can boost parallel action of a validation scheme by a non-volatile memory controller, which in part can also reduce wait time imposed upon the systematic process to track or verify integrity of all addresses of identified sectors that would be required to validate data associated with the address mapping associated with SW update, checkpointing as set forth in Talagata, or data synchronization purposes.
Claims 12, 22-23 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of KR 101516580 (translation), 05-11-2015, 19 pgs (herein ‘580), Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman), and Wu, Muh, USPN: 6,427,200(herein Wu) further in view of Seater et al, USPubN: 2020/0257517 (herein Seater)
As per claim 12, Rosner does not explicitly disclose system of claim 1, wherein
the processor includes a reset input, wherein the processor is configured to reset responsive to an assertion of the reset input, and wherein the processor is configured to remap the first logical address to the second physical address and use the second resource while the reset input of the processor remains de-asserted.
Seater discloses firmware update in terms of a host device receiving a notification of a
firmware update based on which, an associated memory logic controller triggers a Reset via a Assert
signal to cause the host device to power-down and enable a subsequent power-up to reach a stable
level, upon which a de-assert Reset signal is provided by the logic controller to indicate that a proper
Reset and power up has been completed without fail, thereafter the device can execute operations
related to the updated firmware (para 0029)
Seater discloses firmware update in terms of a host device receiving a notification of a firmware update based on which, an associated memory logic controller triggers a Reset via an “Assert” signal to cause the host device to power-down and enable a subsequent power-up to reach a stable level, upon which a de-assert Reset signal is provided by the logic controller to indicate that a proper Reset and power up has been completed without fail, so that the device can execute thereafter operations related to the updated firmware (para 0029)
Thus, it would have been obvious for one of ordinary skill in the art before the effective
filing date of the invention to implement processor controller upon a notification to update firmware
so that a reset input is invoked as part of sequence actions taken by the controller, according to
which, the processor is configured to reset responsive to an assertion of the reset input, and further
configured to invoke a mapper to remap the first logical address to the second physical address as
part of the update sequence that uses the second resource (update firmware) to replace a first
resource(firmware) while the reset input of the processor remains de-asserted - as shown in Seater
Reset assert followed with DEASSERT signal; because
reset assert followed immediately by a Reset De-assert represents a stable situation where a
current host is regenerated with sufficient power and stabilized state throughout all layers and
components associated with the system in line with a host intent of conducting operations or making further manipulation on the state of data as well as protected blocks in non-volatile memory, since a de-asserted Reset will be indicative the host system in a stable state for sustaining operations that
require sufficient energy to activate software and I/O transactions and can only be disrupted by
asynchronous events as unlikely as fault-induced interruption.
As per claim 22, Rosner discloses circuit of claim 17, wherein the processor includes a reset input, wherein the processor is configured to reset responsive to an assertion of the reset input, and wherein the processor is configured to remap the first logical address to the second physical address while the reset input of the processor remains de-asserted.
(refer to rationale of claim 12)
As per claim 23, Rosner discloses circuit of claim 22, wherein the IC further includes a reset input, and wherein the processor is configured to remap the first logical address to the second physical address while the reset input of the IC remains de-asserted.
(refer to rationale of claim 12)
Claim 13 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of KR 101516580 (translation), 05-11-2015, 19 pgs (herein ‘580), Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman), and Wu, Muh, USPN: 6,427,200(herein Wu), further in view of Zamir et al, USPubN: 2019/0164610 (herein
Zamir)
As per claim 13, Rosner does not explicitly disclose s system of claim 1, wherein the processor is configured to execute instructions based on a clock, and wherein the processor is configured to remap the first logic address to the second physical address within 1 clock cycle of the clock.
Zamir discloses initializing a logical to physical (L2P) map of logical address space (para 0033) according to a physical memory space which includes a first single-port and a second single- port memory being written with fresh data at respective single-port during the initial mapping period followed by subsequent writing of fresh data (Figure 16; para 0104) on a clock cycle to whichever of the first or second single-port memory is not busy with a read command during that clock cycle (para 0109). Hence, remapping associated with a logical to physical translation by a memory mapper so that each L2P operation during the initial mapping is directed to a respective port of physical memory space so that data being written thereto is within one cycle of clock is recognized.
Hence, as remapping a second resource (update version) per a L2P translation in Rosner requires initial write of said second resource into sectors of a corresponding NV memory (step 1564-6, Fig. 15; step 1462-2, Fig. 14 ;para 0037) occupied by the current resource, prior to constructing pointer to the remap conversion (program new LA[Wingdings font/0xE0]PA mapping 1462-4, Fig. 14; step 1564-8, Fig. 15) , it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to implement time-based configuration for initializing a remapping as in Rosner so that NV controller software therefor is configured to execute instructions based on a clock, to remap the first logic address to the second physical address in which the second resource is to reside within 1 clock cycle of the clock according to initializing technique of mapping in Zamir; because
use of a mapping technique that relies on available and non-busy port of each target address
space to map within each clock cycle would require low energy/bias for initializing each entry
writing onto single port of a physical address space, the low bias of said write operation due to
exploitation of non-busy port within each a clock cycle averting thereby pre-emptive contention by any ongoing operation (e.g. a new read or new write) that might block the intended write operation on a same physical address.
Claim 21 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of KR 101516580 (translation), 05-11-2015, 19 pgs (herein ‘‘580), Venkatraman et al, USPubN: 2005/0146910 (herein Venkatraman), and Wu, Muh, USPN: 6,427,200(herein Wu), further in view of Tasher et al, TW 1676116, (translation), 11-01-2019, 20 pgs (herein Tasher) and Bohannon et al, USPubN: 2002/0091718 (herein Bohannon)
As per claim 21, Rosner does not explicitly disclose circuit of claim 20, wherein, in response to a success of the authentication, integrity validation, or functional validation of the second resource, the processor is configured to change a rollback protection value.
Tasher discloses a package that includes a prevention against a verification failure in form of a rollback check (receives a verification identifier a complete update "package" and subsequent "rollback protection" - pg. 11); hence a protection status included with a rollback is recognized.
Bohannon discloses protected region of physical storage under checkpointing, preventive precheck and recovery system provided with implementation of codeword Scheme (Fig. 3) associated with update of contents (e.g. images ) in the database, where a flag under an applied codeword can be used to indicate a rollback between a begin and end point of a physical update (para 0096) which include possibility of an UNDO or REDO action (para 0098-0099, 0101), such that if modification of a region covered by a codeword results in no rollback where rollback is not occurring, the flag can be dispensed (para 0105); hence rollback protection in form of codeword flag being re-adjusted with discard of a flag in case of a update operation deemed successful is recognized.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective
filing date of the invention to implement rollback protection- as per Tasher - with a update package in
Rosner’s NV memory system so that the NV memory control processor in response to a successful state of the authentication, integrity, validation – as per Tasher - or functional validation of the second resource, is configured to change a rollback protection value - per a flag remove as set forth in Bohannon when there has been no occurrence of rollback happening; because
performing an authentication, an integrity validation, or a functional validation of the second
resource after remapping the first logical address to the second physical address coupled with roll-
back flag setting as a form of programmatic means would enable a extra layer of precaution added to
the host system prior for the system to allow ultimate access to the set of physical memory space
following a L2P redirection, such that in case of no-fault incurred as part of validating state of
recently mapped to physical address, clearing a roll-back (by setting the flag to another value) as set
forth above would enable instant disarm the rollback mechanism, which in turn would obviate
extraneous resources or effort by the system to initiate recovery of a memory payload to its previous
stable state along with the costly undoing of all existing memory references required as part of a
physical and logical memory operational roll-back.
Claims 25-26 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of Tasher et al, TW I676116B, (translation) 11-01-2019, 20 pgs (herein Tasher)
As per claim 25, Rosner does not explicitly disclose method of claim 24, further executing, by the processor, a third resource that performs an authentication, an integrity validation, or a functional validation of the second resource before remapping the first logical address to the second physical address.
But use of a controller function as a third resource to authenticate and check integrity of firmware data prior to using remapped information has been addressed as obvious using the teaching by Tasher, per rationale of claims 3-4 from above.
Therefore, executing a third resource that performs an authentication, an integrity validation, or a functional validation of the second resource before remapping the first logical address to the second physical address in the context of NV memory address remap of Rosner would have been obvious for the same reasons set forth in the rationale of claims 3-4 from above.
As per claim 26, Rosner discloses method of claim 24, further comprising:
executing, by the processor, a third resource that performs an authentication, an integrity validation, or a functional validation (para 0031) of the second resource after remapping the first logical address to the second physical address (refer to Note2 of claim 20);
while executing the firmware update resource by the processor, remapping the first logical address back to the first physical address (refer to rationale of claim 7) in response to a fault of the authentication, integrity validation, or functional validation of the second resource; and
accessing, by the processor, the hardware peripheral from the first logical address (see remap after initiating a roll back protection per Tasher).
Claim 27 is/are rejected under § 35 U.S.C. 103 as being unpatentable over Rosner et al, USPubN: 2020/0301698 (herein Rosner), in view of Tasher et al, TW I676116B, (translation) 11-01-2019, 20 pgs (herein Tasher) further in view of Zamir et al, USPubN: 2019/0164610 (herein
Zamir)
As per claim 27, Rosner discloses method of claim 24, wherein remapping the first logic address to the second physical address occurs within 1 clock cycle of a clock of the processor.
(refer to rationale of claim 13)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rosner et al, USPubN: 2020/0301698 (herein Rosner).
As per claim 24, Rosner discloses a method, comprising:
accessing, by a processor, a hardware peripheral (memory array 108 – para 0028; array 108 – Figs 1) using a first logical address mapped to a first physical address of a memory (LA[Wingdings font/0xE0]PA mapping of firmware images – para 0029; array 108: (Current Image 114)Pax – Fig. 1A); and
while executing a firmware update resource (refer to claim 1) by the processor:
remapping the first logical address to a second physical address of the memory (refer to claim 1; para 0049; para 0053-0054); and
after the remapping of the first logical address to the second physical address executing, by the processor, a second resource (e.g. use remap data structure 110 to determine which LA[Wingdings font/0xE0]PA mapping is valid and then use such a mapping to direct logical addresses to physical addresses of the valid firmware image – para 0031) using the first logical address (Controller 104[Wingdings font/0xE0](INV: LA_FW=PAy; New Image 118: PAy - Fig. 1C).
Response to Arguments
Applicant's arguments filed 5/27/26 have been fully considered but they are not persuasive. Following are the Examiner’s observations in regard thereto.
(A) The Applicant has submitted that for claim 1 and claim 17, the structural features comprising a multiplexor connected to a first and second address mapper is not taught by any cited reference or combination thereof (Applicant's Remarks pg 9-10). The newly introduced feature has induced a new ground of rejection and use of different references; the above allegation is deemed non-commensurate with the latest state of prosecution, thus deemed largely inconclusive.
(B) The Applicant has submitted that Tasher, per claim 24, fails to teach “accessing” a “hardware peripheral” by a processor using a LA to PA mapping (Applicant's Remarks pg. 10-11). This newly introduced feature has induced a new ground of rejection and use of different references; the above allegation is deemed non-commensurate with the latest state of prosecution, thus deemed largely inconclusive.
( C) The Applicant has submitted that for the prosecuted state of claims 11, 12, 22-23, 13, 27, 21, 28-29, reconsideration and withdrawal of their respective rejection is requested (Applicant's Remarks pg. 12-13). The above request would be deemed moot with current state of prosecution effected to address the latest amended language of the independent claims and dependent claims.
In all, the claims submitted with this response will stand rejected as set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuan A Vu whose telephone number is (571) 272-3735. The examiner can normally be reached on 8AM-4:30PM/Mon-Fri.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Chat Do can be reached on (571)272-3721.
The fax phone number for the organization where this application or proceeding is assigned is (571) 273-3735 ( for non-official correspondence - please consult Examiner before using) or 571-273-8300 ( for official correspondence) or redirected to customer service at 571-272-3609.
Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 Group receptionist: 571-272-2100.
/Tuan A Vu/
Primary Examiner, Art Unit 2193
August 01, 2026
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