DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received October 13, 2025.
Response to Amendment
Applicant's submission filed on October 13, 2025 has been entered. Claims 18 and 21 have been canceled. Claims 22-23 have been added. Claims 1-16, 19-20 and 22-23 are pending in the current application. Claims 1-16, 19-20 and 22-23 are rejected herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh et al. (Hereinafter Osqueizadeh, U.S. Publication No. 2018/0349057) in view of Bolkhovitin et al. (Hereinafter Bolkhovitin, U.S. Publication No. 2018/0341606).
Regarding claim 1, Osqueizadeh teaches:
A storage system comprising:
a plurality of computational storage devices (See Figure 6, in which a first computational storage device corresponds to the configuration/connection of local memory 632.sub.1, dGPU 630.sub.1, NVMe 634.sub.1, and NVM 635.sub.1, as such configuration performs the same function as a computational storage device in the instant application. See Figure 6, in which a second computational storage device corresponds to the configuration/connection of local memory 632.sub.m, dGPU 630.sub.m, NVMe 634.sub.k, and NVM 635.sub.k, as such configuration performs the same function as a computational storage device in the instant application. Specifically, Figure 6 of the prior art corresponds to the teachings of Figure 5 of the instant application in view of the claimed language.); and
a host device configured to offload a program to one or more computational storage devices among the plurality of computational storage devices (See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components. In an implementation, embedded controller 610 can be implemented or emulated on a dedicated host CPU thread or offloaded to a dedicated embedded system or CPU, (e.g. a field-programmable gate array (FPGA)), without a change to the application visible functionality. Offloading can improve performance and system throughput.”),
wherein the plurality of computational storage devices comprises:
a first computational storage device configured (See Figure 6, in which a first computational storage device corresponds to the configuration/connection of local memory 632.sub.1, dGPU 630.sub.1, NVMe 634.sub.1, and NVM 635.sub.1, as such configuration performs the same function as a computational storage device in the instant application. For example, figure 6 of the prior art corresponds to the teachings of Figure 5 of the instant application in view of the claimed language.) to store first data used to execute the program (See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components.” The first computational storage device configuration of the prior art stores data related to the offloaded program.); and
a second computational storage device that comprises a second compute engine including a second accelerator (See Figure 6, in which a second computational storage device corresponds to the configuration/connection of local memory 632.sub.m, dGPU 630.sub.m, NVMe 634.sub.k, and NVM 635.sub.k, as such configuration performs the same function as a computational storage device in the instant application. See Figure 6, graphics processing unit dGPU 630.sub.m., which corresponds to the second accelerator. Specifically, Figure 6 of the prior art corresponds to the teachings of Figure 5 of the instant application in view of the claimed language.), the second computational storage device configured to:
store second data used to execute the program,
receive the offloaded program from the host device (See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components.” The second computational storage device configuration of the prior art stores data related to the offloaded program.),
Osqueizadeh does not explicitly disclose what Bolkhovitin teaches:
bring the first data from the first computational storage device into the second computational storage device (See [0118] “sends one or more subsequent commands, also using a command module (e.g., module 252-3), to the first storage device and/or the second storage device to perform a peer-to-peer transfer of the write data from the second controller memory buffer to the first controller memory buffer” See Figure 4I block 484. In the prior art, the claimed limitation corresponds to the prior art’s teaching of bringing the data from the second controller memory buffer to the first controller memory buffer. See Abstract, Figure 4H and Figure 4I, [0107] and [0117]-[0120] for full context of offloading data writes to multiple storage devices for data computation(s).), and
wherein the second compute engine of the second computational storage device is configured to execute the program using a plurality of data comprising the first data brought into the second computational storage device and the second data (See [0118] “sends one or more subsequent commands, also using a command module (e.g., module 252-3), to the first storage device and/or the second storage device to perform a peer-to-peer transfer of the write data from the second controller memory buffer to the first controller memory buffer and to perform a parity computation at the first storage device on the set of write data in the first controller memory buffer, as shown in 484” See [0119] “Two examples are provided for further illustration. In a first example, the one or more subsequent commands are a peer-to-peer transfer command to the second storage device to send the write data to the first storage device, and a parity computation command that is set to the first storage device after the peer-to-peer transfer is completed. In a second example, the one or more subsequent commands are combined transfer and parity computation command sent to the first storage device to pull in a copy of the write data from the second controller memory buffer and then to compute or update parity using the transferred copy of the write data.” See [0120] “Further, in some such embodiments, if any parity information has already been written to the memory block in the first storage device, it is updated with the write data in the first controller memory buffer. Also, in some embodiments, after sending the write and parity computation commands, the main controller subsystem receives one or more finished notifications from the first storage device and the second storage device” Parity computation is executed/updated on the first storage device by using write data (first data) brought from the second storage device and by using parity data (second data) that is already stored on the first storage device. See Abstract, Figure 4H and Figure 4I, [0107] and [0117]-[0120] for full context of offloading data writes to multiple storage devices for data computation(s).).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh with the data management function offload method of Bolkhovitin to improve the performance of non-volatile memory storage by offloading data management functions to one or more storage devices in a multi-device storage environment (See [0016] of Bolkhovitin).
Regarding claim 2, Osqueizadeh teaches:
The storage system of claim 1, wherein the first computational storage device comprises:
a first non-volatile memory device configured to store the first data(See Figure 6, Non-volatile memory NVM 635.sub.1.);
a memory space configured to store the first data transferred from the first non-volatile memory device (See Figure 6, local memory 632.sub.1. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].); and
a first compute engine (See Figure 6, graphics processing unit dGPU 630.sub.1.),
wherein the second computational storage device comprises:
a second non-volatile memory device configured to store the second data (See Figure 6, Non-volatile memory NVM 635.sub.k.);
a local memory configured to store the second data transferred from the second non-volatile memory device (See Figure 6, local memory 632.sub.m. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].), and configured to store the first data brought from the memory space(See [0045] “In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600” In a RAID storage array, data may be mirrored/copied between storge devices. For example, data may be mirrored/copied from NVMs 635.sub.1 to 635k, which can then be brought into local memory as depicted in Figure 1 and paragraph [0018].); and
the second compute engine, the second compute engine configured to execute the program …(See Figure 6, graphics processing unit dGPU 630.sub.m. See [0018] “Operationally, when a dGPU of the one or more dGPUs 130.sub.1 to 130m is executing commands that require data transfer between an associated local memory and one or more NVMs 135.sub.1 to 135.sub.k, then the processor 120 can instruct or enable direct data transfer from the associated local memory 132.sub.1 to 132m to one or more NVMs 135.sub.1 to 135k (arrow 142) or from one or more NVMs 135.sub.1 to 135k to the associated local memory (arrow 140).” See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system.”).
Osqueizadeh does not explicitly disclose what Bolkhovitin teaches:
the second compute engine, the second compute engine configured to execute the program (See Offload Services Module(s) 322-1 – 322-m depicted in Figure 3. See [0102] “With the support provided by their respective offload services modules 322, the SSDs 304 handle the offloaded operations in response to host commands, in accordance with some embodiments.”) using the plurality of data comprising the first data and the second data stored in the local memory (See [0118] “sends one or more subsequent commands, also using a command module (e.g., module 252-3), to the first storage device and/or the second storage device to perform a peer-to-peer transfer of the write data from the second controller memory buffer to the first controller memory buffer and to perform a parity computation at the first storage device on the set of write data in the first controller memory buffer, as shown in 484” See [0119] “Two examples are provided for further illustration. In a first example, the one or more subsequent commands are a peer-to-peer transfer command to the second storage device to send the write data to the first storage device, and a parity computation command that is set to the first storage device after the peer-to-peer transfer is completed. In a second example, the one or more subsequent commands are combined transfer and parity computation command sent to the first storage device to pull in a copy of the write data from the second controller memory buffer and then to compute or update parity using the transferred copy of the write data.” See [0120] “Further, in some such embodiments, if any parity information has already been written to the memory block in the first storage device, it is updated with the write data in the first controller memory buffer. Also, in some embodiments, after sending the write and parity computation commands, the main controller subsystem receives one or more finished notifications from the first storage device and the second storage device” Parity computation is executed/updated on the first storage device by using write data (first data) brought from the second storage device and by using parity data (second data) that is already stored on the first storage device. See Abstract, Figure 4H and Figure 4I, [0107] and [0117]-[0120] for full context of offloading data writes to multiple storage devices for data computation(s).).
Regarding claim 3, Osqueizadeh teaches:
The storage system of claim 2, wherein the first compute engine comprises a first accelerator (See graphics processing units (accelerators) dGPU 130.sub.1 depicted in Figure 1. See graphics processing units (accelerators) dGPU 430.sub.1 depicted in Figure 4. See [0046] “accelerators like dGPU 630.sub.1 to 630m”), and
wherein the second compute engine is further configured to store an execution result of the program in the local memory (See Figure 6, graphics processing unit dGPU 630.sub.m. See [0018] “Operationally, when a dGPU of the one or more dGPUs 130.sub.1 to 130m is executing commands that require data transfer between an associated local memory and one or more NVMs 135.sub.1 to 135.sub.k, then the processor 120 can instruct or enable direct data transfer from the associated local memory 132.sub.1 to 132m to one or more NVMs 135.sub.1 to 135k (arrow 142) or from one or more NVMs 135.sub.1 to 135k to the associated local memory (arrow 140).”).
Regarding claim 4, Osqueizadeh teaches:
The storage system of claim 2, wherein the memory space is a space accessible by the second computational storage device without intervention of the host device (See [0015] “the method describes transferring data directly between the NVM and the local memory, which bypasses interaction with a system memory of a processor and a host system root complex.” See [0045] “In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600” In a RAID storage array, data may be mirrored/copied between storge devices. For example, data may be mirrored/copied from NVMs 635.sub.1 to 635k. , which can then be brought into local memory as depicted in Figure 1 and paragraph [0018].), and
wherein the second computational storage device is configured to bring the first data from the memory space of the first computational storage device into the local memory of the second computational storage device without intervention of the host device (See [0015] “the method describes transferring data directly between the NVM and the local memory, which bypasses interaction with a system memory of a processor and a host system root complex.” See [0024] “Data is then transferred directly from the first memory architecture to the second memory architecture associated with the GPU using a local switch and bypassing a host processor switch.” See [0024] “Data is then transferred from the second memory architecture to the first memory architecture associated with the GPU using the local switch and bypassing the host processor switch.”).
Regarding claim 6, Osqueizadeh teaches:
The storage system of claim 2, wherein the first computational storage device further comprises a second local memory (See Figure 1, Figure 4 and Figure 6, which depict a plurality of local memories.), and
wherein the host device is further configured to set the memory space in the second local memory such that the memory space is provided as defined memory within the second local memory (See Figure 6, local memory 632.sub.1.), and
Osqueizadeh does not explicitly disclose what Bolkhovitin teaches:
transmit a command including location information of the memory space to the first computational storage device (See [0056] “In some embodiments, a read operation is initiated when a host 101 sends a host read command (e.g., in a set of one or more host read commands), to main controller 110, which translates the received host read command into a read command (e.g., into a lower level data storage device command, sometimes herein called a translated command or translated read command, suitable for execution by a data storage device 120) and sends the translated read command to the storage controller 124 of a respective data storage device 120 (FIG. 1B), requesting data from that data storage device's storage medium (e.g., one or more NVM devices 140). Storage controller 124 sends one or more read access commands to NVM devices 140, via storage medium interface 128 (e.g., through NVM controllers 130), in accordance with memory locations (addresses) specified by the host read command. Storage medium interface 128 provides the raw read data (e.g., comprising one or more codewords) to decoder 327. The read access commands correspond to the received read command, but the read command is converted by storage controller 124 into read access commands, for example so as to be directed to one or more specific NVM device 140.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh with the data management function offload method of Bolkhovitin to improve the performance of non-volatile memory storage by offloading data management functions to one or more storage devices in a multi-device storage environment (See [0016] of Bolkhovitin).
Regarding claim 7, Osqueizadeh teaches:
The storage system of claim 2, wherein the host device is further configured to send a first command to the first computational storage device, and send a second command to the second computational storage device (See Figure 1, Figure 4 and Figure 6, in which the host sends commands to the storage device(s). See [0043] “Each NVM controller 634.sub.1 to 634k can manage and access an associated NVM 635.sub.1 to 635k and in particular, can decode incoming commands from host computing system 405 or dGPU 630.sub.1 to 630.sub.m.”),
wherein the first computational storage device further comprises a first storage controller (See Figure 6, Non-volatile memory controller NVMe 634.sub.1.) configured to receive the first command (See [0043] “Each NVM controller 634.sub.1 to 634k can manage and access an associated NVM 635.sub.1 to 635k and in particular, can decode incoming commands from host computing system 405 or dGPU 630.sub.1 to 630.sub.m.”) and transfer the first data from the first non-volatile memory device to the memory space in response to the first command (See Figure 6, local memory 632.sub.1 and non-volatile memory 635.sub.1. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].),
wherein the second computational storage device further comprises a second storage controller (See Figure 6, Non-volatile memory controller NVMe 634.sub.k.) configured to receive the second command (See [0043] “Each NVM controller 634.sub.1 to 634k can manage and access an associated NVM 635.sub.1 to 635k and in particular, can decode incoming commands from host computing system 405 or dGPU 630.sub.1 to 630.sub.m.”) and transfer the second data from the second non-volatile memory device to the local memory in response to the second command (See Figure 6, local memory 632.sub.m and non-volatile memory 635.sub.k. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].), and
wherein at least one of the first command or the second command comprises a data read command (See [0038] “whether host processor 420 or one of dGPU 430.sub.1 to 430m sent the access request or data transfer command.” See [0047] “the packet commands can be issued by GPU kernels, host processing system or via service drivers as remote storage.” See
[0048] “the packet commands can be used to issue reads and writes referenced via handles to storage spaces/files.” See [0043] “Each NVM controller 634.sub.1 to 634k can manage and access an associated NVM 635.sub.1 to 635k and in particular, can decode incoming commands from host computing system 405 or dGPU 630.sub.1 to 630.sub.m.”).
Regarding claim 22, Osqueizadeh teaches:
The storage system of claim 1, wherein the second computational storage device is a separate semiconductor device from the first computational storage device (See [0016] “The processing system 100 can include a host computing system 105 that is connected to one or more solid state graphics (SSG) boards or cards 110.sub.1 to 110.sub.n.” See Figure 1 and Figure 4, which depict multiple SSG boards that can comprise a first and second computational storage device. See claim 10 of Osqueizadeh, which also teaches multiple SSG boards.).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Choe et al. (Hereinafter Choe, U.S. Publication No. 2022/0100669).
Regarding claim 5, Choe teaches:
The storage system of claim 4, wherein the second computational storage device is configured to access the memory space based on a computer express link (CXL) protocol (See CXL link protocol depicted in Figure 1 and Figures 7-11. See [0002] “The present disclosure relates to a storage device, and more particularly, to a storage device using a Computer eXpress Link (CXL) interface.” See [0005] “A smart storage device includes a smart interface connected to a host device, an accelerator circuit connected to the smart interface through a data bus conforming to compute express link (CXL).cache protocol and a CXL.mem protocol, and configured to perform acceleration computation in response to a computation command of the host device and a storage controller connected to the smart interface through a data bus conforming to CXL.io protocol and configured to control a data access operation for a storage device in response to a data access command of the host device.” See [0027] “The smart interface 100 is configured to utilize CXL sub-protocols such as CXL.io, CXL.cache, and CXL.mem. The CXL.io protocol is a PCIe transaction layer, which is used in the system for device discovery, interrupt management, providing access by registers, initialization processing, signal error processing, or the like. The CXL.cache protocol may be used when the accelerator circuit 200 accesses the host memory 12 of the host device. The CXL.mem protocol may be used when the host device 10 accesses an accelerator memory 290 of the accelerator circuit 200 (see FIG. 2) or the memory device 490 connected to the memory controller 400 (see FIG. 7).”), and
wherein the second computational storage device is further configured to provide an execution result of the program to the host device (See steps S33 and S34 of Figure 6, in which the results of a data operation are sent to the host.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the communications protocol of Choe to reduce the overhead and waiting time of the host device and the storage device and allow the storage space of the host memory and the memory device to be shared in a heterogeneous computing environment in which a host device storage device operate together (See [0025] of Choe.). Furthermore, the combination would permit the storage devices to access memory spaces based on the known CXL protocol standard (See [0027] of Choe.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Deng et al. (Hereinafter Deng, U.S. Publication No. 2023/0229629).
Regarding claim 10, Deng teaches:
The storage system of claim 1, wherein the host device is further configured to select, as the second computational storage device, a computational storage device that stores a greatest amount of data used for execution of the program from among the plurality of computational storage devices (See [0038] “The primary computing node 106A selects a candidate computing node 106 to execute the data storage plan based on which of the data storage files 202 of the data shard 102 that are subject to the data storage plan each candidate computing node 106 locally caches (320). In one implementation, the candidate computing node 106 locally caching the greatest number of the data storage files 202 is selected to execute the data storage plan. In another implementation, the candidate computing node 106 locally caching the largest size of the data storage files is selected to execute the data storage plan.” See claims 6-8 of Deng.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the computing node selection method of Deng to reduce the time needed to process/execute application and/or program data.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Xing et al. (Hereinafter Xing, U.S. Publication No. 2023/0367648) in view of Parikh et al. (Hereinafter Parikh, U.S. Publication No. 2024/0012668 ).
Regarding claim 11, Osqueizadeh teaches:
The storage system of claim 1, wherein each of the plurality of computational storage devices comprises an accelerator (See graphics processing units (accelerators) dGPU 130.sub.1 and dGPU 130.sub.m depicted in Figure 1. See graphics processing units (accelerators) dGPU 430.sub.1 and dGPU 430.sub.m depicted in Figure 4. See [0046] “accelerators like dGPU 630.sub.1 to 630m”), and
Osqueizadeh does not explicitly disclose what Xing teaches:
wherein the host device is further configured to select, as the second computational storage device, a computational storage device comprising the accelerator having an idle state from among the plurality of computational storage devices (See [0072] “When selecting an edge device to which an accelerator is connected as the second edge device, the control server can select an edge device randomly or according to the occupation of the accelerators. Specifically, the control server can further maintain the occupation of different accelerators, wherein a daemon monitors the occupation of the accelerator connected to an edge device on which the daemon is installed, for example, the utilization of the accelerator, and sends the occupation to the control server, and the control server records the occupation. When selecting a second edge device, the control server can select an edge device to which an idle accelerator is connected as the second edge device. Since the accelerator on the second edge device is in an idle state, the accelerator can provide more computing resources for a target application and the accelerator can execute the target application more quickly.”), and
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the edge device selection method of Xing to provide an accelerator that has more computing resources for a target application and therefore can execute the target application more quickly, thus providing optimal selection of an edge device and accelerator to perform a specific task (See [0072] of Xing.).
Osqueizadeh and Xing do not explicitly disclose what Parikh teaches:
wherein the host device is further configured to query each of the plurality of computational storage devices for a state of the accelerator, and receive the state of the accelerator from each of the plurality of computational storage devices (See [0057] “For example, in certain aspects, agent 152 checks system information via an operating system (OS) of host 102 to determine information (e.g., models, versions, etc.) about hardware installed on host 102 and/or resource (CPU, memory, etc.) availability and usage on host 102. Agent 152 may use this information to determine whether hardware installed on host 102 and/or resources available on hosts 102 are compatible and/or allow for VSAN 122 and/or VSAN Max 124 deployment.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin and the edge device selection method of Xing with the hardware checking method of Parikh to ensure hardware compatibility prior to data store deployment.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Goldsack et al. (Hereinafter Goldsack, U.S. Publication No. 2018/0225150) in view of Parikh.
Regarding claim 12, Osqueizadeh teaches:
The storage system of claim 1, wherein each of the plurality of computational storage devices comprises an accelerator (See graphics processing units (accelerators) dGPU 130.sub.1 and dGPU 130.sub.m depicted in Figure 1. See graphics processing units (accelerators) dGPU 430.sub.1 and dGPU 430.sub.m depicted in Figure 4. See [0046] “accelerators like dGPU 630.sub.1 to 630m”), and
Osqueizadeh does not explicitly disclose what Goldsack teaches:
wherein the host device is further configured to select, as the second computational storage device, a computational storage device comprising the accelerator having a lowest utilization from among the plurality of computational storage devices (See [0029] “In some examples the instruction set is arranged such that selecting one of the first processing unit and the second processing unit comprises selecting a processing unit having a predefined affinity above a predefined minimum affinity threshold and a lowest current resource utilisation to perform the computation.”), and
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the storage selection method of Goldsack to ensure that the resources of the computing device are used efficiently. Such combination can ensure that the resources of the computing device are used as efficiently as possible to achieve a particular overall system goal, such as minimizing time to complete, or minimizing energy consumption. (See [0029] of Goldsack.).
Osqueizadeh and Goldsack do not explicitly disclose what Parikh teaches:
wherein the host device is further configured to query each of the plurality of computational storage devices for a utilization of the accelerator, and receive the utilization of the accelerator from each of the plurality of computational storage devices (See [0057] “For example, in certain aspects, agent 152 checks system information via an operating system (OS) of host 102 to determine information (e.g., models, versions, etc.) about hardware installed on host 102 and/or resource (CPU, memory, etc.) availability and usage on host 102. Agent 152 may use this information to determine whether hardware installed on host 102 and/or resources available on hosts 102 are compatible and/or allow for VSAN 122 and/or VSAN Max 124 deployment.”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin and the storage selection method of Goldsack with the hardware checking method of Parikh to ensure hardware compatibility prior to data store deployment.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Moshe et al. (Hereinafter Moshe, U.S. Publication No. 2022/0164299)
Regarding claim 13, Moshe teaches:
The storage system of claim 1, wherein the host device is further configured to perform authentication on the first computational storage device and the second computational storage device (See [0013] “The computer-implemented method may include: determining the first set of access parameters for the first storage device; authenticating, by a host system including the plurality of host memory buffers, the first set of access parameters for storage device access to the first host resource; determining the second set of access parameters for the second storage device; and authenticating, by the host system, the second set of access parameters for storage device access to the second host resource.” See [0092] “At block 712, the storage device may authenticate to the host as itself. For example, during normal operation a host access service of the storage device may use the access parameters assigned to the storage device and provide those access parameters to the host in order to be authenticated by the host for access one or more host resources over the storage interface.” See [0096]. See [0104]. See block 818 of Figure 8.), and
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the host sharing method of Moshe to determine whether a storage device has permission to gain access to the host, which would improve overall security measures when determining valid access parameters of a storage device (See [0041] of Moshe.).
Moshe does not explicitly disclose what Osqueizadeh teaches:
wherein the host device is configured to offload the program to at least one compute namespace of the one or more computational storage devices (See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components. In an implementation, embedded controller 610 can be implemented or emulated on a dedicated host CPU thread or offloaded to a dedicated embedded system or CPU, (e.g. a field-programmable gate array (FPGA)), without a change to the application visible functionality. Offloading can improve performance and system throughput.”).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Kim et al. (U.S. Patent No. 10,310,662).
Regarding claim 14, Kim et al. teaches:
The storage system of claim 1, wherein the first computational storage device and the second computational storage device are further configured to perform authentication between the first computational storage device and the second computational storage device, and wherein the second computational storage device is configured to act as a master computational storage device that authenticates the first computational storage device (See Claim 16 of Kim et al. “A second device comprising: a wireless communication unit configured to perform a communication connection between a second device and a first device, wherein an authentication procedure is performed between the first device and the second device based on a device-specific ID and based on the communication connection being made between the first device and the second device,” See Col. 31 line 65 – Col. 32 lines 8 “Also, when the communication connection is made between the first mobile terminal 400 and the second mobile terminal 500, an authentication procedure (e.g., using a terminal-specific ID, a phone number, or IP information) may be performed between the terminals.” See Col. 32, lines 6-8 “the first mobile terminal 400 transmits location data of the first mobile terminal (or the vehicle) to the second mobile terminal 500.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the communication method of Kim et al. to determine whether a storage device has permission to gain access to another storage device, which would improve overall security measures when determining access parameters/permissions of a storage device.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Shim in view of Seppanen (U.S. Publication No. 2017/0003896).
Regarding claim 8, Shim teaches:
wherein the first computational storage device is further configured to, when transfer of the first data to the memory space is complete, send a second message to the second computational storage device in response to the first message, the second message indicating that the first data are ready in the memory space (See Figure 2B of Shim, in which first, second and third storage information are sent to indicate that data storage has completed.),
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the data transfer method of Shim to ensure that all transmitted data is received prior to trying to access it, thus avoiding redundant access commands and improving I/O management.
Shim does not explicitly disclose what Seppanen teaches:
The storage system of claim 7, wherein the second computational storage device is further configured to send to the first computational storage device a first message querying whether the first data are ready in the memory space (See [0024] “Retrieving the control information from the storage device (146, 150) may be carried out, for example, by the storage array controller (106, 112) querying the storage device (146, 150) for the location of control information for the storage device.” Such limitation is taught in the prior art’s teaching of a storage controller querying a storage device for control information, as the storage controller is querying the storage device to retrieve the control information from the storage device.),
wherein the second computational storage device is further configured to bring the first data from the memory space into the local memory in response to the second message (See [0024] “The storage device (146, 150) may subsequently send a response message to the storage array controller (106, 112) that includes the location of control information for the storage device (146, 150). As such, the storage array controller (106, 112) may subsequently issue a request to read data stored at the address associated with the location of control information for the storage device (146, 150).”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the offloading data transfer communication method of Seppanen to improve I/O management when transferring data between multiple devices by improving communications (i.e. implementing response/acknowledgement messages) between devices.
Regarding claim 9, Shim teaches:
The storage system of claim 7, wherein the first computational storage device is further configured to send a message to the second computational storage device when transfer of the first data to the memory space is complete (See Figure 2B of Shim, in which first, second and third storage information are sent to indicate that data storage has completed.), and
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the data transfer method of Shim to ensure that all transmitted data is received prior to trying to access it, thus avoiding redundant access commands and improving I/O management.
Shim does not explicitly disclose what Seppanen teaches:
wherein the second computational storage device is further configured to bring the first data from the memory space into the local memory in response to the message (See [0024] “The storage device (146, 150) may subsequently send a response message to the storage array controller (106, 112) that includes the location of control information for the storage device (146, 150). As such, the storage array controller (106, 112) may subsequently issue a request to read data stored at the address associated with the location of control information for the storage device (146, 150).”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the offloading data transfer communication method of Seppanen to improve I/O management when transferring data between multiple devices by improving communications (i.e. implementing response/acknowledgement messages) between devices.
Claims 15-16, 19 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Kachare et al. (Hereinafter Kachare, U.S. Publication No. 2021/0281639).
Regarding claim 15, Osqueizadeh teaches:
A computational storage device comprising:
a non-volatile memory device configured to store first data (See Figure 6, Non-volatile memory NVM 635.sub.1.) used in execution of a first program offloaded from a host device (See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components. In an implementation, embedded controller 610 can be implemented or emulated on a dedicated host CPU thread or offloaded to a dedicated embedded system or CPU, (e.g. a field-programmable gate array (FPGA)), without a change to the application visible functionality. Offloading can improve performance and system throughput.”);
a local memory configured to store the first data transferred from the non-volatile memory device (See Figure 6, local memory 632.sub.1. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].), and store second data that are used in execution of the first program and transferred from another computational storage device (See Figure 6, local memory 632.sub.1. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].); and
a compute engine including an accelerator (See graphics processing units (accelerators) dGPU 130.sub.1 depicted in Figure 1. See graphics processing units (accelerators) dGPU 430.sub.1 depicted in Figure 4. See [0046] “accelerators like dGPU 630.sub.1 to 630m”).) configured to execute the first program offloaded from the host…(See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components. In an implementation, embedded controller 610 can be implemented or emulated on a dedicated host CPU thread or offloaded to a dedicated embedded system or CPU, (e.g. a field-programmable gate array (FPGA)), without a change to the application visible functionality. Offloading can improve performance and system throughput.”)
…transfer the first data from the non-volatile memory device to the local memory (See Figure 6, local memory 632.sub.1. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].),
Osqueizadeh does not explicitly disclose what Bolkhovitin teaches:
a compute engine… configured to execute the first program offloaded from the host device (See Offload Services Module(s) 322-1 – 322-m depicted in Figure 3. See [0102] “With the support provided by their respective offload services modules 322, the SSDs 304 handle the offloaded operations in response to host commands, in accordance with some embodiments.”) using a plurality of data comprising the first data and the second data …(See [0118] “sends one or more subsequent commands, also using a command module (e.g., module 252-3), to the first storage device and/or the second storage device to perform a peer-to-peer transfer of the write data from the second controller memory buffer to the first controller memory buffer and to perform a parity computation at the first storage device on the set of write data in the first controller memory buffer, as shown in 484” See [0119] “Two examples are provided for further illustration. In a first example, the one or more subsequent commands are a peer-to-peer transfer command to the second storage device to send the write data to the first storage device, and a parity computation command that is set to the first storage device after the peer-to-peer transfer is completed. In a second example, the one or more subsequent commands are combined transfer and parity computation command sent to the first storage device to pull in a copy of the write data from the second controller memory buffer and then to compute or update parity using the transferred copy of the write data.” See [0120] “Further, in some such embodiments, if any parity information has already been written to the memory block in the first storage device, it is updated with the write data in the first controller memory buffer. Also, in some embodiments, after sending the write and parity computation commands, the main controller subsystem receives one or more finished notifications from the first storage device and the second storage device” Parity computation is executed/updated on the first storage device by using write data (first data) brought from the second storage device and by using parity data (second data) that is already stored on the first storage device. See Abstract, Figure 4H and Figure 4I, [0107] and [0117]-[0120] for full context of offloading data writes to multiple storage devices for data computation(s).),
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh with the data management function offload method of Bolkhovitin to improve the performance of non-volatile memory storage by offloading data management functions to one or more storage devices in a multi-device storage environment (See [0016] of Bolkhovitin). Furthermore, while the combination of Osqueizadeh and Bolkhovitin do teach a storage controller to transfer the first data from the non-volatile memory device to the local memory, and transfer the second data from a shared memory space of the another computational storage device to the local memory, neither Osqueizadeh nor Bolkhovitin teach the transfer to be done by the compute engine. It would have been obvious to try implementing the claimed limitations in a compute engine, choosing from a finite number of identified, predictable structures, with a reasonable expectation of success.
Osqueizadeh and Bolkhovitin do not explicitly disclose what Kachare teaches:
and transfer the second data from a shared memory space of the another computational storage device to the local memory (See [0046] “In some embodiments, one or more storage devices may use peer-to-peer data transfers to implement computational storage and/or otherwise offload computation and/or bandwidth loads from one or more hosts and/or host interfaces. For example, in some embodiments, one or more storage devices in a group or subgroup of devices having a peer-to-peer channel configured between them may be designated to perform data compression, encryption, and/or the like for the other storage devices in the group, subgroup, storage system, and/or the like. As another example, in some embodiments, one or more storage devices may use peer-to-peer channels to transfer intermediate calculation results between devices for further calculations without having to send and/or receive the intermediate results to and/or from a host.”), wherein the shared memory space and the local memory each comprise volatile memory (While the prior art does not explicitly disclose the shared memory and local memory to comprise volatile memory, memory can either be volatile or non-volatile. Therefore, it would have obvious to try, choosing from a finite number of identified, predictable memory technology types (i.e. such as non-volatile and volatile memory), with a reasonable expectation of success. That is, memory can be either volatile or non-volatile, with one of ordinary skilled in the art choosing between the two based on the limitations and advantages/disadvantages between the two memory technologies.);
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the offload method of Kachare to transfer intermediate calculation results between devices for further calculations without having to send and/or receive the intermediate results to and/or from a host, thus enabling faster access/use of the calculated data.
Regarding claim 16, Osqueizadeh and Bolkhovitin teaches:
The computational storage device of claim 15,
wherein the compute engine is further configured to execute the first program in response to a program execution command transmitted by the host device (Claim 16 is rejected for the same reasons as claim 2, claim 7 and claim 15.), and
Osqueizadeh and Bolkhovitin do not explicitly disclose what Kachare teaches:
wherein the compute engine is further configured to directly transfer the second data from the shared memory space of the another computational storage device to the local memory of the computational storage device (See [0046] “In some embodiments, one or more storage devices may use peer-to-peer data transfers to implement computational storage and/or otherwise offload computation and/or bandwidth loads from one or more hosts and/or host interfaces. For example, in some embodiments, one or more storage devices in a group or subgroup of devices having a peer-to-peer channel configured between them may be designated to perform data compression, encryption, and/or the like for the other storage devices in the group, subgroup, storage system, and/or the like. As another example, in some embodiments, one or more storage devices may use peer-to-peer channels to transfer intermediate calculation results between devices for further calculations without having to send and/or receive the intermediate results to and/or from a host.”);
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the offload method of Kachare to transfer intermediate calculation results between devices for further calculations without having to send and/or receive the intermediate results to and/or from a host, thus enabling faster access/use of the calculated data.
Regarding claim 19, Osqueizadeh teaches:
A method of operating a storage system comprising a plurality of computational storage devices and a host device, the plurality of computational storage devices comprising a first computational storage device and a second computational storage device, the method comprising:
offloading a program from the host device to the first computational storage device (See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components. In an implementation, embedded controller 610 can be implemented or emulated on a dedicated host CPU thread or offloaded to a dedicated embedded system or CPU, (e.g. a field-programmable gate array (FPGA)), without a change to the application visible functionality. Offloading can improve performance and system throughput.”);
transferring first data from a first non-volatile memory device of the first computational storage device to a local memory of the first computational storage device in response to a first command from the host device (See Figure 6, local memory 632.sub.1. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].);
transferring second data from a second non-volatile memory device of the second computational storage device to a shared memory space of the second computational storage device in response to a second command from the host device (See Figure 6, local memory 632.sub.m. See Figure 1 in which element 142 depicts data transfer from local memory to non-volatile memory, and element 140 depicts data transfer from non-volatile memory to local memory, as supported in paragraph [0018].);
a compute engine including an accelerator of the first computational storage device (See graphics processing units (accelerators) dGPU 130.sub.1 depicted in Figure 1. See graphics processing units (accelerators) dGPU 430.sub.1 depicted in Figure 4. See [0046] “accelerators like dGPU 630.sub.1 to 630m”).)
Osqueizadeh does not explicitly disclose what Bolkhovitin teaches:
executing the program using a plurality of data comprising the first data and the second data on the first computational storage device, the program being executed by a compute engine …(See [0118] “sends one or more subsequent commands, also using a command module (e.g., module 252-3), to the first storage device and/or the second storage device to perform a peer-to-peer transfer of the write data from the second controller memory buffer to the first controller memory buffer and to perform a parity computation at the first storage device on the set of write data in the first controller memory buffer, as shown in 484” See [0119] “Two examples are provided for further illustration. In a first example, the one or more subsequent commands are a peer-to-peer transfer command to the second storage device to send the write data to the first storage device, and a parity computation command that is set to the first storage device after the peer-to-peer transfer is completed. In a second example, the one or more subsequent commands are combined transfer and parity computation command sent to the first storage device to pull in a copy of the write data from the second controller memory buffer and then to compute or update parity using the transferred copy of the write data.” See [0120] “Further, in some such embodiments, if any parity information has already been written to the memory block in the first storage device, it is updated with the write data in the first controller memory buffer. Also, in some embodiments, after sending the write and parity computation commands, the main controller subsystem receives one or more finished notifications from the first storage device and the second storage device” Parity computation is executed/updated on the first storage device by using write data (first data) brought from the second storage device and by using parity data (second data) that is already stored on the first storage device. See Abstract, Figure 4H and Figure 4I, [0107] and [0117]-[0120] for full context of offloading data writes to multiple storage devices for data computation(s).).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh with the data management function offload method of Bolkhovitin to improve the performance of non-volatile memory storage by offloading data management functions to one or more storage devices in a multi-device storage environment (See [0016] of Bolkhovitin).
Osqueizadeh and Bolkhovitin do not explicitly disclose what Kachare teaches:
directly transferring the second data from the shared memory space of the second computational storage device to the local memory of the first computational storage device (See [0046] “In some embodiments, one or more storage devices may use peer-to-peer data transfers to implement computational storage and/or otherwise offload computation and/or bandwidth loads from one or more hosts and/or host interfaces. For example, in some embodiments, one or more storage devices in a group or subgroup of devices having a peer-to-peer channel configured between them may be designated to perform data compression, encryption, and/or the like for the other storage devices in the group, subgroup, storage system, and/or the like. As another example, in some embodiments, one or more storage devices may use peer-to-peer channels to transfer intermediate calculation results between devices for further calculations without having to send and/or receive the intermediate results to and/or from a host.”) wherein the shared memory space and the local memory each comprise volatile memory (While the prior art does not explicitly disclose the shared memory and local memory to comprise volatile memory, memory can either be volatile or non-volatile. Therefore, it would have obvious to try, choosing from a finite number of identified, predictable memory technology types (i.e. such as non-volatile and volatile memory), with a reasonable expectation of success. That is, memory can be either volatile or non-volatile, with one of ordinary skilled in the art choosing between the two based on the limitations and advantages/disadvantages between the two memory technologies.);
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the offload method of Kachare to transfer intermediate calculation results between devices for further calculations without having to send and/or receive the intermediate results to and/or from a host.
Regarding claim 23, Osqueizadeh teaches:
The method of claim 19, further comprising storing the first data in the first non-volatile memory device of the first computational storage device and storing the second data in the second non-volatile memory device of the second computational storage device (See Figure 1 and Figure 6, in which data may be stored in a first non-volatile memory device and a second non-volatile memory device.), wherein, after the first and second data are respectively stored in the first and second non- volatile memory devices, the program is offloaded from the host device to the first computational storage device (See [0044] “SSG board 600 further includes an embedded controller 610 that offloads certain functions from NVM controllers 634.sub.1 to 634k.” See [0045] “Embedded controller 610 enables offloading high-throughput work from the host CPUs and enables dGPU 630.sub.1 to 630m to dispatch requests to NVM 635.sub.1 to 635k at a file system level, with embedded controller 610 managing the file system. In particular, embedded controller 610 can run NVMs 635.sub.1 to 635k as raw RAID storage array on SSG board 600 and provide a single linear addressed storage array view to other components. In an implementation, embedded controller 610 can be implemented or emulated on a dedicated host CPU thread or offloaded to a dedicated embedded system or CPU, (e.g. a field-programmable gate array (FPGA)), without a change to the application visible functionality. Offloading can improve performance and system throughput.”).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Osqueizadeh in view of Bolkhovitin in view of Kachare in view of Shim (U.S. Publication No. 2021/0326070)
Regarding claim 20, Shim teaches:
The method of claim 19, further comprising notifying from the second computational storage device to the first computational storage device that transfer of the second data device to the shared memory space is complete (See [0019] “a fifth storage operation of transmitting the data from the first storage device to the second storage device and then storing the data in the second storage device; a first transmission operation of generating, by the second storage device, the second storage information in response to the completion of the fifth storage operation and transmitting the second storage information to the first storage device;” See [0023] “The second storage device may be further suitable for generating second storage information in response to the completion of the storage of non-compressed the data, received from the first storage device, in the second storage device and transmitting the second storage information to the first storage device,”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the storage system of Osqueizadeh and the data management function offload method of Bolkhovitin with the data transfer method of Shim to ensure that all transmitted data is received prior to trying to access it, thus avoiding redundant access commands and improving I/O management.
Response to Arguments
Applicant's arguments filed October 13, 2025 in regards to newly filed amendments have been fully considered and are not persuasive. Applicant’s representative submitted that the combination of Osqueizadeh, Bolkhovitin, and Volpe does not teach “a second computational storage device that comprises a second compute engine including a second accelerator … the second compute engine of the second computational storage device is configured to execute the program using a plurality of data comprising the first data brought into the second computational storage device and the second data”. Specifically, applicant’s representative submitted that Bolkhovitin fails to teach or suggest that a compute engine including an accelerator is configured to execute a program using first and second data, since Bolkhovitin offloads data write requests to storage devices instead of using computing devices/accelerators to execute data write requests. Examiner respectfully disagrees and maintains that [0118] and [0119] of Bolkhovitin teaches the limitations set forth in claim one as recited in the rejection of claim 1, and further maintains that the combination of the cited references to the claimed limitations as a whole.
Applicant’s representative submitted that the combination of Osqueizadeh, Bolkhovitin, and Volpe does not teach “the second compute engine of the second computational storage device is configured to execute the program using a plurality of data comprising the first data brought into the second computational storage device and the second data”. Specifically, applicant’s representative submitted that Bolkhovitin teaches that the first storage device performs the parity computation on the set of write data transferred from the second controller memory buffer of the second storage device, but does not teach that the parity computation is performed on data including the set of write data transferred from the second controller memory buffer and data that is previously stored in the first controller memory buffer of the first storage device. Examiner respectfully disagrees, and maintains that the citations provided, in regards to parity updates/calculations in the art, are sufficient to teach that parity computation is executed/updated on the first storage device by using write data (first data) brought from the second storage device and by using parity data (second data) that is already stored on the first storage device. For example, see [0119] “In a second example, the one or more subsequent commands are combined transfer and parity computation command sent to the first storage device to pull in a copy of the write data from the second controller memory buffer and then to compute or update parity using the transferred copy of the write data.” See [0120] “Further, in some such embodiments, if any parity information has already been written to the memory block in the first storage device, it is updated with the write data in the first controller memory buffer.” See [0102] “Such offloaded services include global flash translation layer (FTL) addressing operations, parity computations (e.g., XOR, Reed-Solomon).” Paragraphs [0018]-[0120] teaches updating parity data using the transferred copy of the write data. As well known in the art, parity data may be updated by performing XOR calculations using the old data, new data, and old parity data (i.e. parity data that has been previously stored).
In regards to applicant’s arguments for claim 15, an obviousness rationale has been provided for use/substitution of volatile memory, as volatile memory is well known in the art. The arguments for claim 19 are similar to that of claim 1 and claim 15, and therefore are not persuasive for the same reasons provided for claim 1 and claim 15. In regards to the arguments for newly added claim 22, [0016] Osqueizadeh has been used to teach the limitation, therefore, such arguments are not persuasive. All pending claims are rejected herein.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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