DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed on 2/10/2026 have been fully considered but they are not persuasive.
Applicant argues that Lee fails to disclose:
An impedance transformer (IT) at the output;
An IT comprising a high-pass pi-type lumped circuit including:
a first part comprising an inductor,
a second part comprising an inductor,
connected via a capacitor;
A second part of the IT having:
a first end connected to the output and the capacitor,
a second end grounded.
Applicant further argues that Lee eliminates an impedance transformer and instead uses a post-matching LC network.
These arguments are not persuasive for the reasons set forth below.
I. Lee Explicitly Discloses an Output Impedance Transformer
Lee Fig. 9 shows the overall DPA including:
Carrier and Peaking amplifiers,
Output combining node,
Load network,
λ/4 impedance transforming section (see Fig. 4, Z0∠90°),
Lumped implementation thereof.
Lee expressly discloses that the λ/4 transmission line is implemented using lumped L-C-L networks (Fig. 4(a), Fig. 4(b)).
A quarter-wave impedance transformer implemented as an L-C-L high-pass pi-type lumped network constitutes an impedance transformer under its plain and ordinary meaning.
The fact that Lee discusses eliminating bulky transformers does not negate the presence of a lumped λ/4 impedance transforming structure.
Lee’s Fig. 4 and Fig. 9 clearly show:
Left and right LT sections,
LP inductors,
Capacitive element between them,
Implemented via bondwires in Fig. 9 (BW1, BW2, BW3).
Thus, Lee discloses an impedance transformer.
II. Lee Discloses a High-Pass pi-Type Lumped Circuit
Claim 1 now recites:
"an impedance transformer comprising a high-pass pi-type lumped circuit which further comprises a first part connected to a second part via a capacitor; each of the first part and the second part comprising an inductor"
Lee Fig. 4(a) discloses:
Inductor (LP)
Capacitor (C)
Inductor (LT)
This is structurally an L-C-L high-pass pi-type network.
Lee Fig. 4(b) shows merging of inductors.Lee Fig. 9 shows bondwire implementation.
Thus Lee discloses:
First inductor (left LT/merged LP-LT)
Capacitor (central C)
Second inductor (right LT/merged LP-LT)
Implemented as lumped components
Applicant’s distinction between transmission-line and lumped implementation is not persuasive because Lee explicitly teaches lumped realization of the λ/4 section.
III. Lee Discloses the Claimed Grounded Second Part
Claim 1 further requires:
"the second part of the impedance transformer being connected to the output and the capacitor at a first end thereof, and being grounded at a second end thereof."
In Lee Fig. 4(a):
The second inductor (LT) is connected at one end to the capacitor and output node.
The other end is tied to ground through RF ground reference.
Lee Fig. 9 shows this implemented via bondwire and grounded pad structure in the IC layout.
The RF ground return path is clearly present.
A ground-referenced inductor connected between node and ground satisfies the claimed limitation.
Applicant’s argument that Lee does not explicitly label this as “grounded” is not persuasive because RF grounding is inherent for DC bias terminal (VDD) in the depicted RF implementation and understood by a person of ordinary skill in the art.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (“Highly Efficient Fully Integrated GaN-HEMT Doherty Power Amplifier Based on Compact Load Network”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 12, DECEMBER 2017, cited by the applicant).
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Fig. 9 of Lee annotated by the examiner for ease of reference.
Regarding claim 1, Lee discloses (i.e., in Fig. 9) a schematic of a Doherty power amplifier (Overall schematic of the proposed DPA IC is shown in Fig. 9) comprising:
an input terminal (RFin);
(b) an output terminal (RFout);
(c) a main or carrier amplifier (Carrier shown in Fig. 9) connected between the input terminal (RFin) and the output terminal (RFout);
(d) an auxiliary or peak amplifier (Peaking shown in Fig. 9) connected in parallel to the carrier amplifier between the input terminal (RFin) and the output terminal (RFout);
(e) an output matching network (designated as ‘OM’ by the examiner as shown in the annotated Fig. 9 above) connected between the output (RFout), and the main (carrier) and auxiliary (Peaking) power amplification devices; and
(f) an impedance transformer (designated as ‘IT’ by the examiner as shown in the annotated Fig. 9 above) connected between the output matching network (OM) and the output (RFout);
the impedance transformer (designated by the examiner as IT in the annotated Fig. 4(a) of Lee) comprising a high-pass pi-type lumped circuit which further comprises a first part (left LT) connected to a second part (right LT) via a capacitor (CT); each of the first part and the second part comprising an inductor (LT);
wherein a first part (Lp of the carrier amplifier) of the output matching network is merged with a first part (left LT of the high-pass pi-type lumped circuit in Fig. 4(a)). the second part (right LT of the high-pass pi-type lumped circuit in Fig. 4(a)) of the impedance transformer (IT being merged with Lp of the peaking amplifier) being connected to the output (Output, RF+DC) and the capacitor (CT) at a first end (top end) thereof, and being grounded at a second end (bottom is RF grounded, VDD is RF ground) with thereof.
[AltContent: textbox (IT)]
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Figs. 4(a)-left and 4(b)-right of Lee annotated by the examiner for ease of reference.
wherein per claim 2, both the output matching network comprises a high-pass pi-type lumped networks (see Fig. 4(a)); the first part of the output matching network (LT at the output of the carrier amplifier and LT at the output of the peaking amplifier) and the first part (left and right LPs of the impedance transformer) comprising inductors that are merged (see Fig. 4), and
wherein per claim 3, the inductors (carrier LP and left LT in Fig. 4(a) are merged as L’T (Fig. 4(b)) to become the bondwire BW1 in Fig. 9 and peaking LP and right LT in Fig. 4 (a) are merged as L’T (Fig. 4(b)) to become the bondwire BW2 in Fig. 9 and part of the impedance transformer of Fig. 4 is implemented as BW3) are merged to be implemented as bondwires.
Further per claim 4, the DPA of Lee also comprises a power splitter (see Fig. 9) and an input offset line (offset TL) that are connected between the input (RFin), and the main (carrier) and auxiliary (peaking) power amplification device (Fig. 9); wherein a first part of the input offset line is merged with a first part of the power splitter (see Figs. 8(a) and 8(b)).
wherein per claim 5, both the input offset line (offset TL) and the power splitter (input splitter as shown in Fig. 8(a)) comprise high-pass n-type lumped networks (see Fig. 8(a)); the first part of the input offset line and the first part of the power splitter comprising inductors that are merged (Figs 8(a) and 8(b)).
wherein per claim 6, the inductors that are merged are implemented as a bondwire (see Fig. 10(a) the two bondwires at the input of the DPA IC).
wherein per claim 7, the power splitter (input splitter in Fig. 8(a)) further comprises a second part (bottom part in Fig. 8(a) is considered as a second part as opposed to a top part of Fig. 8(a) which would be considered as a first part) that comprises inductors (see Fig. 8(a)) which are merged within the power splitter (Fig. 8(b)).
Further per claim 8, the DPA of Lee comprises an input matching network (designated as ‘IM’ by the examiner as shown in the annotated Fig. 9 above) that is connected between the input, and the main (carrier) and auxiliary (peaking) power amplification devices; the input matching network (IM) comprising shunt inductors which are implemented using bondwires (designated as ‘BW4’ and ‘BW5’ by the examiner as shown in the annotated Fig. 9 above).
wherein per claim 9, the input matching network (IM) is merged with an input bias network (gate supply voltages for carrier (VGS,C) and peaking (VGS,P) amplifiers).
wherein per claim 10, the output matching network (OM) is merged with an output bias network (Drain supply voltages for carrier (VCD) and peaking (VPD) amplifiers).
wherein per claim 11, the impedance transformer (IT) further comprises a second part that comprises an inductor implemented using a bondwire (BW3).
wherein per claim 12, the impedance transformer is a l/4 impedance transformer (see Fig. 4, Z0∠90°).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
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Modified Fig. 4(a) of Lee considering Fig. 1 of Ember and annotated by the examiner for ease of reference.
Regarding claims 13 and 14, Lee teaches all limitations of claim 1, Lee however, didn’t show explicitly a first and second part of an output offset line.
It is, however, well-known in the art of Doherty amplifiers that there exists offset between the outputs of carrier and peaking amplifiers, which are usually implemented in the form of transmission line segments or through equivalent lumped elements. Although not explicitly shown it must have been included in the output matching networks of the carrier and peaking amplifiers before the combining nodes.
While a person of ordinary skill in the art would find it obvious based on the teaching of Lee of merging to consolidate multiple inductances into one inductance element and similarly consolidating multiple capacitance elements into one capacitive element, to be able to merge and consolidate any first and second parts of output offset line (realized in the form of inductance or capacitances) conveniently as one element between the output of the carrier amplifier and the combining node and as a second one between the output of the peaking amplifier and the combining node as discussed earlier in regards to claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.