Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
2. Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-11, drawn to a compute-in-memory apparatus, classified in G11C 11/4072
II. Claims 12-14, drawn to a convolutional neural network, classified in G06N3/0464
The inventions are independent or distinct, each from the other because:
3. Inventions I and II are related as subcombinations disclosed as usable together in a single combination. The subcombinations are distinct if they do not overlap in scope and are not obvious variants, and if it is shown that at least one subcombination is separately usable. In the instant case, subcombination II has a separate utility such as a convolutional neural network which is software as opposed to the compute-in-memory hardware, and which does not require such hardware to be run. See MPEP § 806.05(d).
The Examiner has required restriction between subcombinations usable together. Where applicant elects a subcombination and claims thereto are subsequently found allowable, any claim(s) depending from or otherwise requiring all the limitations of the allowable subcombination will be examined for patentability in accordance with 37 CFR 1.104. See MPEP § 821.04(a). Applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
4. Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
a) Different recognized classification among the prior art between Inventions I and II.
b) The search for Invention I would be quite different than that for Invention II. For example, Invention I pertains to specific hardware technology and Invention II pertains to specific software technology.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
5. During a telephone conversation with Mr. Zachary Cody on 6/1/26, a provisional election was made without traverse to prosecute the invention of I, claims 1-11. Note that linking claim 15 will be included with this election as well. Affirmation of this election must be made by applicant in replying to this Office action. Claims 12-14 are withdrawn from further consideration by the Examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
6. Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim(s) 1-2, 5, 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 11,322,199 B1) and Kashmiri et al “Kashmiri” (US 2022/0027130 A1) and Srivastava et al “Srivastava” (US 11657238 B2).
(Please see the attached copy of Li and Srivastava that numbers paragraphs in the same manner as that used in this Action).
9. Regarding claim 1, Li shows a compute-in-memory apparatus (para 6, 16, Figure 2A), wherein the apparatus comprises: a computing array, which includes a plurality of computing modules (para 8, 16, 35, Figures 6, 9 show the computing array with plurality of computing circuits), the computing module comprises at least one storage cell (Figures 2A, 6, 8A, para 16-18, 29 show the storage circuit) and a capacitor (para 21-23 show the capacitor), the storage cell comprises at least one storage switch (para 16-18 show the switch included with the storage circuit), wherein: the storage switch comprises a storage control terminal, a storage detection terminal and a storage terminal, the storage terminal is connected to a data storage line to receive a storage state voltage and information associated with the storage state voltage, the storage control terminal is connected to a control word-line to receive a control voltage (para 8, 16-18, 29 show the storage circuit switch has a storage terminal connected to a data storage line and receives a word voltage storage state input; para 29, 33, show a storage control terminal connects to the word-line to receive a control voltage); a control module, which is connected to the computing array to control the computing array to perform at least one of a store operation, a read operation and a compute operation (note the alternative recitation - para 16, 34, 48 shows a control circuit connected to the array to perform store and read operations for example). As noted, Li para 29, 33, show the storage control terminal is connected to a control word-line to receive a control voltage, and Li para 16-17 further show multiply-and-accumulate operations, but Li does not explicitly show adjusting the impedance characteristic between the storage detection terminal and the storage terminal. Kashmiri however does show in a compute-in-memory device, adjusting the impedance characteristic between the storage detection terminal and the storage terminal (para 56 shows the in-memory compute device, and para 91, 168, 192-193, 214 show adjusting impedance characteristics between the storage terminal which receives a storage state voltage and a voltage [storage] detection terminal). It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to adjust the impedance characteristic between the storage detection terminal and the storage terminal in Li, as is done in Kashmiri, because it would allow the array to naturally perform multiply-and-accumulate operations, and would provide an efficient way to process data directly in memory while minimizing unnecessary energy consumption (Kashmiri para 168). Neither Li nor Kashmiri explicitly show a reset switch comprising a reset control terminal, a reset detection terminal and a reset terminal, the reset control terminal is connected to a control word-line to receive a reset voltage to adjust the impedance characteristic between the reset detection terminal and the reset terminal; the reset terminal is connected to a reset state voltage line to receive a reset state voltage, the reset detection terminal and a first terminal of the capacitor are connected to an output terminal of at least one storage module, a second terminal of the capacitor is connected to a computing bit-line. Srivastava however does show a compute-in-memory device (para 18 shows the compute-in-memory device) with a reset switch comprising a reset control terminal, a reset detection terminal and a reset terminal, the reset control terminal is connected to a control word-line to receive a reset voltage to adjust the impedance characteristic between the reset detection terminal and the reset terminal (para 11, 15-16, 19 show the reset switch has a reset terminal connected to a data storage line and receives a word voltage storage state input; para 11, 14-17 show a reset control terminal connects to the word-line to receive a control voltage); the reset terminal is connected to a reset state voltage line to receive a reset state voltage (para 15-16 show the reset terminal line receiving the control voltage is connected to a reset state voltage line to receive the reset state voltage), the reset detection terminal and a first terminal of the capacitor are connected to an output terminal of at least one storage module (para 28-29 show a receiving/detecting reset terminal and [first] terminal of a capacitor are connected to an output terminal of a storage circuit), a second terminal of the capacitor is connected to a computing bit-line (para 11, 14-15, 28-29 show the second terminal of the capacitor is connected to a computing bit-line). Furthermore, Srivastava para 18, Figures 2A-B show the reset phase applied in a multiply accumulate circuit. It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have the reset switch including the reset control terminal, reset detection terminal and reset terminal as is in Srivastava, in the compute-in-memory device of Li, especially as modified by Kashmiri, because it would provide an efficient way to regulate current and perform multiply-and-accumulate operations (Srivastava para 18). As noted, Srivastava para 11, 14-17 show the storage control terminal is connected to a control word-line to receive a control voltage, para 18, Figures 2A-B show the reset phase applied in a multiply accumulate circuit. Also Li para 16-17 further show multiply-and-accumulate operations. Nevertheless, Srivastava (and Li) do not explicitly show adjusting the impedance characteristic between the reset detection terminal and the reset terminal. Kashmiri as noted does show adjusting the impedance characteristic between a detection terminal and a storage terminal (para 56 shows the in-memory compute device, and para 91, 168, 192-193, 214 show adjusting impedance characteristics between the terminal which receives a storage state voltage and a voltage detection terminal). It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to apply Kashmiri’s ability to adjust the impedance characteristic, between the reset detection terminal and the reset terminal in Srivavasta, because it would provide an efficient way to regulate current in tandem with the reset switch, and it would help to efficiently perform multiply-and-accumulate operations.
10. Regarding claim 2, the storage cell comprises a first storage switch and a second storage switch, the storage detection terminals of both the first storage switch and the second storage switch are connected to the output terminal of the storage cell (Li para 16-18, 29 show multiple storage circuits and each has a storage switch which are connected to the output terminal of the storage circuit).
11. Regarding claim 5, Li shows the compute operation includes a multiply-and-accumulate operation (Li para 16, 23, 39, 44 shows the multiply-and-accumulate operation), the control module is additionally used to: activate the storage control terminal of the storage switch of the storage cell of a target computing module (Li para 20, 23, 25, 29 show activating the storage control terminal which is the storage circuit switch having a storage terminal connected to a data storage line and receiving a word voltage storage state input), thereby a logic AND operation is performed on the information carried by the control word-line connected to the storage control terminal of the activated storage switch and the information associated with the storage state voltage of the storage terminal of the activated storage switch (Li para 30-31, 33, 43-45 show the logic AND operation applied to the information carried by the control word-line connected to the activated storage control terminal and the information associated with the storage state voltage of the storage terminal which is part of the now activated storage switch); obtain a result of the multiply-and-accumulate operation via the computing bit-line (Li para 35, 39, 41, 49, 52 show the result of the multiply-and-accumulate obtained through the computing bit line).
12. Regarding claim 7, in addition to that mentioned for claim 1, Li shows the compute operation includes a logic AND operation, such that the control module is additionally used to input a set of operands for the logic AND operation via the storage control terminal, the control word-line connected to the storage control terminal of the storage switch and the data storage line connected to the storage terminal of the storage switch (Li para 30-31, 33, 43-45 show the logic AND operation applied to the control word-line connected to the [activated] storage control terminal of the storage switch and the data/information storage line connected to the storage terminal which is part of the storage switch); obtain a result of the logic AND operation on the set of operands via the computing bit-line (Li para 30, 41, 43, 45 show the result of the logic AND operation obtained through the computing bit line). Li does not explicitly show one of the operands is the reset control terminal per se, such that the control module is additionally used to activate the reset control terminal of the reset switch of a target computing module and the computing bit-line, thereby a voltage difference is maintained between the two terminals of the capacitor of the target computing module; turn off the reset control terminal and set the computing bit-line into floating state. Srivastava however does show using the reset control terminal as an operand for AND derivable logic operations (Srivastava para 11-12, 28 show the reset control terminal [as explained for claim 1] is applied to a logical XNOR operation. Note that the gate may be implemented such that one input is high thus simulating a logic AND operation), and activating the reset control terminal of the reset switch of a target computing module and the computing bit-line, thereby a voltage difference is maintained between the two terminals of the capacitor of the target computing module (Srivavasta para 11-12, 15-17 show applying a signal to the reset control terminal [of the reset switch] of a particular/target circuit and the computing bit line, and a voltage difference is applied between the two terminals of the capacitor and target circuit); turning off the reset control terminal and set the computing bit-line into floating state (Srivastava para 11, 15-16, 29 show turning off the reset control terminal thereby placing the computing bit line into a float state). It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to use the reset control terminal as described in the compute-in-memory device of Li, especially as modified by Kashmiri, because it would provide an efficient way to enable bit serial accumulation for multiply-and-accumulate operations.
13. Regarding claim 8, in addition to that mentioned for claim 1, within the same column of the computing array, the control bit lines and computing bit-lines of at least one computing module are connected (Li para 37-38, 50 show the control/write bit line and compute/read bit lines within the same column of the computing array are coupled); within the same row of the computing array, the control word-lines, data storage lines and reset state voltage lines of at least one computing module are connected (Li para 8 show control word lines and data storage lines coupled within the same row of the computing array. Srivastava para 15-17, 22 show control word lines, data lines, and reset state voltage are coupled within the same row of the computing array – motivation to combine Srivastava with Li (and Kashmiri) is the same as that mentioned for claim 1).
14. Regarding claim 9, in addition to that mentioned for claim 8, the compute operation includes a multiply-and-accumulate operation (Li para 16 for example show the compute operation includes a multiply-and-accumulate operation), the control module is additionally used to: control one or more columns of computing modules of the computing array to perform a multiply-and-accumulate operation, and/or control some or all of the computing modules connected to the same computing bit-line to perform the multiply-and-accumulate operation (note the alternative recitation – Li para 35, 39, 49, 52 show controlling a column of circuits in the computing array to perform a multiply-and-accumulate operation).
15. Regarding claim 10, in addition to that mentioned for claim 8, the control module is additionally used to control the computing modules connected to different computing bit-lines to perform a pipelined compute operation (Li para 39, 49, 52 show circuits connected to different computing bit lines to process different stages of computations with overlapping execution, and accumulating results over cycles - this is a pipelining technique).
16. Regarding claim 11, in addition to that mentioned for claim 8, Li does not explicitly show the control module is additionally used to control each control word-line, control bit line, computing bit-line, data storage line and reset state voltage line to be grounded, whereby the computing array enters an idle mode. However Kashmiri para 206 shows the control word line, the control bit line, computing bit line, and data storage line are grounded, which then disables the array and places it in an idle mode. Srivastava para 11, 13, 15, 22 shows the reset state voltage line, word line, and computing bit line are grounded. It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to ground each control word-line, control bit line, computing bit-line, data storage line and reset state voltage line in the compute-in-memory device of Li, as is done in Kashmiri and Srivastava, because it would provide an efficient way for routine power management (Kashmiri para 201).
17. Claim(s) 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li and Kashmiri and Srivastava and Rawat et al “Rawat” (US 11984151 B2).
(Please also see the attached copy of Rawat that numbers paragraphs in the same manner as that used in this Action).
18. Regarding claim 3, in addition to that mentioned for claim 1, Kashmiri shows the computing module additionally comprises a selection switch, the selection switch comprises a selection control terminal, a first detection terminal and a second detection terminal (para 215-216, 221, 227 show the selector switch with a selection control and a first and second detection/threshold terminals), wherein the selection control terminal is connected to a control bit line to receive a control voltage to adjust the impedance characteristic between the first detection terminal and the second detection terminal (para 215, 221 show the selector switch is connected to a control bit line and receives a control voltage. Para 206, 213-214 show the voltage adjusts the impedance characteristic between the first and second detection/threshold terminals). Kashmiri (and Li and Srivastava) do not explicitly show that the first detection terminal is connected to the output terminal of the storage cell, the second detection terminal is connected to each storage detection terminal. However, Rawat shows a compute-in-memory device in which a selection switch has first and second detection terminals such that the first detection terminal is connected to the output terminal of the storage cell and the second detection terminal is connected to each storage detection terminal (Rawat para 26, 28, 38, 40-41 show selection switch with a first driven/detection line connecting to an output of a storage node and a second driven/detection line connecting to the storage assertion lines). It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have a selection switch having first and second detection terminals such that the first detection terminal is connected to the output terminal of the storage cell, and the second detection terminal is connected to each storage detection terminal, as in Rawat, in the compute-in-memory device of Li, as modified by Kashmiri and Srivastava, because it would allow the hardware to decouple data storage from computational sensing.
19. Regarding claim 6, in addition to that mentioned for claim 3, the compute operation includes a multiply-and-accumulate operation (Li para 16, 23, 39, 44 shows the multiply-and-accumulate operation), the control module is additionally used to: activate the storage control terminal of the storage switch of the storage cell of a target computing module (Li para 20, 23, 25, 29 show activating the storage control terminal which is the storage circuit switch having a storage terminal connected to a data storage line and receiving a word voltage storage state input), thereby a logic AND operation is performed on the information carried by the control word-line connected to the storage control terminal of the activated storage switch and the information associated with the storage state voltage of the storage terminal of the activated storage switch (Li para 30-31, 33, 43-45 show the logic AND operation applied to the information carried by the control word-line connected to the activated storage control terminal and the information associated with the storage state voltage of the storage terminal which is part of the now activated storage switch); obtain a result of the logic AND operation via the computing bit-line (Li para 30, 41, 43, 45 show the result of the logic AND operation obtained through the computing bit line). Note also that Rawat para 26, 28, 38, 40-41 show the selection control terminal of the selection switch would be connected to the storage control terminal of the storage switch. Motivation to combine Rawat into Li, as modified by Kashmiri and Srivastava, is the same as that given for claim 3.
20. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li and Kashmiri and Srivastava and Quader et al “Quader” (US 2022/0114424 A1).
21. Regarding claim 15, Li shows a compute-in-memory apparatus (para 6, 16, Figure 2A), wherein the apparatus comprises: a computing array, which includes a plurality of computing modules (para 8, 16, 35, Figures 6, 9 show the computing array with plurality of computing circuits), the computing module comprises at least one storage cell (Figures 2A, 6, 8A, para 16-18, 29 show the storage circuit) and a capacitor (para 21-23 show the capacitor), the storage cell comprises at least one storage switch (para 16-18 show the switch included with the storage circuit), wherein: the storage switch comprises a storage control terminal, a storage detection terminal and a storage terminal, the storage terminal is connected to a data storage line to receive a storage state voltage and information associated with the storage state voltage, the storage control terminal is connected to a control word-line to receive a control voltage (para 8, 16-18, 29 show the storage circuit switch has a storage terminal connected to a data storage line and receives a word voltage storage state input; para 29, 33, show a storage control terminal connects to the word-line to receive a control voltage); a control module, which is connected to the computing array to control the computing array to perform at least one of a store operation, a read operation and a compute operation (note the alternative recitation - para 16, 34, 48 shows a control circuit connected to the array to perform store and read operations for example). As noted, Li para 29, 33, show the storage control terminal is connected to a control word-line to receive a control voltage, and Li para 16-17 further show multiply-and-accumulate operations, but Li does not explicitly show adjusting the impedance characteristic between the storage detection terminal and the storage terminal. Kashmiri however does show in a compute-in-memory device, adjusting the impedance characteristic between the storage detection terminal and the storage terminal (para 56 shows the in-memory compute device, and para 91, 168, 192-193, 214 show adjusting impedance characteristics between the storage terminal which receives a storage state voltage and a voltage [storage] detection terminal). It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to adjust the impedance characteristic between the storage detection terminal and the storage terminal in Li, as is done in Kashmiri, because it would allow the array to naturally perform multiply-and-accumulate operations, and would provide an efficient way to process data directly in memory while minimizing unnecessary energy consumption (Kashmiri para 168). Neither Li nor Kashmiri explicitly show a reset switch comprising a reset control terminal, a reset detection terminal and a reset terminal, the reset control terminal is connected to a control word-line to receive a reset voltage to adjust the impedance characteristic between the reset detection terminal and the reset terminal; the reset terminal is connected to a reset state voltage line to receive a reset state voltage, the reset detection terminal and a first terminal of the capacitor are connected to an output terminal of at least one storage module, a second terminal of the capacitor is connected to a computing bit-line. Srivastava however does show a compute-in-memory device (para 18 shows the compute-in-memory device) with a reset switch comprising a reset control terminal, a reset detection terminal and a reset terminal, the reset control terminal is connected to a control word-line to receive a reset voltage to adjust the impedance characteristic between the reset detection terminal and the reset terminal (para 11, 15-16, 19 show the reset switch has a reset terminal connected to a data storage line and receives a word voltage storage state input; para 11, 14-17 show a reset control terminal connects to the word-line to receive a control voltage); the reset terminal is connected to a reset state voltage line to receive a reset state voltage (para 15-16 show the reset terminal line receiving the control voltage is connected to a reset state voltage line to receive the reset state voltage), the reset detection terminal and a first terminal of the capacitor are connected to an output terminal of at least one storage module (para 28-29 show a receiving/detecting reset terminal and [first] terminal of a capacitor are connected to an output terminal of a storage circuit), a second terminal of the capacitor is connected to a computing bit-line (para 11, 14-15, 28-29 show the second terminal of the capacitor is connected to a computing bit-line). Furthermore, Srivastava para 18, Figures 2A-B show the reset phase applied in a multiply accumulate circuit. It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have the reset switch including the reset control terminal, reset detection terminal and reset terminal as is in Srivastava, in the compute-in-memory device of Li, especially as modified by Kashmiri, because it would provide an efficient way to regulate current and perform multiply-and-accumulate operations (Srivastava para 18). As noted, Srivastava para 11, 14-17 show the storage control terminal is connected to a control word-line to receive a control voltage, para 18, Figures 2A-B show the reset phase applied in a multiply accumulate circuit. Also Li para 16-17 further show multiply-and-accumulate operations. Nevertheless, Srivastava (and Li) do not explicitly show adjusting the impedance characteristic between the reset detection terminal and the reset terminal. Kashmiri as noted does show adjusting the impedance characteristic between a detection terminal and a storage terminal (para 56 shows the in-memory compute device, and para 91, 168, 192-193, 214 show adjusting impedance characteristics between the terminal which receives a storage state voltage and a voltage detection terminal). It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to apply Kashmiri’s ability to adjust the impedance characteristic, between the reset detection terminal and the reset terminal in Srivavasta, because it would provide an efficient way to regulate current in tandem with the reset switch, and it would help to efficiently perform multiply-and-accumulate operations.
A compute-in-memory apparatus is a type of neural network accelerator, and Li para 16, 27, 39, 41, Figure 1 show the neural network being implemented using the compute-in-memory apparatus. However, neither Li nor Kashmiri nor Srivastava go into the details that the neural network accelerator comprises at least one neural network module, the neural network module comprises at least one original convolutional layer, and the original convolutional layer comprises a backbone layer that has fixed weights and a branch layer that has adjustable weights, the backbone layer comprises one or more convolutional layers, and the branch layer at least comprises a first branch convolutional layer, a second branch convolutional layer, and a third branch convolutional layer, which are sequentially connected, the input channel number of the first branch convolutional layer is equal to that of the backbone layer, the output channel number of the third branch convolutional layer is equal to that of the backbone layer, the input channel number of the second branch convolution layer is smaller than that of the backbone layer, and the output channel number of the second branch convolution layer is smaller than that of the backbone layer, wherein the backbone layer and the convolutional layers of the branch layer are implemented using the compute-in-memory apparatus. Nevertheless, Quader shows a neural network accelerator (para 45 shows that the processing units performing the operations of a convolutional neural network, may be a neural network accelerator), wherein the neural network accelerator comprises at least one neural network module, the neural network module comprises at least one original convolutional layer (Figure 1C, para 13, 19, 42 show the neural network module with at least one convolutional layer), and the original convolutional layer comprises a backbone layer that has fixed weights (para 42, 51, 58 show the feature extraction layer [which is another name for the backbone layer] that has a set of specific weights) and a branch layer that has adjustable weights (para 104, 106, 107 show the branch layers which have weights that may be adjusted), the backbone layer comprises one or more convolutional layers (para 42, 51, 54 show the backbone/feature extraction layer has several convolutional layers), and the branch layer at least comprises a first branch convolutional layer, a second branch convolutional layer, and a third branch convolutional layer, which are sequentially connected (para 63, 65, 67 show the branch layer has first, second, and third branch convolutional layers sequentially connected), the input channel number of the first branch convolutional layer is equal to that of the backbone layer and the output channel number of the third branch convolutional layer is equal to that of the backbone layer (para 127, 129-130 show the number of input and output channels for the first branch convolutional layer is equal to that of the feature extraction [aka backbone] layer), the input channel number of the second branch convolution layer is smaller than that of the backbone layer and the output channel number of the second branch convolution layer is smaller than that of the backbone layer (para 13-14, 64, 70, 75 show that the number of input and output channels for the second branch convolution layer is reduced and smaller than that of the feature extraction [aka backbone] layer). It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have the neural network convolutional layer details of Quader in the neural network accelerator of Li, especially as modified by Kashmiri and Srivastava, because it would provide an efficient convolutional neural network whose operations can be performed using a compute-in-memory apparatus. Given the combination, the backbone/feature extraction layer and convolutional layers of the branch layer would thus be implemented by the compute-in-memory apparatus.
Allowable Subject Matter
22. Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The additional selection switches and storage switches and their particular connections as recited, in combination with the limitations of intervening claim 3 and independent claim 1, together are not set forth in the prior art of record.
Conclusion
23. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
a) Chang (US 11714570 B2) shows a compute-in-memory device which specifically describes a reset switch mechanism.
b) He (CN 116934583 A) shows a neural network accelerator with feature extraction/backbone layer and branch convolutional layers.
c) Shaik (US 111776991 B1) shows a compute-in-memory device for multiply-and-accumulate operations.
24. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN PAUL SAX whose telephone number is (571)272-4072. The examiner can normally be reached Monday - Friday, 9:30 - 6:00 Est.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Usmaan Saeed, can be reached at 571-272-4046. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN P SAX/ Primary Examiner, Art Unit 2146
Prosecution Insights