DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed December 18, 2025, have been fully considered but they are not persuasive.
Applicant argues US Publication 2020/0107449 to Fu does not teach or suggest wherein one or both of: the first layer is monolithic, such that there is no interface between the first horizontal portion and the first vertical portion; or the second layer is monolithic, such that there is no interface between the second horizontal portion and the second vertical portion, as recited in amended claim 1 (and previously pending claim 10). Applicant similarly argues Fu fails to teach or suggest, “continuous and monolithic” as recited in claim 19.
As previously set forth, Fu (FIG. 8-12) teaches a fully additive circuit board processing method resulting in no interface between a horizontal portion (120 and 130) and a vertical portion (113).
Applicant asserts in FIG. 11: “Item 21b of Fu represents a seam or boundary”.
As shown in FIG. 12 (a portion of which is reproduced below) and disclosed in paragraphs 39-40 of Fu, first conductive circuit layer 120, second conductive circuit layer 130 and conductive line 21b are formed by a fully additive process, one that does not create an interface between the first conductive circuit layer and conductive line 21b.
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Regarding Applicant’s assertion of a special definition of “monolithic” (Arguments 5), the specification does not clearly set forth a definition of the term that is different from its ordinary and customary meaning. The portions of the specification using monolithic use “e.g.” and “example” and do not unambiguously act to define “monolithic” in a particular and specific way.
It is also noted the specification sets forth on pages 8-9 paragraph 21 (emphasis added):
For example, the layer 107, including the horizontal portion 109 and the vertical portions 111, may be formed using a same conductive material deposition process (e.g., formed using an additive deposition process), and hence, the layer 107 may be continuous and monolithic. However, in another example, the horizontal portion 109 and the vertical portions 111 may be formed by separate conductive material deposition process, and there may be an interface therebetween.
Given that Fu teaches a fully additive processing method without any interface, Applicant’s argument that Fu fails to teach or suggest “monolithic” as recited in claim 1 and “continuous and monolithic” as recited in claim 19 is unpersuasive.
Applicant argues US Publication 2018/0132355 to Saita et al. (hereinafter Saita) fails to disclose a first and second contact pad structure as recited in claim 15 (Arguments 3). Applicant argues, “the vias of Saita and layers 21 and 22 are different structures. This is particularly notable with Item 21 of Saita as Item 21 does not make contact with via 51” (Arguments 4).
As shown below on a marked-up FIG. 1 of Saita:
Saita (FIG. 1) discloses an apparatus comprising:
a first contact pad structure (51; paragraph 33) comprising conductive material, and a first horizontal portion (21) of conductive material extending from the first contact pad structure (51) along a first horizontal plane;
a second contact pad structure (52; paragraph 33) comprising conductive material, and a second horizontal portion (22) of conductive material extending from the second contact pad (22) structure along a second horizontal plane different from the first horizontal plane; and
a layer of dielectric material (23; paragraph 29) between the first horizontal plane and the second first horizontal plane, the layer of dielectric material (23) having a thickness of at most 4000 nanometers (nm)(paragraph 50).
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Applicant’s argument that 51 of Saita does not contact 21 and that 52 does not contact 22 is therefore unpersuasive.
Accordingly, Applicant's arguments have been fully considered but they are not persuasive.
Information Disclosure Statement
The information disclosure statement (IDS) submitted is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
The objection to the claims is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saita.
Claim 15
Saita (FIG. 1) discloses an apparatus comprising:
a first contact pad structure (51; paragraph 33) comprising conductive material, and a first horizontal portion (21) of conductive material extending from the first contact pad structure (51) along a first horizontal plane;
a second contact pad structure (52; paragraph 33) comprising conductive material, and a second horizontal portion (22) of conductive material extending from the second contact pad (22) structure along a second horizontal plane different from the first horizontal plane; and
a layer of dielectric material (23; paragraph 29) between the first horizontal plane and the second first horizontal plane, the layer of dielectric material (23) having a thickness of at most 4000 nanometers (nm)(paragraph 50).
Claim 16
Saita discloses the apparatus of claim 15, wherein:
at least a section of the first horizontal portion (21) provides a first capacitor electrode, at least a section of the second horizontal portion (22) provides a second capacitor electrode, and at least a section of the layer of dielectric material (23) provides a capacitor dielectric; and
the first capacitor electrode, the second capacitor electrode, and the capacitor dielectric provide a capacitor (20; paragraph 29).
Claim 17
Saita discloses the apparatus of claim 15, wherein:
the first contact pad structure (51) comprises a vertical structure that extends through an opening within the second horizontal portion (22), without making contact with the second horizontal portion (22).
Claim 18
Saita discloses the apparatus of claim 15, wherein:
the second contact pad (52) structure comprises a vertical structure that extends through an opening within the first horizontal portion (21), without making contact with the first horizontal portion (21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 13-14, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2020/0126934 to Oyamada in view of Fu.
Claim 1
Oyamada (FIG. 1) discloses an interconnect structure comprising:
a first layer of conductive material comprising (i) a first horizontal portion (11; paragraph 44-45) extending along a first horizontal plane, with a first opening (11A; paragraph 45) within the first horizontal portion (11), and (ii) a first vertical portion (3G);
a second layer of conductive material comprising (i) a second horizontal portion (13; paragraph 44, 47) extending along a second horizontal plane, with a second opening (13A; paragraph 47) within the second horizontal portion (13), and (ii) a second vertical portion (3P); and
a layer of dielectric material (12; paragraph 44, 46) extending along a third horizontal plane between the first and second horizontal portions (11, 13), and having third and fourth openings (12A; paragraph 46);
wherein the first vertical portion (3G) extends upward from the first horizontal portion (11), through the third opening (12A) within the layer of dielectric material (12) and through the second opening (13A) within the second horizontal portion (13); and
wherein the second vertical portion (3P) extends downward from the second horizontal portion (13), through the fourth opening (12A) within the layer of dielectric material (12) and through the first opening (11A) within the first horizontal portion (11), as recited in claim 1.
Oyamada does not expressly disclose wherein one or both of: the first layer is monolithic, such that there is no interface between the first horizontal portion and the first vertical portion; or the second layer is monolithic, such that there is no interface between the second horizontal portion and the second vertical portion, as recited in claim 1.
Fu (FIG. 8-12) teaches a fully additive circuit board processing method resulting in no interface between a horizontal portion (120 and 130) and a vertical portion (113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Fu with Oyamada to incorporate a fully additive process as taught by Fu in the structure taught by Oyamada and thereby have one or both of: the first layer monolithic, such that there is no interface between the first horizontal portion and the first vertical portion; or the second layer monolithic, such that there is no interface between the second horizontal portion and the second vertical portion, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for the use of laser processing (Fu paragraph 24, 35) and precise control of a continuous and smooth layer of metal, allowing for avoidance of discontinuities and contamination of boundaries between vias and traces if they were processed at different times.
Claim 2
Oyamada with Fu teaches the interconnect structure of claim 1, wherein:
at least a section of the first horizontal portion (Oyamada 11) provides a first capacitor electrode, at least a section of the second horizontal portion (13) provides a second capacitor electrode, and at least a section of the layer of dielectric material (12) provides a capacitor dielectric; and
the first capacitor electrode, the second capacitor electrode, and the capacitor dielectric provide a capacitor (10; paragraph 44).
Claim 3
Oyamada with Fu teaches the interconnect structure of claim 1, further comprising:
a first interconnect component (Oyamada 3; paragraph 40) coupled to an upper surface of the first vertical portion (3G); and
a second interconnect component (3) coupled to an upper surface of the second horizontal portion (13 coupled to 3P).
Claim 4
Oyamada with Fu teaches the interconnect structure of claim 1, wherein:
the first horizontal portion (Oyamada 11) has a fifth opening therewithin (11A);
the second horizontal portion (13) has a sixth opening therewithin (13A);
the layer of dielectric material (12) has a seventh opening therewithin (12A);
a third layer of conductive material (3S) extending vertically through the fifth, sixth, and seventh openings (11A-13A).
Claim 5
Oyamada with Fu teaches the interconnect structure of claim 4, further comprising:
a first interconnect component (Oyamada 3) coupled to an upper surface of the first vertical portion (3G);
a second interconnect component (3) coupled to an upper surface of the second horizontal portion (13 coupled to 3P); and
a third interconnect component (3) coupled to an upper surface of the third layer (3S).
Claim 6
Oyamada with Fu teaches the interconnect structure of claim 5, wherein each of the first, second, and third interconnect components is a solder ball or a solder bump (Oyamada when viewing FIG. 1 upside-down: the power electrode structure 3P extending upwards from layer 13 becomes the first vertical portion, the ground electrode structure 3G extending downwards from layer 11 becomes the second vertical portion of claim 1, and the signal electrode structure 3S extending through layers 11-12 becomes the third layer of conductive material, and therefore the solder balls 6 become the first, second, and third interconnect components and are solder balls or solder bumps, as claimed in claim 6).
Claim 7
Oyamada with Fu teaches the interconnect structure of claim 1, wherein:
the first layer (Oyamada 11; paragraph 44, 54) is coupled to one of a power terminal, a ground terminal, or a signal terminal; and
the second layer (13; paragraph 44, 54) is coupled to another of the power terminal, the ground terminal, or signal terminal.
Claim 8
Oyamada with Fu teaches the interconnect structure of claim 1, wherein the first layer further comprises a third vertical portion (Oyamada an additional 3G) that extends upward from the first horizontal portion (11), through a fifth opening (12A) within the layer of dielectric material (12) and through a sixth opening (13A) within the second horizontal portion (13).
Claim 9
Oyamada with Fu teaches the interconnect structure of claim 1, wherein the second layer further comprises a third vertical portion (Oyamada an additional 3P) that extends downward from the second horizontal portion (13), through a fifth opening (12A) within the layer of dielectric material (12) and through a sixth opening (11A) within the first horizontal portion (11).
Claim 13
Oyamada with Fu teaches the interconnect structure of claim 1, wherein the conductive material of the first layer is the same as the conductive material of the second layer (Oyamada paragraph 54: copper foil).
Claim 14
Oyamada with Fu teaches the interconnect structure of claim 1, wherein the interconnect structure is included within one of a circuit board, an integrated circuit die, or a carrier substrate of an integrated circuit package (Oyamada paragraph 39).
Claim 19
Oyamada (FIG. 1) discloses a capacitor structure comprising:
a first electrode (11; paragraph 44-45) continuous with a first contact pad (3G);
a second electrode (13; paragraph 44, 47) continuous with a second contact pad (3P); and
a capacitor dielectric (12; paragraph 44, 46) between the first electrode (11) and the second electrode (13), as recited in claim 19.
Oyamada does not expressly disclose the first electrode is monolithic with the first contact pad; and the second electrode is monolithic with the second contact pad, as recited in claim 19.
Fu (FIG. 8-12) teaches a fully additive circuit board processing method resulting in no interface between a horizontal portion (120 and 130) and a vertical portion (113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Fu with Oyamada to incorporate a fully additive process as taught by Fu in the structure taught by Oyamada and thereby have a first electrode, continuous and monolithic with, a first contact pad and a second electrode, continuous and monolithic with, a second contact pad, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for the use of laser processing (Fu paragraph 24, 35) and precise control of a continuous and smooth layer of metal, allowing for avoidance of discontinuities and contamination of boundaries between vias and traces if they were processed at different times.
Claim 20
Oyamada with Fu teaches the capacitor structure of claim 19, wherein:
the first contact pad (Oyamada 3G) comprises a vertical structure that extends through an opening (13A) within the second electrode (13), without making contact with the second electrode (13).
Claims 1-3, 7, 11-12, 14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Saita in view of Fu.
Claim 1
Saita (FIG. 1) discloses an interconnect structure comprising:
a first layer of conductive material comprising (i) a first horizontal portion (21; paragraph 29) extending along a first horizontal plane, with a first opening within the first horizontal portion (21), and (ii) a first vertical portion (51; paragraph 33);
a second layer of conductive material comprising (i) a second horizontal portion (22; paragraph 29) extending along a second horizontal plane, with a second opening within the second horizontal portion (22), and (ii) a second vertical portion (52; paragraph 33); and
a layer of dielectric material (23; paragraph 29) extending along a third horizontal plane between the first and second horizontal portions (21-22), and having third and fourth openings;
wherein the first vertical component (51) extends upward from the first horizontal portion (21), through the third opening within the layer of dielectric material (23) and through the second opening within the second horizontal portion (22); and
wherein the second vertical component (52) extends downward from the second horizontal portion (22), through the fourth opening within the layer of dielectric material (23) and through the first opening within the first horizontal portion (21), as recited in claim 1.
Saita does not expressly disclose wherein one or both of: the first layer is monolithic, such that there is no interface between the first horizontal portion and the first vertical portion; or the second layer is monolithic, such that there is no interface between the second horizontal portion and the second vertical portion, as recited in claim 1.
Fu (FIG. 8-12) teaches a fully additive circuit board processing method resulting in no interface between a horizontal portion (120 and 130) and a vertical portion (113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Fu with Saita to incorporate a fully additive process as taught by Fu in the structure taught by Saita and thereby have one or both of: the first layer monolithic, such that there is no interface between the first horizontal portion and the first vertical portion; or the second layer monolithic, such that there is no interface between the second horizontal portion and the second vertical portion, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for the use of laser processing (Fu paragraph 24, 35) and precise control of a continuous and smooth layer of metal, allowing for avoidance of discontinuities and contamination of boundaries between vias and traces if they were processed at different times.
Claim 2
Saita with Fu teaches the interconnect structure of claim 1, wherein:
at least a section of the first horizontal portion (Saita 21) provides a first capacitor electrode, at least a section of the second horizontal portion (22) provides a second capacitor electrode, and at least a section of the layer of dielectric material (23) provides a capacitor dielectric; and
the first capacitor electrode, the second capacitor electrode, and the capacitor dielectric provide a capacitor (20; paragraph 29).
Claim 3
Saita with Fu teaches the interconnect structure of claim 1, further comprising:
a first interconnect component (Saita 4; paragraph 31) coupled to an upper surface of the first vertical portion (51); and
a second interconnect component (4) coupled to an upper surface of the second horizontal portion (22).
Claim 7
Saita with Fu teaches the interconnect structure of claim 1, wherein:
the first layer is coupled to one of a power terminal, a ground terminal, or a signal terminal (Saita paragraph 33); and
the second layer is coupled to another of the power terminal, the ground terminal, or signal terminal (paragraph 33).
Claim 11
Saita with Fu teaches the interconnect structure of claim 1, wherein:
the first layer of conductive material comprises a third horizontal portion (Saita conductive layer 42 along bottom of core substrate 10) extending along a fourth horizontal plane that is different from the first, second, and third horizontal planes, with a fifth opening within the third horizontal portion (for 52);
the second layer of conductive material comprises a fourth horizontal portion (conductive layer along top of core substrate 10) extending along a fifth horizontal plane that is different from the first, second, third, and fourth horizontal planes, with a sixth opening within the fourth horizontal portion (for 51); and
the interconnect structure further comprises another layer of dielectric material (10; paragraph 27) extending along a sixth horizontal plane between the third and fourth horizontal portions (as shown in FIG. 1, paragraph 33: power and ground planes on opposite sides of core substate 10; alternatively, see paragraph 80: embodiment with multiple of each of 21-23).
Claim 12
Saita with Fu teaches the interconnect structure of claim 1, wherein the conductive material of the first layer is elementally different from the conductive material of the second layer (Saita paragraph 44).
Claim 14
Saita with Fu teaches the interconnect structure of claim 1, wherein the interconnect structure is included within one of a circuit board, an integrated circuit die, or a carrier substrate of an integrated circuit package (Saita paragraph 24-26).
Claim 19
Saita (FIG. 1) discloses a capacitor structure comprising:
a first electrode (21; paragraph 29) continuous with a first contact pad (51; paragraph 33);
a second electrode (22; paragraph 29) continuous with a second contact pad (52; paragraph 33); and
a capacitor dielectric (23; paragraph 29) between the first electrode (21) and the second electrode (22), as recited in claim 19.
Saita does not expressly disclose the first electrode is monolithic with the first contact pad; and the second electrode is monolithic with the second contact pad, as recited in claim 19.
Fu (FIG. 8-12) teaches a fully additive circuit board processing method resulting in no interface between a horizontal portion (120 and 130) and a vertical portion (113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Fu with Saita to incorporate a fully additive process as taught by Fu in the structure taught by Saita and thereby have a first electrode, continuous and monolithic with, a first contact pad and a second electrode, continuous and monolithic with, a second contact pad, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for the use of laser processing (Fu paragraph 24, 35) and precise control of a continuous and smooth layer of metal, allowing for avoidance of discontinuities and contamination of boundaries between vias and traces if they were processed at different times.
Claim 20
Saita with Fu teaches the capacitor structure of claim 19, wherein:
the first contact pad (Saita 51) comprises a vertical structure that extends through an opening within the second electrode (22), without making contact with the second electrode (22).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571) 270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN MILAKOVICH/Primary Examiner, Art Unit 2847