Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is an AIA application filed June 28, 2023.
The earliest effective filing date of this AIA application is seen as June 28, 2023, the actual filing date, there being no earlier priority applications.
The claims originally filed June 28, 2023 are entered, currently outstanding, and subject to examination.
This action is in response to the updated application data sheet/ADS filing of December 9, 2025.
Claims 1-20 are currently pending and outstanding.
No claims have been amended, cancelled, withdrawn, or added.
Claims 1-20 are currently outstanding and subject to examination.
This is a non-final action and is the first action on the merits.
Allowable subject matter is not indicated below.
Often, in the substance of the action below, formal matters are addressed first, claim rejections second, and any response to arguments third.
Special Definitions for Claim Language - MPEP § 2111.01(IV)
No special definitions are seen as present in the specification regarding the language used in the claims. Consequently, the words and phrases of the claims are given their plain meaning. MPEP §§ 2173.01, 2173.05(a), and 2111.01.
If special definitions are present, Applicant should bring those to the attention of the examiner and the prosecution history with its next response in a manner both specific and particular. In doing so, there will be no mistake, confusion, and/or ambiguity as to what constitutes the special definition(s).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5-7, 11, and 13-16 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 20230367087 of Mayukh et al. (Mayukh).
With respect to claim 1, Mayukh discloses an integrated circuit package (Fig. 3, semiconductor package 300, ¶¶ 34-37 inter alia) comprising:
a first package substrate (core 210);
a photonics integrated circuit (PIC) die (PIC 320) coupled to the first package substrate at an edge of the first package substrate (per the surfaces adjacent PIC 320);
a second package substrate (lower substrate 305) coupled to a bottom side of the first package substrate (310); and
a pedestal (right half of portion of 210 below FOC 330b) coupled to a top side of the second package substrate (305) in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die (320) is located (per Fig. 3).
With respect to claim 2, Mayukh as set forth above discloses the integrated circuit package of claim 1, including one wherein
the pedestal is a first pedestal, and
the integrated circuit package further comprises a second pedestal (left half of portion of 210 below FOC 330b) coupled to the top side of the second package substrate (305) in an area of the second package substrate that extends beyond the edge of the first package substrate (310) at which the PIC die (320) is located.
With respect to claim 5, Mayukh as set forth above discloses the integrated circuit package of claim 1, including one wherein
the first package substrate (310) comprises a cutout region (surrounding PIC 320) and the PIC die (320) is located at an edge defining cutout region (PER Fig. 3).
With respect to claim 6, Mayukh as set forth above discloses the integrated circuit package of claim 1, including one wherein
the PIC die (320) is within a cavity in a top side of the first package substrate (310).
Per Fig. 3.
With respect to claim 7, Mayukh as set forth above discloses the integrated circuit package of claim 1, including one further comprising
an electronic integrated circuit (EIC) die (EIC 325) coupled to the first package substrate (310) and connected to the PIC die (320, ¶ 37, "In various embodiments, the EIC 325 may be coupled to the PIC 320 using one or more vias in the substrate 305.").
With respect to claim 11, Mayukh as set forth above discloses a system comprising:
an integrated circuit package comprising:
a first package substrate;
a photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate;
a second package substrate coupled to a bottom side of the first package substrate; and
a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located (for the foregoing, see claim 1, above); and
optical fiber (via fiber optic couplers (FOCs) 330b) coupled to the PIC and on a top surface of the pedestal (per Fig. 3).
With respect to claim 13, Mayukh as set forth above discloses the system of claim 11, including one wherein
the pedestal is a first pedestal, and
the system further comprises a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the PIC die is located, and
wherein the optical fiber is further on a top surface of the second pedestal.
Per claim 2, above.
With respect to claim 14, Mayukh as set forth above discloses the system of claim 11, including one wherein
the first package substrate comprises a cutout region and the PIC die is located at an edge defining cutout region.
Per claim 5, above.
With respect to claim 15, Mayukh as set forth above discloses the system of claim 11, including one wherein
the PIC die is within a cavity in a top side of the first package substrate.
Per claim 6, above.
With respect to claim 16, Mayukh as set forth above discloses the system of claim 11, including one further comprising
an electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die.
Per claim 7, above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 4, 8-10, 12, and 17-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Mayukh as set forth above in view of legal precedent.
With respect to claim 3, Mayukh as set forth above discloses the integrated circuit package of claim 2, but not one wherein
the first pedestal and second pedestal comprise different materials.
The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination.
Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol. “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle.” 325 U.S. at 335, 65 USPQ at 301.).
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.). MPEP § 2144.07.
Consequently, the recitation of specific materials is seen as obvious.
For example, the first pedestal may be made of a conductor, such as a metal, in order to provide an electrical ground. The second pedestal may be made of a dielectric, such as glass, in order to provide an insulator or other electrical separation.
With respect to claim 4, Mayukh as set forth above discloses the integrated circuit package of claim 1, wherein the pedestal comprises glass or metal.
The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination.
Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol. “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle.” 325 U.S. at 335, 65 USPQ at 301.).
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.). MPEP § 2144.07.
Consequently, the recitation of specific materials is seen as obvious.
For example, the first may be made of a conductor, such as a metal, in order to provide an electrical ground. The pedestal might alternatively be made of a dielectric, such as glass, in order to provide an insulator or other electrical separation.
With respect to claim 8, Mayukh as set forth above discloses the integrated circuit package of claim 1, but not one further comprising
a processor coupled to the first package substrate and connected to the EIC die.
Mayukh ¶ 54 provides:
"For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and/or any combination thereof."
The disclosure of "custom integrated circuits (ICs), programmable logic, and/or any combination thereof" is seen to include “processors”.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to couple a processor optically to the first package substrate (310) along the lines of ¶ 54 in a system according to Mayukh as set forth above in order to provide optical communication between different components and to provide signal and/or data processing. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optoelectronic system) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
a processor coupled to the first package substrate and connected to the EIC die.
With respect to claim 9, Mayukh as set forth above discloses the integrated circuit package of claim 1, but not one wherein
the second package substrate comprises vias connected between electrical connection pads on a top side of the second package substrate and electrical connection pads on a bottom side of the second package substrate.
¶ 22 provides:
"In various embodiments, the semiconductor package 100 includes interposer 105, which may further include core 110, copper (Cu) traces 115, and one or more through-hole vias, also referred to as “vias,” 150a, 150b. Each of the vias 150a, 150b may respectively include via walls 120 defining a via hole 125, and via pads through which the vias may be electrically coupled (e.g., to other components or to Cu trace 115). Moreover, each via 150a, 150b may respectively include a waveguide 135 positioned inside via hole 125, and optically coupled to the photonics IC 140."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use vias and pads along the lines of ¶ 22 in a system according to Mayukh as set forth above in order to electrical communication between components. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optoelectronic system) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the second package substrate comprises vias connected between electrical connection pads on a top side of the second package substrate and electrical connection pads on a bottom side of the second package substrate.
With respect to claim 10, Mayukh as set forth above discloses the integrated circuit package of claim 1, but not one wherein
the second package substrate (305) comprises one or more of redistribution layer traces and fan-out traces.
¶ 22 provides:
"In various embodiments, the semiconductor package 100 includes interposer 105, which may further include core 110, copper (Cu) traces 115, and one or more through-hole vias, also referred to as “vias,” 150a, 150b. Each of the vias 150a, 150b may respectively include via walls 120 defining a via hole 125, and via pads through which the vias may be electrically coupled (e.g., to other components or to Cu trace 115). Moreover, each via 150a, 150b may respectively include a waveguide 135 positioned inside via hole 125, and optically coupled to the photonics IC 140."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use traces and other conductors along the lines of ¶ 22 in a system according to Mayukh as set forth above in order to electrical communication between components. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optoelectronic system) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the second package substrate (305) comprises one or more of redistribution layer traces and fan-out traces.
See also ¶ 31 where it provides:
In the embodiments depicted, the substrate 205 may be an organic flip-chip substrate, redistribution layer (RDL), or printed circuit board (PCB) having one or more internal routing layers. Routing layers may include any layer configured to provide component interconnects. For example, routing layers are layers of the substrate through which interconnections may be established between components. Connections may be routed, for example, through copper pads, copper/metal traces deposited on/in the substrate layer, and through-hole vias, or other suitable interconnects.
With respect to claim 12, Mayukh as set forth above discloses the system of claim 11, but not one wherein
the optical fiber is adhesively coupled to the pedestal.
¶ 40 provides "In yet further examples, modules like the PIC 420 and/or FOC 430 may be coupled to the interposer 410 via adhesive, molding, or other bonding techniques."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use adhesive bonding along the lines of ¶ 40 in a system according to Mayukh as set forth above in order to secure components, including optical fibers. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optoelectronic system) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the optical fiber is adhesively coupled to the pedestal.
With respect to claim 17, Mayukh as set forth above discloses the system of claim 11, but not one further comprising
a circuit board,
wherein the second package is coupled to a top side of the circuit board.
¶ 31 provides that "In the embodiments depicted, the substrate 205 may be an organic flip-chip substrate, redistribution layer (RDL), or printed circuit board (PCB) having one or more internal routing layers."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a circuit board for internal routing along the lines of ¶ 31 in a system according to Mayukh as set forth above in order to provide additional signal and/or power pathways. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optoelectronic system) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
a circuit board,
wherein the second package is coupled to a top side of the circuit board.
With respect to claim 18, Mayukh as set forth above discloses a system comprising:
a circuit board (per claim 17);
an integrated circuit package coupled to the circuit board, the integrated circuit package comprising:
a first package substrate (claim 1);
a first photonics integrated circuit (PIC) die coupled to the first package substrate at an edge of the first package substrate (claim 1);
a first electronic integrated circuit (EIC) die coupled to the first package substrate and connected to the PIC die (claim 7);
a second PIC die coupled to the first package substrate at the edge of the first package substrate (duplication of parts, below);
a second EIC die coupled to the first package substrate and connected to the PIC die (duplication of parts, below);
a processor coupled to the first EIC die and the second EIC die (per claim 8, above, and duplication of parts);
a second package substrate coupled to a top side of the circuit board and to a bottom side of the first package substrate (per claims 1 and 17); and
a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located (per claim 1);
a first fiber array unit (FAU) coupled to the first PIC and on a top surface of the pedestal (FOC 330b, Fig. 3); and
a second FAU coupled to the second PIC and on the top surface of the pedestal (duplication of parts).
Mere duplication of parts has no distinguishing significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP § 2144.04(VI)(B).
Duplicating additional elements to add additional features that are the same as existing ones is seen as a duplication of parts.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include additional similarly-operating elements in the same known was as a duplication of parts in a system according to Mayukh as set forth above in order to provide additional capacity. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the references) to yield predictable results (an optoelectronic system) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
a second PIC die coupled to the first package substrate at the edge of the first package substrate (duplication of parts, below);
a second EIC die coupled to the first package substrate and connected to the PIC die (duplication of parts, below);
a processor coupled to the first EIC die and the second EIC die (per claim 8, above, and duplication of parts); and
a second FAU coupled to the second PIC and on the top surface of the pedestal (duplication of parts).
With respect to claim 19, Mayukh as set forth above discloses the system of claim 18, including one wherein
the pedestal is a first pedestal,
the system further comprises
a second pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located (per claim 2, above), and
wherein one of the first FAU or the second FAU are on a top surface of the second pedestal (per Fig. 3 and duplication of parts).
With respect to claim 20, Mayukh as set forth above discloses the system of claim 19, but not one further comprising
a third pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located (duplication of parts),
wherein the first FAU is on the top surface of the second pedestal and the second FAU is on a top surface of the third pedestal (duplication of parts).
Rearrangement of specific elements shown in Mayukh are not seen to be beyond the knowledge/skill of the person of ordinary skill in the art before the effective filing date of the claimed invention. As such, the subject matter of claim 20 is seen to be obvious.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use pedestals for FAU/FOC support along the lines of Mayukh in a system according to Mayukh as set forth above in order to provide additional capacity and securement for connection elements. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), prior art elements (listed above) are combined according to known methods (per the reference) to yield predictable results (an optoelectronic system) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
a third pedestal coupled to the top side of the second package substrate in an area of the second package substrate that extends beyond the edge of the first package substrate at which the first PIC die and second PIC die are located (duplication of parts),
wherein the first FAU is on the top surface of the second pedestal and the second FAU is on a top surface of the third pedestal (duplication of parts).
Conclusion
Applicant’s publication US 20250004206 A1 published January 2, 2025 is cited.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited references have elements related to Applicant’s disclosure and/or claims or are otherwise associated with the other cited references, particularly with respect to optoelectronic circuit systems and the like.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW JORDAN whose telephone number is (571) 270-1571. The examiner can normally be reached most days 1000-1800 PACIFIC TIME ZONE (messages are returned).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. While examiner does not examine over the phone (see 37 C.F.R. § 1.2), examiner is glad to clarify or discuss issues so long as it forwards prosecution.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas (Tom) HOLLWEG can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andrew Jordan/
Primary Examiner, Art Unit 2874
V: (571) 270-1571 (Pacific time)
F: (571) 270-2571
August 30, 2026
Prosecution Insights