Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10 – 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Osanai et al (US 2002/0084492 A1 – hereafter “Osanai”) in view of Wong et al. (US 2024/0421074 A1 – hereafter “Wong”).
As per claim 1, Osanai teaches:
An electronic device (see para [0607]), comprising:
a well region having a first conductivity type extending into a semiconductor substrate layer having an opposite second conductivity type (see para [0607]);
and first and second terminals connected to the well region a separated by a resistive portion of the well region (see para [0607]);
and a thin-film bias resistor conductively connected to the first terminal (see para [0607], [0760], [0744]), the bias resistor formed in a region of the substrate conductively isolated from the n-well region (see para [0607], [0648]). However, Osanai does not explicitly teach the well resistor is configured or used as a thermistor for sensing temperature.
Wong teaches thermistors integrated within semiconductor devices, including thin film resistor structures having defined temperature coefficients of resistance for temperature dependent operation (see para [0025]).
It would have been obvious to a person of ordinary skill in the art before the
effective filing date of the instant application to modify Osanai in view of Wong to use the well resistor structure of Osanai as a thermistor in order to implement temperature dependent operation within a semiconductor device, as expressly taught by Wong, which discloses resistors integrated in semiconductor devices for thermistor applications.
Regarding claim 10, the claim recites “The electronic device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.”
Osanai teaches a well region of a first conductivity type formed in a substrate layer of an opposite second conductivity type, including an n-type well formed on a p-type substrate (see para [0607], [0648]).
It would have been obvious to a person of ordinary skill in the art before the
effective filing date of the instant application to modify Osanai in view of Wong to employ the disclosed n-type well and p-type substrate configuration in order to implement a thermistor structure consistent with conventional CMOS fabrication techniques.
As per claim 11, Osanai teaches the following:
A method of fabricating an electronic device (see para [0607]), comprising:
the thermistor including a well region having a first conductivity type and extending into a substrate layer having a different second conductivity type (see para [0607]);
and forming a thin-film bias resistor over a dielectric layer over the substrate (see para [0607], [0760], [0744]), the bias resistor conductively connected to a terminal of the thermistor (see para [0607], [0648]). However, Osanai does not explicitly teach the well resistor is configured or used as a thermistor for sensing temperature.
Wong teaches thermistors integrated within semiconductor devices, including thin film resistor structures having defined temperature coefficients of resistance for temperature dependent operation (see para [0025]).
It would have been obvious to a person of ordinary skill in the art before the
effective filing date of the instant application to modify Osanai in view of Wong to form the well resistor of Osanai as a thermistor in order to implement temperature dependent operation within the fabricated semiconductor device, as expressly taught by Wong, which discloses resistors integrated in semiconductor devices for thermistor applications.
Regarding claim 20, the claim recites “The method of claim 11, wherein the first conductivity type is n-type and the second conductivity type is p-type.”
Osanai teaches a well region of a first conductivity type formed in a substrate layer of an opposite second conductivity type, including an n-type well formed on a p-type substrate (see para [0607], [0648]).
It would have been obvious to a person of ordinary skill in the art before the
effective filing date of the instant application to modify Osanai in view of Wong to employ the disclosed n-type well and p-type substrate configuration in order to implement a thermistor structure consistent with conventional CMOS fabrication techniques.
Claims 4, 5, 8, 14, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Osanai in view of Wong in further view of Kato et al. (US 2006/0065949 A1 – hereafter “Kato”).
Regarding claim 4, the claim recites “The electronic device of claim 1, wherein the bias resistor comprises a metal-silicon alloy.”
Osanai in view of Wong does not teach the bias resistor comprises a metal-silicon alloy.
Kato teaches a CrSi (silicon-chromium) thin film resistor formed as a metal-silicon alloy (see para [0267]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Kato to form the bias resistor as a metal-silicon alloy thin film, such as CrSi, in order to provide a resistor material having controlled sheet resistance and stable electrical characteristics.
Regarding claim 5, the claim recites “The electronic device of claim 1, wherein the first and second terminals include a first metal silicide and the bias resistor comprises a different second metal silicide.”
Osanai in view of Wong teaches terminals including a metal silicide and teaches a bias resistor that may be formed of a metal silicide; however, does not teach the first and second terminals include a first metal silicide and the bias resistor comprises a different second metal silicide.
Kato teaches a CrSi metal-silicon alloy thin film resistor (see para [0267]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Kato to form the bias resistor from a metal silicide different from the metal silicide used in the terminals, such as forming the terminals of tungsten silicide as taught by Osanai and forming the bias resistor of chromium silicide as taught by Kato, in order to independently optimize the electrical conductivity of the terminals and the sheet resistance and temperature characteristics of the bias resistor.
Regarding claim 8, the claim recites “The electronic device of claim 1, wherein the bias resistor includes a silicon-chromium (SiCr) film having a thickness of ranging from about 3 nm to about 4 nm.”
Osanai in view of Wong does not teach the bias resistor includes a silicon-chromium (SiCr) film having a thickness of ranging from about 3 nm to about 4 nm.
Kato teaches a CrSi thin film resistor having a thickness ranging from 2.5 nm to 50 nm (see para [0267]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Kato to form the bias resistor as a silicon-chromium thin film having a thickness within the taught range, including 3 – 4 nm, in order to achieve controlled sheet resistance and miniaturization.
Regarding claim 14, the claim recites “The method of claim 11, wherein the bias resistor comprises a metal-silicon alloy.”
Osanai in view of Wong does not teach the bias resistor comprises a metal-silicon alloy.
Kato teaches a CrSi (silicon-chromium) thin film resistor formed as a metal-silicon alloy (see para [0267]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Kato to form the bias resistor as a metal-silicon alloy thin film, such as CrSi, in order to provide a resistor material having controlled sheet resistance and stable electrical characteristics.
Regarding claim 15, the claim recites “The method of claim 11, wherein the terminal includes a first metal silicide and the bias resistor comprises a different second metal silicide.”
Osanai in view of Wong teaches terminals including a metal silicide and teaches a bias resistor that may be formed of a metal silicide; however, does not teach the first and second terminals include a first metal silicide and the bias resistor comprises a different second metal silicide.
Kato teaches a CrSi metal-silicon alloy thin film resistor (see para [0267]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Kato to form the bias resistor from a metal silicide different from the metal silicide used in the terminals, such as forming the terminals of tungsten silicide as taught by Osanai and forming the bias resistor of chromium silicide as taught by Kato, in order to independently optimize the electrical conductivity of the terminals and the sheet resistance and temperature characteristics of the bias resistor.
Regarding claim 18, the claim recites “The method as recited in claim 11, wherein the bias resistor includes a silicon-chromium (SiCr) film having a thickness of ranging from about 3 nm to about 4 nm.
Osanai in view of Wong does not teach the bias resistor includes a silicon-chromium (SiCr) film having a thickness of ranging from about 3 nm to about 4 nm.
Kato teaches a CrSi thin film resistor having a thickness ranging from 2.5 nm to 50 nm (see para [0267]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Kato to form the bias resistor as a silicon-chromium thin film having a thickness within the taught range, including 3 – 4 nm, in order to achieve controlled sheet resistance and miniaturization.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Osanai in view of Wong in further view of Huang et al. (US 2021/0335991 A1 – hereafter “Huang”).
Regarding claim 6, the claim recites “The electronic device of claim 1, wherein the bias resistor is located directly over a shallow trench isolation (STI) structure.”
Osanai in view of Wong does not teach the bias resistor is located directly over a shallow trench isolation (STI) structure.
Huang teaches a resistor circuit formed on a shallow trench isolation region, wherein metal resistor structures overlap the STI region and the resistor circuit is formed on the STI region (see para [0139], [0141] and [0145]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Huang to locate the bias resistor directly over a STI structure as taught by Huang in order to provide electrical isolation of the resistor from active regions of the substrate and to reduce parasitic coupling.
Regarding claim 16, the claim recites “The method of claim 11, wherein the bias resistor is located directly on a shallow trench isolation (STI) structure.”
Osanai in view of Wong does not teach the bias resistor is located directly on a shallow trench isolation (STI) structure.
Huang teaches a resistor circuit formed on a shallow trench isolation region, wherein metal resistor structures overlap the STI region and the resistor circuit is formed on the STI region (see para [0139], [0141] and [0145]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Huang to locate the bias resistor directly over a STI structure as taught by Huang in order to provide electrical isolation of the resistor from active regions of the substrate and to reduce parasitic coupling.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Osanai in view of Wong in further view of Sun et al. (US 2014/0159180 A1– hereafter “Sun”).
Regarding claim 9, the claim recites “The electronic device of claim 1, wherein the substrate layer is an epitaxial layer.” Osanai in view of Wong does not teach the substrate layer is an epitaxial layer.
Sun teaches a thin epitaxial silicon layer forming the substrate (see para [0105]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Sun to form the substrate layer as an epitaxial layer as taught by Sun in order to provide improved control of doping profiles and device characteristics.
Regarding claim 19, the claim recites “The electronic device of claim 11, wherein the substrate layer is an epitaxial layer.” Osanai in view of Wong does not teach the substrate layer is an epitaxial layer.
Sun teaches a thin epitaxial silicon layer forming the substrate (see para [0105]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the instant application to modify Osanai in view of Wong in further view of Sun to form the substrate layer as an epitaxial layer as taught by Sun in order to provide improved control of doping profiles and device characteristics.
Allowable Subject Matter
Claims 2 – 3, 7, 12 – 13, 17 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/MANUEL SALVADOR CASTELLON JR/Examiner, Art Unit 2855
/JOHN E BREENE/Supervisory Patent Examiner, Art Unit 2855