DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 03/17/2026 has been entered. Applicant’s amendments to the Specification and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed 12/19/2025.
Response to Arguments
Applicant's arguments filed 03/17/2026 have been fully considered but they are not persuasive. The claim language does not explicitly state that the first and second bias signals have different bias values. The primary art by Bao teaches that the bias voltage applied to the third and fourth transistors can be variable, resulting in different operating modes. See the rejection below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 12, and 18 recites the limitation "the first gain mode or the second gain mode" in the last limitation of each claim. There is insufficient antecedent basis for this limitation in the claim. A first and a second gain mode have not been previously defined in the claim. Appropriate correction is required. Claims 2-11, 13-17, and 19-20 inherit these rejections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 117792295 by Bao.
Regarding claim 1, Bao teaches an amplifier comprising:
a first transistor (Fig. 2 NM1p) and a second transistor (Fig. 2 NM1n) to which differential input signals of a differential input signal pair are applied to gate terminals thereof (Fig. 2 INp and Inn), respectively;
a third transistor (Fig. 2 NP2p) having a first end (source) connected to the first transistor (NM1p), a gate terminal receiving a first bias signal (VC_1), and a second end (Drain) outputting a first differential output signal of a differential output signal pair (OUTp);
a fourth transistor (Fig 2 MN2n) having a first end (source) connected to the second transistor (MN1n), a gate terminal receiving a second bias signal (VC_1; the claim language does not indicate that the first and second bias signals must be different from each other), and a second end outputting a second differential output signal of the differential output signal pair (OUTn); and
a pair of capacitors (Fig. 2 Ccp and Ccn) coupled to the third transistor (NM2p) and the fourth transistor (NM2n), and having a cross-coupled structure with respect to each other,
wherein the first bias signal and the second bias signal are defined to operate amplifier in the first gain mode or the second gain mode (Par. 38 of the previously provided translation notes that the bias voltage VC_1 which is applied to the third and fourth transistor gates can vary. One of the main reasons to vary the bias voltage is to change the gain and linearity, and it’s obvious to a person of ordinary skill in the art that varying the bias voltage would result in different modes of gain (such as high or low)).
Regarding claim 2, Bao teaches the amplifier of claim 1, wherein the pair of capacitors includes:
a first capacitor (Fig. 2 Ccn) having a first end connected to the second end (drain) of the fourth transistor (NM2n) and having a second end connected to the first end (source) of the third transistor (NM2p); and
a second capacitor (Fig. 2 Ccp) having a first end connected to the second end (drain) of the third transistor (NM2p) and a second end connected to the first end (source) of the fourth transistor (NM2n).
Regarding claim 3, Bao teaches the amplifier of claim 2, wherein: the first capacitor cancels a parasitic capacitance component of the fourth transistor, and the second capacitor cancels a parasitic capacitance component of the third transistor (Par. 19; it is evident by knowing the circuit topology that one can conclude or infer that the purpose of the cross coupled capacitors is to cancel parasitic capacitance and improve linearity).
Regarding claim 4, Bao teaches the amplifier of claim 2 wherein a capacitance of the first capacitor has a value depending on a size of the fourth transistor, and wherein a capacitance of the second capacitor has a value depending on a size of the third transistor (Par. 41).
Regarding claim 5, Bao teaches the amplifier of claim 1, wherein a resistance component of an output impedance defined at the second end of the third transistor and the second end of the fourth transistor has a positive value (It is known in the art of amplifiers that the load resistance has to be positive in order to avoid oscillation).
Regarding claim 6, Bao teaches the amplifier of claim 1, wherein:
the pair of capacitors (Fig. 2 Ccp and Ccn) cancels parasitic capacitance components of the third and fourth transistors when the first through fourth transistors are turned on (Par. 19); and
the pair of capacitors cancels parasitic capacitance components of the third and fourth transistors when the first through fourth transistors are turned off (While not explicitly stated, the pair of capacitors Ccp and Ccn are designed to cancel the parasitic capacitance of the cascode transistors regardless of whether they are on or off).
Regarding claim 7, Bao teaches the amplifier of claim 1, but fails to teach that the first through fourth transistors are each an NMOS transistor. Only NM1n and NM2n are. However, this is simply design engineering, and it would be easy to a person of ordinary skill in the art to substitute the transistors in this circuit with NMOS transistors. Different transistor types are known in the art and US 20230179162 by Mehr et al. teaches a similar differential cascode arrangement where each transistors is an NMOS transistor (Mehr Par. 19).
Regarding claim 8, Bao teaches the amplifier of claim 7, wherein:
a first end of a first capacitor (Fig. 2 Ccn) of the pair of capacitors is connected to a drain of the fourth transistor (NM2n) and the other end of the first capacitor is connected to a source of the third transistor (NM2p), and
a first end of a second capacitor (Fig. 2 Ccp) of the pair of capacitors is connected to a drain of the third transistor (NM2p) and the other end of the second capacitor is connected to a source of the fourth transistor (NM2n).
Regarding claim 9, Bao teaches the amplifier of claim 7, wherein:
a drain of the first transistor (Fig. 2 NM1p) is connected to a source of the third transistor (NM2p), and
a drain terminal of the second transistor (NM1n) is connected to a source of the fourth transistor (NM2n).
Regarding claim 10, Bao teaches the amplifier of claim 1, but doesn’t explicitly mention the sizes of the first to fourth transistors. However, this is simply design engineering and a person of ordinary skill in the art would be able to adjust the sizes of the transistors based on the needs of the circuit. This is known in the art, as shown in teaching reference US 20160164468 by Nobbe et al., which states in par. 114 that a cascode arrangement of transistors can be of different sizes.
Regarding claim 11, Bao teaches the amplifier of claim 3, wherein a current flowing through the first capacitor (fig. 2 Ccn) and a leakage current according to a parasitic capacitance component of the fourth transistor (Fig. 2 NM2n) have opposite polarities (Par. 19), and
a current flowing through the second capacitor (Fig. 2 Ccp) and a leakage current according to a parasitic capacitance component of the third transistor (Fig. 2 NM2p) have opposite polarities (Par. 19).
Regarding claim 12, Bao teaches an amplifier comprising:
a first transistor (Fig. 2 NM1p) and a second transistor (Fig. 2 NM1n) to which differential input signals of a differential input signal pair are applied to gate terminals thereof (Fig. 2 INp and Inn), respectively,
a third transistor (Fig. 2 NP2p) having a first end (source) connected to the first transistor (NM1p), a gate terminal receiving a bias signal (VC_1), and a second end (Drain) outputting a first differential output signal of a differential output signal pair (OUTp);
a fourth transistor (Fig 2 MN2n) having a first end (source) connected to the second transistor (MN1n), a gate terminal receiving a second bias signal (VC_1; the claim language does not indicate that the first and second bias signals must be different from each other), and a second end outputting a second differential output signal of the differential output signal pair (OUTn); and
a pair of capacitors (Fig. 2 Ccp and Ccn) coupled to the third transistor (NM2p) and the fourth transistor (NM2n), and having a cross-coupled structure with respect to each other,
wherein the first bias signal and the second bias signal are defined to operate amplifier in the first gain mode or the second gain mode (Par. 38 of the previously provided translation notes that the bias voltage VC_1 which is applied to the third and fourth transistor gates can vary. One of the main reasons to vary the bias voltage is to change the gain and linearity, and it’s obvious to a person of ordinary skill in the art that varying the bias voltage would result in different modes of gain (such as high or low)).
Bao fails to teach a multi-stage amplifier comprising a plurality of amplifiers connected in parallel to each other through input nodes and output nodes.
However, multi-stage parallel amplifiers are known in the art, as shown in US 20230283316 Fig. 7 and par. 48 and a person having ordinary skill in the art would be able to implement the structure of Bao in a multi-stage parallel circuit in order to vary gain.
Regarding claim 13, Bao teaches the multi-stage amplifier of claim 12, wherein the pair of capacitors includes:
a first capacitor (Fig. 2 Ccn) having a first end connected to the second end (drain) of the fourth transistor (NM2n) and having a second end connected to the first end (source) of the third transistor (NM2p); and
a second capacitor (Fig. 2 Ccp) having a first end connected to the second end (drain) of the third transistor (NM2p) and a second end connected to the first end (source) of the fourth transistor (NM2n).
Regarding claim 14, Bao teaches the amplifier of claim 13, wherein: the first capacitor cancels a parasitic capacitance component of the fourth transistor, and the second capacitor cancels a parasitic capacitance component of the third transistor (Par. 19; it is evident by knowing the circuit topology that one can conclude or infer that the purpose of the cross coupled capacitors is to cancel parasitic capacitance and improve linearity).
Regarding claim 15, Bao teaches the multi-stage amplifier of claim 12, wherein each of the first and second bias signals (Vc_1) turns on or turns off at least one amplifier among the plurality of amplifiers (It is known in the art that bias signals turn amplifiers on and off).
Regarding claim 16, Bao teaches the multi-stage amplifier of claim 15, wherein the pair of capacitors cancels parasitic capacitance components generated when the first transistor, the second transistor, the third transistor, and the fourth transistor are turned off (while not explicitly stated, the pair of capacitors Ccp and Ccn are designed to cancel the parasitic capacitance of the cascode transistors regardless of whether they are on or off) according to the first bias signal and/or the second bias signal (It is known in the art that bias signals turn amplifiers on an off).
Regarding claim 17, Bao teaches the multi-stage amplifier of claim 13, wherein a capacitance of the first capacitor has a value depending on a size of the fourth transistor, and wherein a capacitance of the second capacitor has a value depending on a size of the third transistor (Par. 41).
Regarding claim 18, Bao teaches a wireless communication device comprising (“Technical Field”):
a processor (RF amplifiers have processors); and
a radio frequency (RF) chip configured to generate an RF signal based on a baseband signal received from the processor, and to adjust a gain of the RF signal through an amplifier to output an adjusted RF signal (Fig. 1-5; Par. 5-6; “Background Art”), and
wherein the amplifier includes:
a first transistor (Fig. 2 NM1p) and a second transistor (NM1n) to which the RF signal is applied to respective gate terminals thereof (INp and Inn);
a third transistor (Fig. 2 NP2p) having a first end (source) connected to the first transistor (NM1p), a gate terminal receiving a bias signal (VC_1), and a second end (Drain) outputting a first differential output signal of a differential output signal pair (OUTp);
a fourth transistor (Fig 2 MN2n) having a first end (source) connected to the second transistor (MN1n), a gate terminal receiving a second bias signal (VC_1; the claim language does not indicate that the first and second bias signals must be different from each other), and a second end outputting a second differential output signal of the differential output signal pair (OUTn); and
a pair of capacitors (Fig. 2 Ccp and Ccn) coupled to the third transistor (NM2p) and the fourth transistor (NM2n), and having a cross-coupled structure with respect to each other,
wherein the first bias signal and the second bias signal are defined to operate amplifier in the first gain mode or the second gain mode (Par. 38 of the previously provided translation notes that the bias voltage VC_1 which is applied to the third and fourth transistor gates can vary. One of the main reasons to vary the bias voltage is to change the gain and linearity, and it’s obvious to a person of ordinary skill in the art that varying the bias voltage would result in different modes of gain (such as high or low)).
Regarding claim 19, Bao teaches the wireless communication device of claim 18, wherein the pair of capacitors includes:
a first capacitor (Fig. 2 Ccn) having a first end connected to the second end (drain) of the fourth transistor (NM2n) and having a second end connected to the first end (source) of the third transistor (NM2p); and
a second capacitor (Fig. 2 Ccp) having a first end connected to the second end (drain) of the third transistor (NM2p) and a second end connected to the first end (source) of the fourth transistor (NM2n), and
wherein the first capacitor cancels a parasitic capacitance component of the fourth transistor, and the second capacitor cancels a parasitic capacitance component of the third transistor (Par. 19; it is evident by knowing the circuit topology that one can conclude or infer that the purpose of the cross coupled capacitors is to cancel parasitic capacitance and improve linearity).
Regarding claim 20, Bao teaches the amplifier of claim 19, wherein a capacitance of the first capacitor has a value depending on a size of the fourth transistor, and wherein a capacitance of the second capacitor has a value depending on a size of the third transistor (Par. 41).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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