DETAILED ACTION
1. This action is in response to the RCE filed on 4/1/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/1/26 has been entered.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-3, 7-9, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20050024129) in view of Iwata wt al. (US 20160299518).
Regarding claim 1: Jang disclsoes (i.e. figures 6-10) a circuit comprising:
a power supply node (i.e. node of VDD);
a reference node (i.e. node of Vss);
an output node (i.e. node of Vref);
a first transistor (i.e. MP9) coupled (i.e. electrically coupled) between the power supply (i.e. node of VDD) and output nodes (i.e. node of Vref);
an amplifier (i.e. amplifier of 300) comprising:
a non-inverting input (i.e. + input);
an inverting input (i.e. - input) coupled (i.e. electrically coupled) to the reference node (i.e. node of Vss) through a second passive device (i.e. R2_8); and
an output (i.e. output of amplifier 300) coupled (i.e. electrically coupled) to a gate of the first transistor (i.e. MP9);
a first inverter (i.e. figure 8: 120) coupled (i.e. electrically coupled) between the output (i.e. node of Vref) and reference nodes (i.e. node of Vss) and configured to generate a mode control signal (i.e. output of 120) responsive to a mode select signal (i.e. signal to 120);
a first switching device (i.e. MN18) configured to, responsive to the mode control signal (i.e. output of 120), selectively couple the non-inverting input (i.e. + input) of the amplifier (i.e. amplifier of 300) to the reference node (i.e. node of Vss) through a third passive device (i.e. R2_1); and
a second switching (i.e. MN20) device configured to, responsive to the mode control signal (i.e. output of 120), selectively couple the inverting input (i.e. + input) of the amplifier (i.e. amplifier of 300) to the output node through a fourth passive device (i.e. R2_2),
but does not specifically disclose a non-inverting input directly connected to the power supply node through a first passive device.
Iwata wt al. disclose a voltage generator (i.e. figure 2) comprising a non-inverting input (i.e. + input of 34) directly connected to the power supply node (i.e. Vin) through a first passive device (i.e. 35b).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Jang’s invention with the voltage generator as disclose by Iwata wt al. to improve transient characteristics for rapid change in the input voltage Vin and avoid the overshoot of the output voltage Vout in advance.
Regarding claim 2: (i.e. figures 6-10) wherein the third passive device (i.e. R2_1) is coupled (i.e. electrically coupled) between the non- inverting input (i.e. - input) of the amplifier (i.e. amplifier of 300) and the first switching device (i.e. MN18).
Regarding claim 3: (i.e. figures 6-10) wherein the fourth passive device (i.e. R2_2) is coupled (i.e. electrically coupled) between the inverting input of the amplifier (i.e. amplifier of 300) and the second switching device (i.e. MN20).
Regarding claim 7: (i.e. figures 6-10) wherein the first switching device (i.e. MN18) comprises an n-type transistor.
Regarding claim 8: (i.e. figures 6-10) wherein each of the first through fourth passive devices comprises one or more of a resistive device, a diode, or a diode-configured transistor (i.e. see resistors).
Regarding claim 9: (i.e. figures 6-10) wherein the amplifier (i.e. amplifier of 300) is coupled (i.e. electrically coupled) to each of the power supply and reference nodes (i.e. node of VDD) (i.e. node of Vref).
Regarding claims 17-19: the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated).
6. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20050024129) in view of Iwata wt al. (US 20160299518) and further in view of Farian et al. (US 20200088767).
Regarding claim 10: Jang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose a capacitive device arranged in parallel with the first switching device and the third passive device.
Farian et al. disclose a voltage circuit (i.e. figure 3) comprising a capacitive device (i.e. C1) arranged in parallel with the first switching device (i.e. 32 or 22) and the third passive device (i.e. R1).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Jang’s invention with the circuit as disclose by Farian et al. to have voltage divider circuits having low power consumption requirements suitable for use in battery powered devices.
7. Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20050024129) in view of Kawakubo (US 6531914) and Iwata wt al. (US 20160299518).
Regarding claim 11: Jang discloses a circuit (i.e. figures 6-10) comprising:
a power supply node (i.e. node of VDD);
a reference node (i.e. node of Vss);
a first output node (i.e. node of Vref);
a first transistor (i.e. MP9) coupled (i.e. electrically coupled) between the power supply node (i.e. node of VDD) and the first output node (i.e. node of Vref);
an amplifier (i.e. amplifier of 300) comprising:
a non-inverting input (i.e. + input);
an inverting input (i.e. - input) coupled (i.e. electrically coupled) (i.e. electrically coupled) to the reference node (i.e. node of Vss) through a second passive device (i.e. R2_8); and
an output (i.e. output of amplifier 300) coupled (i.e. electrically coupled) to a gate of the first transistor (i.e. MP9);
a first inverter (i.e. figure 8: 120) coupled (i.e. electrically coupled) between the first output node (i.e. node of Vref) and the reference node (i.e. node of Vss) and configured to generate a first mode control signal (i.e. output of 120) responsive to a mode select signal (i.e. signal to 120);
a second inverter (i.e. 122) coupled (i.e. electrically coupled) between the first output node (i.e. node of Vref) and the reference node (i.e. node of Vss) and configured to generate a second mode control signal (i.e. F0b) responsive to the first mode control signal (i.e. output of 120);
a second transistor (i.e. MN18) configured to, responsive to the second mode control signal (i.e. F0b), selectively couple (i.e. electrically coupled) the non-inverting input of the amplifier (i.e. amplifier of 300) to the reference node (i.e. node of Vss) through a third passive device (i.e. R2_1); and
a gate (i.e. gate of MN20) configured to, responsive to the first (i.e. output of 120) and second mode control signals (i.e. F0b), selectively couple (i.e. electrically coupled) the inverting input of the amplifier (i.e. amplifier of 300) to the first output node (i.e. node of Vref) through a fourth passive device (i.e. R2_2), wherein the circuit is configured to generate a first output voltage (i.e. Vref) on the first output node responsive to the mode select signal (i.e. signal to 120) and a power supply voltage (i.e. VDD) on the power supply node (i.e. node of VDD).
but does not specifically disclose a gate is a transmission gate; and a non-inverting input directly connected to the power supply node through a first passive device.
Kawakubo discloses a voltage circuit (i.e. figure 2) comprising a gate is a transmission gate (i.e. 36).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Jang’s invention with the circuit as disclose by Kawakubo to have a small area, that has many correction points and provides an output voltage with a high precision.
Iwata wt al. disclose a voltage generator (i.e. figure 2) comprising a non-inverting input (i.e. + input of 34) directly connected to the power supply node (i.e. Vin) through a first passive device (i.e. 35b).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Jang’s invention with the voltage generator as disclose by Iwata wt al. to improve transient characteristics for rapid change in the input voltage Vin and avoid the overshoot of the output voltage Vout in advance.
Regarding claim 12: Jang discloses (i.e. figures 6-10) further comprising: a third inverter (i.e. 121) coupled (i.e. electrically coupled) between the first output node and the reference node and configured to generate a second output voltage (i.e. voltage of 120 and/circuit of figure 7) on a second output node (i.e. node of figure 7 and/or 8) responsive to the first mode control signal (i.e. output of 120).
Regarding claim 13: Jang discloses the third inverter comprises one or more transistors (i.e. transistor form the inverter) except for the third inverter comprises one or more transistors having a total channel size larger than a total channel size of one or more transistors of the second inverter. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Jang’s invention to have the third inverter comprises one or more transistors having a total channel size larger than a total channel size of one or more transistors of the second inverter for increase the efficiency of the voltage circuit, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 14: Jang discloses the above except for the total channel size of the one or more transistors of the third inverter is more than 200 times the total channel size of the one or more transistors of the second inverter. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Jang’s invention to have the total channel size of the one or more transistors of the third inverter is more than 200 times the total channel size of the one or more transistors of the second inverter for increase the efficiency of the voltage circuit, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 15: Jang discloses the above except for a total number of the one or more transistors of the third inverter is greater than a total number of the one or more transistors of the second inverter. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Jang’s invention to a total number of the one or more transistors of the third inverter is greater than a total number of the one or more transistors of the second inverter for increase the efficiency of the voltage circuit, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 16: Jang discloses (i.e. figures 6-10) wherein each of the first through fourth passive devices comprises one or more of a resistive device, a diode, or a diode-configured transistor (i.e. see resistors).
8. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 20050024129) in view of Iwata wt al. (US 20160299518).
Regarding claim 20: Jang discloses (i.e. figures 6-10) using a third inverter to generate a second output voltage in response to the first mode control signal, the above except for wherein the using the third inverter comprises the third inverter having a greater total number of transistors than a total number of transistors of the second inverter. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Jang’s invention to have the using the third inverter comprises the third inverter having a greater total number of transistors than a total number of transistors of the second inverter for increase the efficiency of the voltage circuit, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
9. Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/ Primary Examiner, Art Unit 2838
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