DETAILED ACTION
This Non Final Office Action is in response to Application filed on 06/28/2023.
Claims 1-20 filed on 06/28/2023 are being considered on the merits.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings filed on 06/28/2023 are accepted.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/23/2023 have been considered. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly an initialed and dated copy of Applicant's IDS form 1449 filed 08/23/2023 are attached to the instant Office action.
Claim Objections
Claims 1, 8 and 15 are objected to because of the following informalities: Claims 1, 8 and 15 recite “about a value”, emphasis in italic, where the aforementioned term does not definitively recite the “value”. Examiner recommends removing “about” to alleviate any ambiguity that may arise in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-6, 8-9, 11-13, 15-16, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over VAIDYA (US 20190007223 A1) in view of Ghosh (US 20190318130 A1).
Regarding claim 1, VAIDYA (US 20190007223 A1) teaches an apparatus (VAIDYA Figure 2A) comprising:
encryption circuitry, coupled to a power source, to encrypt data into encrypted data (VAIDYA Figure 2A 108 coupled to 104);
time-domain obfuscation control circuitry to connect and disconnect one or more capacitors to the encryption circuitry during the encrypt to provide obfuscation across a time-domain to maintain a software observable power consumption from the power source to about a value (VAIDYA [0011] “…a power converter that utilizes one or more capacitors to power encryption circuitry while encryption is being performed….each of the one or more capacitors may always be charged/discharged to the same upper/lower voltage levels to prevent a power signature from being detectable.”, where the power converter connect and disconnect (i.e. charge and discharge) capacitors 204 to maintain the voltage level to a same upper/lower voltage levels/values, [0018] “…power source 104 may be used by power converter 106 to charge the one or more capacitors… converter 106 may operate one or more switches to conductively couple each capacitor to either the power source 104 or the encryption circuitry 108.”, further in [0029] with respect to capacitors 304 and 308 in Figures 3AB).
While VAIDYA discloses depleting capacitors to the lower voltage by discharging energy stored by capacitors to ground, however, VAIDYA does no explicitly disclose the below limitation.
Ghosh discloses signature attenuation control circuitry to selectively connect the encryption circuitry during the encrypt to a shunt to drain power to maintain the software observable power consumption from the power source at about the value (Ghosh [0033] “…the bypass path 350 is to drain out excess current and to maintain a voltage across the crypto cores 310 to a desired reference voltage such that any variations of in current flow that is visible at VCC is suppressed.”, [0038] “…a bypass path (which may include, for example, a PMOS transistor 450, biased at a reference voltage (V.sub.ref) minus the threshold voltage (V.sub.TH) for the transistor device)), which provides a negative bias and assists in maintaining the current source 430 at saturation.”, where the reference voltage is selectively adjusted by the circuit as power is consumed by the operation of the crypto cores).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified VAIDYA to incorporate the teaching of Ghosh to utilize the above feature, with the motivation of mainlining a reference voltage as the power is consumed by the crypto core, therefore impeding power line attack, as recognized by (Ghosh [0033]).
Regarding claim 8, claim 8 is rejected with the same rationale/motivation applied to claim 1.
Regarding claim 15, claim 15 is rejected with the same rationale/motivation applied to claim 1.
Regarding claim 2, VAIDYA in view of Ghosh teaches the apparatus of claim 1, wherein the value is an average power consumed by the encryption circuitry when operating (VAIDYA discloses upper value and lower value when operating the cryptographic circuit, which can be construed as the average values as power is consumed by the encryption circuit as discussed in claim 1, Ghosh further discloses the reference voltage maintained as power is consumed by the crypto cores as discussed in claim 1, see rationale and motivation).
Regarding claim 9, claim 9 is rejected with the same rationale/motivation applied to claim 2.
Regarding claim 16, claim 16 is rejected with the same rationale/motivation applied to claim 2.
Regarding claim 4, VAIDYA in view of Ghosh teaches the apparatus of claim 2.
VAIDYA does no explicitly disclose the below limitation.
Ghosh discloses wherein the signature attenuation control circuitry is also to set a biased current source to provide power at about the average power (Ghosh [0033] “…the bypass path 350 is to drain out excess current and to maintain a voltage across the crypto cores 310 to a desired reference voltage such that any variations of in current flow that is visible at VCC is suppressed.”, [0038] “…a bypass path (which may include, for example, a PMOS transistor 450, biased at a reference voltage (V.sub.ref) minus the threshold voltage (V.sub.TH) for the transistor device)), which provides a negative bias and assists in maintaining the current source 430 at saturation.”, where the reference voltage is selectively adjusted by the circuit as power is consumed by the operation of the crypto cores, where maintaining a current with no variation and maintaining a reference voltage provide a maintained average power).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified VAIDYA to incorporate the teaching of Ghosh to utilize the above feature, with the motivation of mainlining a reference voltage as the power is consumed by the crypto core, therefore impeding power line attack, as recognized by (Ghosh [0033]).
Regarding claim 11, claim 11 is rejected with the same rationale/motivation applied to claim 4.
Regarding claim 18, claim 18 is rejected with the same rationale/motivation applied to claim 4.
Regarding claim 5, VAIDYA in view of Ghosh teaches the apparatus of claim 1.
VAIDYA does no explicitly disclose the below limitation.
Ghosh discloses wherein the signature attenuation control circuitry is further to selectively connect the encryption circuitry during the encrypt to one or more of the capacitors for charging to drain power to maintain the software observable power consumption from the power source at about the value (Ghosh Figure 3 illustrates connect the crypto core 310 to charging/discharging capacitor 340 while the bypass path, i.e. attenuation control circuitry, drain out any excess current to maintain the reference voltage and current without variation and an average power, [0033] “…the bypass path 350 is to drain out excess current and to maintain a voltage across the crypto cores 310 to a desired reference voltage such that any variations of in current flow that is visible at VCC is suppressed. As the current sources 330 provide fixed currents, the capacitor 340 is to absorb (charge) and provide (discharge) extra current based on executions in the Crypto Cores through charge and discharge operation.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified VAIDYA to incorporate the teaching of Ghosh to utilize the above feature, with the motivation of mainlining a reference voltage as the power is consumed by the crypto core, therefore impeding power line attack, as recognized by (Ghosh [0033]).
Regarding claim 12, claim 12 is rejected with the same rationale/motivation applied to claim 5.
Regarding claim 6, VAIDYA in view of Ghosh teaches the apparatus of claim 1.
VAIDYA discloses that there maybe a randomizer/noise injected, however VAIDYA does not explicitly disclose the below limitation.
Ghosh discloses wherein the signature attenuation control circuitry does not perform noise injection to maintain the software observable power consumption from the power source at about the value (Ghosh Figure 3 does not illustrate any randomizer/noise injected in order to maintain voltage/current/power as the crypto core is executed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified VAIDYA to incorporate the teaching of Ghosh to utilize the above feature, with the motivation of mainlining a reference voltage as the power is consumed by the crypto core, therefore impeding power line attack, as recognized by (Ghosh [0033]).
Regarding claim 13, claim 13 is rejected with the same rationale/motivation applied to claim 6.
Regarding claim 19, claim 19 is rejected with the same rationale/motivation applied to claim 6.
Claims 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over VAIDYA (US 20190007223 A1) in view of Ghosh (US 20190318130 A1) and ABDULGADIR (US 20240421993 A1).
Regarding claim 3, VAIDYA in view of Ghosh teaches the apparatus of claim 2, wherein the value is the average power consumed by the encryption circuitry when performing an operation according to encryption standard (VAIDYA average power consumed by encryption circuitry according to different standards, e.g. in [0019] “electronic codebook (ECB), cipher block chaining (CBC), propagating CBC, cipher feedback (CFB), output feedback (OFB), or counter (CTR).”, Ghosh further discloses utilizing cryptographic standards, [0015] e.g. AES motivation in claim 1 apply).
VAIDYA in view of Ghosh does not explicitly disclose Kyber encryption standard.
ABDULGADIR discloses Kyber encryption standard (ABDULGADIR [0007] “Kyber algorithm is useful for protecting communication between devices but the implementation may leave the system vulnerable to power analysis attacks” and further discloses protecting against power analysis attacks in e.g. [0008]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified VAIDYA in view of Ghosh to incorporate the teaching of ABDULGADIR to utilize the above feature, with the motivation of protecting communication between devices, as recognized by (ABDULGADIR [0007]).
Regarding claim 10, claim 10 is rejected with the same rationale/motivation applied to claim 3.
Regarding claim 17, claim 17 is rejected with the same rationale/motivation applied to claim 3.
Claims 7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over VAIDYA (US 20190007223 A1) in view of Ghosh (US 20190318130 A1) and Ozzie (US 20200034372 A1).
Regarding claim 7, VAIDYA in view of Ghosh teaches the apparatus of claim 1.
VAIDYA in view of Ghosh discloses time-domain obfuscation control circuitry and the signature attenuation control circuitry, which keep the consumed power at constant values to prevent potential attack, however, VAIDYA in view of Ghosh does not disclose a control to enable/disable the process on the aforementioned circuitries to prevent such attack and to keep the drawn/consumed power constant.
Ozzie discloses further comprising a control register that, when set to a first value, enables…and when set to a second value, disables ([0076] “…the Secure Element may draw constant power when enabled to prevent certain side-channel attacks.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified VAIDYA in view of Ghosh to incorporate the teaching of Ozzie to utilize the above feature, with the motivation of selectively draw constant power and prevent certain side-channel attacks, as recognized by (Ozzie [0076]).
Regarding claim 14, claim 14 is rejected with the same rationale/motivation applied to claim 7.
Regarding claim 20, claim 20 is rejected with the same rationale/motivation applied to claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ryan (US 6766455 B1) discloses system and method for preventing differential power analysis attacks (dpa) on a cryptographic device.
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/BASSAM A NOAMAN/Primary Examiner, Art Unit 2497
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