Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claims 1 and 11 (and dependent claims 2-10 and 12-20) recite “A non-transitory computer readable medium, comprising instructions stored therein that when executed by a processor cause the processor to: receive current information of a semiconductor device, calculate an absolute current value of the semiconductor device from the current information and compare the absolute current value with a first threshold; receive information regarding a duration of a forward bias of the semiconductor device and compare the duration with a second threshold if the absolute current value is more than the first threshold; perform a layout review of a tap spacing of selected semiconductor device components; and output safe operation area (SOA) information indicating a forward bias junction result based on the absolute current value, the duration of the forward bias and the layout review.”
Claims 1-20, in view of the claim limitations, recite the abstract idea of “receive current information of a semiconductor device, calculate an absolute current value of the semiconductor device from the current information and compare the absolute current value with a first threshold; receive information regarding a duration of a forward bias of the semiconductor device and compare the duration with a second threshold if the absolute current value is more than the first threshold; perform a layout review of a tap spacing of selected semiconductor device components; and output safe operation area (SOA) information indicating a forward bias junction result based on the absolute current value, the duration of the forward bias and the layout review.”
As a whole, in view of the claim limitations, but for the computer components and systems performing the claimed functions, the broadest reasonable interpretation of the recited “receive current information of a semiconductor device, calculate an absolute current value of the semiconductor device from the current information and compare the absolute current value with a first threshold; receive information regarding a duration of a forward bias of the semiconductor device and compare the duration with a second threshold if the absolute current value is more than the first threshold; perform a layout review of a tap spacing of selected semiconductor device components; and output safe operation area (SOA) information indicating a forward bias junction result based on the absolute current value, the duration of the forward bias and the layout review.”; therefore, the claims recite mental processes and mathematical concepts. Accordingly, the claims recite a mental process and a mathematical concept, and thus, the claims recite an abstract idea under the first prong of Step 2A.
Regarding claims 2 and 12, wherein the processor is configured to measure the duration of the forward bias by calculating a bulk current time duration and/or a gate current time duration. This is an abstract mathematical/measurement step; and hence, there is no practical application added.
Regarding claims 3 and 13, wherein the first threshold is 1 pA. This merely recites a numerical limitation which does not transform the abstract idea.
Regarding claims 4 and 14, wherein the layout review of the tap spacing of selected semiconductor device components is performed if the bulk current time duration or the gate current time duration is more than the second threshold. This is considered as a conditional application of the abstract idea.
Regarding claims 5 and 15, wherein the second threshold is 100 nA*ns. This merely recites a numerical limitation which does not transform the abstract idea.
Regarding claims 6 and 16, wherein performing the layout review of the tap spacing comprises measuring a tap spacing information between a drain or source to a bulk contact to obtain a measured tap spacing information. This is considered as a mental process/data gathering step performed by a generic processor.
Regarding claims 7 and 17, wherein the processor is further configured to measure a ratio N of a predetermined maximum tap spacing divided by the measured tap spacing information. This is considered as a pure mathematical calculation.
Regarding claims 8 and 18, wherein the processor is further configured to compare the duration of the forward bias with the ratio N and the second threshold. Again, it shows an additional comparison which does not transform the abstract idea.
Regarding claims 9 and 19, wherein the forward bias junction result comprise information regarding which the forward bias junction requires manual checking. This is considered as an output of a flag/decision or a post solution activity.
Regarding claims 10 and 20, wherein the semiconductor device is a field effect transistor. This is a field-of-use limitation.
This judicial exception is not integrated into a practical application under the second prong of Step 2A. In particular, the claims recite the additional elements beyond the recited abstract idea of“[a] computer- implemented method” and “the method is carried out by one or more physical processors configured by machine-readable instructions” as recited in claims 1 and 11, individually and when viewed as an ordered combination, and pursuant to the broadest reasonable interpretation, each of the additional elements are computing elements recited at high level of generality implementing the abstract idea on a computer (i.e. apply it), and thus, are no more than applying the abstract idea with generic computer components. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-10 and 12-20 do not integrate the abstract idea into a practical application because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception under Step 2B. As noted above, the aforementioned additional elements beyond the recited abstract idea, as an order combination, are no more than mere instructions to implement the idea using generic computer components (i.e. apply it), and further, generally link the abstract idea to a field of use, which is not sufficient to amount to significantly more than an abstract idea; therefore, the additional elements are not sufficient to amount to significantly more than an abstract idea. Furthermore, as an ordered combination, these elements amount to generic computer components performing repetitive calculations, receiving or transmitting data over a network, which, as held by the courts, are well-understood, routine, and conventional. See MPEP 2106.05(d); July 2015 Update, p. 7. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-10 and 12-20 do not transform the recited abstract idea into a patent eligible invention because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. Looking at these limitations as an ordered combination adds nothing additional that is sufficient to amount to significantly more than the recited abstract idea because they simply provide instructions to use a generic arrangement of generic computer components and recitations of generic computer structure that perform well-understood, routine, and conventional computer functions that are used to “apply” the recited abstract idea. Thus, the elements of the claims, considered both individually and as an ordered combination, are not sufficient to ensure that the claim as a whole amounts to significantly more than the abstract idea itself. Since there are no limitations in these claims that transform the exception into a patent eligible application such that these claims amount to significantly more than the exception itself, claims 1-20 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Riordan (US 9,245,088).
O’Riordon discloses the following claimed features:
Regarding claims 1 and 11, a computing device comprising: a semiconductor device; a processor; and a non-transitory computer readable medium comprising instructions stored therein that when executed by the processor cause the processor (column 10, lines 47-62) to: receive current information of the semiconductor device, calculate an absolute current value of the semiconductor device from the current information and compare the absolute current value with a first threshold; receive information regarding a duration of a forward bias of the semiconductor device and compare the duration with a second threshold if the absolute current value is more than the first threshold; and output safe operation area (SOA) information indicating a forward bias junction result based on the absolute current value, and the duration of the forward bias (Figures 1, 2 and 6; column 2, line 53 to column 3, line 37).
O’Riordon discloses the claimed invention except for explicitly reciting a layout review of a tap spacing of selected semiconductor device components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to include a layout review of a tap spacing of selected semiconductor device components, as it is well known in the semiconductor field that well-tap spacing can be added to a known electrical SOA analysis system in order to improve completeness of the reliability report and reduce the need for separate manual reviews.
Regarding claims 2 and 12, wherein the processor is configured to measure the duration of the forward bias by calculating a bulk current time duration and/or a gate current time duration (it’s conventional in FBSOA characterization).
Regarding claims 3 and 13, wherein the first threshold is 1 pA. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first threshold is 1 pA, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). See also In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to optimize the first threshold for the purpose of obtaining the SOA information indicating a duration of a forward-bias.
Regarding claims 4 and 14, wherein the layout review of the tap spacing of selected semiconductor device components is performed if the bulk current time duration or the gate current time duration is more than the second threshold. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have the layout review of the tap spacing of selected semiconductor device components is performed if the bulk current time duration or the gate current time duration is more than the second threshold, since it has been held to be within the ordinary skill of a worker in the art to select the layout review of the tap spacing on the basis of its suitability for the intended use. One would have been motivated to use the layout review of the tap spacing for the purpose of obtaining a predictable result of a more complete forward-bas junction assessment.
Regarding claims 5 and 15, wherein the second threshold is 100 nA*ns. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second threshold is 100 nA*ns, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). See also In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to optimize the second threshold for the purpose of obtaining the SOA information indicating a duration of a forward-bias.
Regarding claims 6 and 16, wherein performing the layout review of the tap spacing comprises measuring a tap spacing information between a drain or source to a bulk contact to obtain a measured tap spacing information. It would have been obvious to one having ordinary skill in the art at the time the invention was made to include measuring a tap spacing information between a drain or source to a bulk contact to obtain a measured tap spacing information, as it is well known in the semiconductor field that well-tap spacing can be added to a known electrical SOA analysis system in order to improve completeness of the reliability report and reduce the need for separate manual reviews.
Regarding claims 7 and 17, wherein the processor is further configured to measure a ratio N of a predetermined maximum tap spacing divided by the measured tap spacing information. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to measure a ratio N of a predetermined maximum tap spacing divided by the measured tap spacing information, since it has been held to be within the ordinary skill of a worker in the art to measure a ratio N of a predetermined maximum tap spacing divided by the measured tap spacing information on the basis of its suitability for the intended use. One would have been motivated to use measurement of a ratio N of a predetermined maximum tap spacing for the purpose of obtaining and comparing a predictable result of a more complete forward-bas junction assessment.
Regarding claims 8 and 18, wherein the processor is further configured to compare the duration of the forward bias with the ratio N and the second threshold. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to compare the duration of the forward bias with the ratio N and the second threshold, since it has been held to be within the ordinary skill of a worker in the art to compare the duration of the forward bias with the ratio N and the second threshold on the basis of its suitability for the intended use. One would have been motivated to use comparison of the duration of the forward bias with the ratio N and the second threshold for the purpose of obtaining and comparing a predictable result of a more complete forward-bas junction assessment
Regarding claims 9 and 19, wherein the forward bias junction result comprise information regarding which the forward bias junction requires manual checking (Figures 1 and 2; column 2, line 53 to column 3, line 18).
Regarding claims 10 and 20, wherein the semiconductor device is a field effect transistor ((Figures 1 and 2; column 2, line 53 to column 3, line 53).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nakamura (US 10,026,803) discloses a semiconductor device having a vertical structure, providing stable withstand voltage characteristics, reducing a turn-off loss with reduction in leakage current at a time of turn-off, and improving a controllability of a turn-off operation and a blocking capability at a time of turn-off. Qian et al (US 10,997,351) disclose a method that includes: receiving, using at least one processor, a placed layout and one or more electronic design simulation datasets including current information associated with at least one pin; estimating a width to support the current information associated with the at least one pin and updating a pin size associated with the at least one pin based upon, at least in part, the estimated width; identifying at least one pin that is above a predetermined threshold and splitting the at least one pin that is above the predetermined threshold into a plurality of pin; and generating one or more width-spacing-pattern tracks based upon, at least in part, the updated pin size.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AN H DO whose telephone number is (571)272-2143. The examiner can normally be reached on M-F 7:00am-4:00pm.
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/AN H DO/Primary Examiner, Art Unit 2853
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