Prosecution Insights
Last updated: October 02, 2026
Application No. 18/343,770

HIGH VOLTAGE POWER TRANSFER ON PRINTED CIRCUIT BOARD

Non-Final OA §103
Filed
Jun 29, 2023
Examiner
PATEL, AMOL H
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
552 granted / 646 resolved
+25.4% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
13 currently pending
Career history
656
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.1%
+13.1% vs TC avg
§102
36.0%
-4.0% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 646 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4-9, 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pearson (WO 2020/214150 A1). As to claim 1, Pearson discloses a device (fig. 1) comprising: a printed circuit board 170; a package substrate 110 disposed on the printed circuit board; a plurality of voltage regulators 120 disposed on and electrically connected to the package substrate; and a plurality of voltage regulators (¶0012 discloses that the PCB 170 may include additional voltage regulators) disposed on and electrically connected to the printed circuit board. However, Pearson does not disclose a plurality of high-power voltage regulators disposed on and electrically connected to the package substrate and a plurality of low power voltage regulator disposed on and electrically connected to the printed circuit board. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson disposed on the package substrate be high voltage regulators and the plurality of voltage regulators of Pearson disposed on the printed circuit board be low power voltage regulators, since it has been held by the courts that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham 2 USPQ2d 1647 (1987). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson disposed on the package substrate be high voltage regulators and the plurality of voltage regulators of Pearson disposed on the printed circuit board be low power voltage regulators since it was known in the art to choose a voltage regulator based on the voltage requirement of components. As to claim 4, Pearson discloses that the printed circuit board operates at an input voltage (¶0008-0009, 0012, 0013). As to claim 5, Pearson discloses that a bucking operation is conducted by the plurality of high-power voltage regulators on the package substrate (¶0012-0013 discloses a processor operates on a lower voltage level than which is provided to a motherboard.). As to claim 6, Pearson discloses a capacitor disposed on the package substrate to control a ripple voltage of the package substrate (¶0015). As to claim 7, Pearson discloses a base die 140 disposed on the package substrate, wherein the plurality of high-power voltage regulators is positioned adjacent to the base die and provides a power source for the base die. As to claim 9, Pearson discloses a method comprising: providing a printed circuit board 170 (fig. 1); disposing a package substrate 110 on the printed circuit board; disposing and electrically connecting a plurality of voltage regulators 120 to the package substrate; and disposing and electrically connecting a plurality of voltage regulators (¶0012 discloses that the PCB 170 may include additional voltage regulators) to the printed circuit board. However, Pearson does not disclose a plurality of high-power voltage regulators to the package substrate; and disposing and electrically connecting a plurality of low-power voltage regulators to the printed circuit board. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson disposed on the package substrate be high voltage regulators and the plurality of voltage regulators of Pearson disposed on the printed circuit board be low power voltage regulators, since it has been held by the courts that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham 2 USPQ2d 1647 (1987). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson disposed on the package substrate be high voltage regulators and the plurality of voltage regulators of Pearson disposed on the printed circuit board be low power voltage regulators since it was known in the art to choose a voltage regulator based on the voltage requirement of components. As to claim 12, Pearson discloses that the printed circuit board operates at an input voltage (¶0008-0009, 0012, 0013). As to claim 13, Pearson discloses that a bucking operation is conducted by the plurality of high-power voltage regulators on the package substrate (¶0012-0013 discloses a processor operates on a lower voltage level than which is provided to a motherboard.). As to claim 14, Pearson discloses a capacitor disposed on the package substrate to control a ripple voltage of the package substrate (¶0015). As to claim 15, Pearson discloses disposing a base die on the package substrate, wherein the plurality of high-power voltage regulators is positioned adjacent to the base die. As to claim 17, Pearson discloses a device comprising: a package substrate 110; a base die 140 disposed on the package substrate; and a plurality of voltage regulators 120 disposed on and electrically connected to the package substrate, wherein the plurality of voltage regulators are electrically connected to the base die and provides a power source for the base die. However, Pearson does not explicitly disclose a plurality of high-power voltage regulators. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson disposed on the package substrate be high voltage regulators since it has been held by the courts that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham 2 USPQ2d 1647 (1987). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson disposed on the package substrate be high voltage regulators since it was known in the art to choose a voltage regulator based on the voltage requirement of components. As to claim 18, Pearson discloses a printed circuit board 170; and a plurality of voltage regulators ¶0012) disposed on and electrically connected to the printed circuit board, wherein the package substrate is disposed on and electrically connected to the printed circuit board. However, Pearson does not disclose that the plurality of voltage regulators are low-power voltage regulators. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson be low-power voltage regulators since it has been held by the courts that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham 2 USPQ2d 1647 (1987). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of voltage regulators of Pearson be low-voltage power regulators since it was known in the art to choose a voltage regulator based on the voltage requirement of components. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pearson (WO 2020/214150 A1) as applied to claim 1 above, and further in view of Calugaru (Pub. No. US 2020/0381351). As to claim 8, Pearson does not explicitly disclose that the plurality of low-power voltage regulators is positioned adjacent to the package substrate. Calugaru discloses a plurality of power voltage regulators 130, 132, 134 (fig. 1) positioned adjacent to a package substrate 104. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of low-power voltage regulators be positioned adjacent to the package substrate, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of low-power voltage regulator be positioned adjacent to the package substrate in order to prevent voltage droop. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pearson (WO 2020/214150 A1) as applied to claim 9 above, and further in view of Calugaru (Pub. No. US 2020/0381351). As to claim 16, Pearson does not disclose that the plurality of low-power voltage regulators is positioned adjacent to the package substrate. Calugaru discloses a plurality of power voltage regulators 130, 132, 134 positioned adjacent to a package substrate 104. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of low-power voltage regulators be positioned adjacent to the package substrate, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of low-power voltage regulator be positioned adjacent to the package substrate in order to prevent voltage droop. Allowable Subject Matter Claims 2-3, 10-11, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding dependent claim 2, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claim 1, a combination of limitations that discloses wherein a first size of each high-power voltage regulator of the plurality of high-power voltage regulators is smaller than a second size of each low-power voltage regulator of the plurality of low-power voltage regulators. None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 10, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claim 9, a combination of limitations that discloses wherein a first size of each high-power voltage regulator of the plurality of high-power voltage regulators is smaller than a second size of each low-power voltage regulator of the plurality of low-power voltage regulators None of the reference art of record discloses or renders obvious such a combination. Regarding dependent claim 19, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations within the claim and limitation recited in claims 17 and 18, a combination of limitations that discloses wherein a first size of each high-power voltage regulator of the plurality of high-power voltage regulators is smaller than a second size of each low-power voltage regulator of the plurality of low-power voltage regulators. None of the reference art of record discloses or renders obvious such a combination. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMOL H PATEL whose telephone number is (571)270-7833. The examiner can normally be reached 9:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY THOMPSON can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMOL H PATEL/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jun 29, 2023
Application Filed
Nov 15, 2023
Response after Non-Final Action
Sep 11, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+9.5%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 646 resolved cases by this examiner. Grant probability derived from career allowance rate.

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