DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 1-17 are pending and are rejected.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/04/2026 has been entered.
Response to Amendment
This Office Action is responsive to the RCE filed on 08/04/2026.
Claims 1 and 11 are amended and claims 13-17 are new and these amended and new claims are being fully considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant responds
(a) Rejections under 35 U.S.C. § 102
The cited portions of Satyavolu, however, do not disclose "the at least one real-time domain has deterministic execution behavior and the at least one application domain is based on an event-based programming paradigm," as recited in amended claim 1. Satyavolu makes no distinction between a real-time domain having deterministic execution behavior and an application domain based on an event-based programming paradigm.
Furthermore, Satyavolu does not disclose "distributing an application over the at least one real-time domain and the at least one application domain" as claimed.
Satyavolu does not disclose splitting an application such that one part executes on a real-time domain having deterministic execution behavior and another part executes on an application domain based on an event-based programming paradigm.
Furthermore, Satyavolu does not disclose "generating a basic synchronization event in the at least one real-time domain, and transmitting the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain" as claimed…. Moreover, the basic synchronization event "is independent of the transmitted data and is not globally defined for or adjusted to the system."…This is directly contrary to Satyavolu's globally defined, hypervisor-imposed time-triggered scheduling approach.
Accordingly, Satyavolu fails to disclose "distributing an application over the at least one real-time domain and the at least one application domain; and generating a basic synchronization event in the at least one real-time domain, and transmitting the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain; wherein the at least one real-time domain has deterministic execution behavior and the at least one application domain is based on an event-based programming paradigm," as recited in amended claim 1.
Independent claim 11 has been amended to recite similar language as amended claim 1 and is also patentable for the same reasons set forth above.
(Pages: 4-5)
With respect to (a) above, Examiner appreciates the interpretative description given by Applicant in response.
In response to applicant’s amendments to claims 1 and 11, a new grounds of rejections in view of Chen has been introduced. Combination of Chen, LIU and Paulin teach all the limitations of claims 1 and 11 as described in the current office action.
Applicant’s arguments are fully considered, but for the above-described reasons, they are moot; therefore, claims 1-17 are rejected under 35 USC § 103 in view of the references as set forth in the current office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5-11, 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20230266788A1) [hereinafter Chen] and LIU et al. (CN109995628A) [hereinafter LIU], and further in view of Paulin (US20220413459A1) [hereinafter Paulin].
Regarding claim 1 (amended):
Chen disclose(s), A method for operating a control device, which has at least one arithmetic logic unit in which at least one real-time domain and at least one application domain are provided, the method comprising the following steps: [¶6: a control system, a clock synchronization method, a controller, a node device, and a vehicle,…
¶7: provides a control system…a primary controller and at least one node device. The primary controller is configured to perform timing based on a frequency of a local clock signal of the primary controller and execute a task,…
¶21: the at least one node device may be at least one secondary controller…
¶8: the primary controller directly sends the reference clock signal to perform time synchronization, so that precision of clock synchronization between the primary controller and the node device can be improved to precision equal to a pulse width of the reference clock signal…
¶308: The primary controller may include a processor 2101…
¶309: processor 2101 may be a CPU, or…another general-purpose processor,… application-specific integrated circuit (ASIC),…a discrete gate or transistor logic device, a discrete hardware assembly, or the like….
Examiner notes that Chen discloses, arithmetic logic unit such as the general purpose processor that can perform general arithmetic (e.g., add, subtract) and bitwise logic (e.g., AND, OR, XOR) operations;
real time domain where executing tasks per local clock of the primary controller and
at least one application domain where task processing ability of the node devices in non-real time];
generating a basic synchronization event in the at least one real-time domain, [¶7: The primary controller is configured to perform timing based on a frequency of a local clock signal of the primary controller and execute a task,…
¶8: the primary controller directly sends the reference clock signal to perform time synchronization…
¶16: primary controller may be further configured to send a synchronization signal to the at least one node device];
transmitting the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain; [¶16: primary controller may be further configured to send a synchronization signal to the at least one node device…The at least one node device is further configured to correct time of a local clock of the node device based on the received synchronization signal.];
the at least one application domain is based on an event-based programming paradigm. [¶139: the at least one node device 02 is at least one secondary controller,…a task that needs to be executed by the at least one secondary controller 02 each may include one or more of the following tasks: a data transmission task, a data processing task, a sending task of an instruction, and an output task of a drive signal. The instruction may be used to instruct the sensor 03 to collect data, or used to instruct to output the drive signal to the executor 04. Correspondingly, data transmission may be: transmitting data collected by the sensor 03. Data processing may be: processing data collected by the sensor 03…
Examiner notes that, Chen discloses, node device/secondary controller application domain is based on event-based programming paradigm such as sensor output event data based program execution/task completion/data processing], but doesn’t explicitly disclose, and
LIU discloses, distributing an application over the at least one real-time domain and the at least one application domain; and [page 5, ¶10: by using micro controller unit and microprocessor unit as domain…The core chips of controller, being handled using micro controller unit has the soft of pre-provisioning request for real-time performance and/or security performance…
(page 6, ¶4) micro controller unit 100 have real-time performance and/or security performance for handling The software function of pre-provisioning request..
(page 5, ¶10) Part function is handled the software function for having pre-provisioning request for calculated performance and/or communication performance using microprocessor unit, is based on The reasonable distribution and redundancy backup of micro controller unit and microprocessor unit,..
(page 6, ¶4) The microprocessor unit 101 has calculated performance and/or communication performance for processing predetermined It is required that software function.],
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to have combined the capability of distributing an application over the at least one real-time domain and the at least one application domain in order to improve calculated performance, security performance and real-time performance taught by LIU with the method taught by Chen as discussed above in order to have a reasonable expectation of success such as to improve calculated performance, security performance and real-time performance [LIU: (page 4, ¶2) To improve calculating and communication performance… (page, ¶4) takes into account the problem of demand of calculated performance, security performance and real-time performance], but LIU doesn’t explicitly disclose, and
Paulin discloses, wherein the at least one real-time domain has deterministic execution behavior [¶16: the runtime environment defines the priority order in which the programs are processed.… the runtime environment assigns cyclical time slices to the real-time programs which are processed in real time…
¶46: hardware layer 12 and a layer which is formed by a realtime-capable operating system 14…
Examiner notes that Pauline discloses, deterministic execution behavior such as deterministic scheduling; assignment of fixed cyclical time slices for real time processing in real time domain];
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to have combined the at least one real-time domain that has deterministic execution behavior in order to ensure highly stable and secure system taught by Paulin with the method taught by Chen and LIU as discussed above in order to have a reasonable expectation of success such as to ensure highly stable and secure system [Paulin: ¶15: allows for the simultaneous execution of real-time and non-real-time programs, which ensures the system described herein is highly stable and secure].
Regarding Claim 5:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein at least parts of the application are synchronized with the basic synchronization event. [¶7: The primary controller is configured to perform timing based on a frequency of a local clock signal of the primary controller and execute a task,…
¶8: the primary controller directly sends the reference clock signal to perform time synchronization…
¶16: primary controller may be further configured to send a synchronization signal to the at least one node device].
Regarding Claim 6:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), the method is carried out for a control device that is provided for controlling a system selected from a group including the following:
driver assistance systems, industrial manufacturing facilities, systems for transport and data control. [¶234: The system that has a high requirement on function safety includes:…a rail transport drive system, and may further include a drive and control system of an autonomous vehicle, a teleoperated driving vehicle, and an airborne vehicle.].
Regarding Claim 7:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein the method is used for synchronizing data. [¶80: The primary controller…directly send the reference clock signal to the at least one node device…In this way, clock synchronization between the primary controller and the at least one node device is implemented…
¶25: based on load of the primary controller and load of the at least one secondary controller, a data processing task that needs to be executed by the primary controller and a data processing task that needs to be executed by the at least one secondary controller].
Regarding Claim 8:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein the method is used for synchronizing events. [¶80: The primary controller…directly send the reference clock signal to the at least one node device…In this way, clock synchronization between the primary controller and the at least one node device is implemented…
¶145: if the control system includes a plurality of different types of sensors 03 that need to synchronously collect data, the primary controller 01 may set, to a same moment, execution moments of tasks used to instruct the sensor 03 to collect data… he controller in the ring network may send, to the sensor 03 at a same moment, an instruction used to instruct to collect data].
Regarding Claim 9:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein the method is used for configuring algorithms. [¶23: determine the task that needs to be executed by the primary controller and an execution moment of the task, determine the task that needs to be executed by the at least one secondary controller and an execution moment of the task, execute a task at the execution moment of the task that needs to be executed by the primary controller, and send a task scheduling table to the at least one secondary controller. The task scheduling table received by the at least one secondary controller includes the task that needs to be executed by the at least one secondary controller and the execution moment of the task. Correspondingly, the at least one secondary controller may be configured to execute, based on the task scheduling table, the task at the execution moment of the task that needs to be executed by the at least one secondary controller.].
Regarding Claim 10:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Paulin further disclose(s), wherein the method is used for configuring deterministic frameworks. [¶16: the runtime environment defines the priority order in which the programs are processed.… the runtime environment assigns cyclical time slices to the real-time programs which are processed in real time…
¶46: hardware layer 12 and a layer which is formed by a realtime-capable operating system 14…
Examiner notes that Pauline discloses, configuring deterministic execution behavior such as deterministic scheduling; assignment of fixed cyclical time slices for real time processing in real time domain].
Regarding claim 11 (amended):
Chen disclose(s), A control device having at least one arithmetic logic unit in which at least one real-time domain and at least one application domain are provided, the control device configured to: [¶6: a control system, a clock synchronization method, a controller, a node device, and a vehicle,…
¶7: provides a control system…a primary controller and at least one node device. The primary controller is configured to perform timing based on a frequency of a local clock signal of the primary controller and execute a task,…
¶21: the at least one node device may be at least one secondary controller…
¶8: the primary controller directly sends the reference clock signal to perform time synchronization, so that precision of clock synchronization between the primary controller and the node device can be improved to precision equal to a pulse width of the reference clock signal…
¶308: The primary controller may include a processor 2101…
¶309: processor 2101 may be a CPU, or…another general-purpose processor,… application-specific integrated circuit (ASIC),…a discrete gate or transistor logic device, a discrete hardware assembly, or the like….
Examiner notes that Chen discloses, arithmetic logic unit such as the general purpose processor that can perform general arithmetic (e.g., add, subtract) and bitwise logic (e.g., AND, OR, XOR) operations;
real time domain where executing tasks per local clock of the primary controller and
at least one application domain where task processing ability of the node devices in non-real time];
generate a basic synchronization event in the at least one real-time domain, [¶7: The primary controller is configured to perform timing based on a frequency of a local clock signal of the primary controller and execute a task,…
¶8: the primary controller directly sends the reference clock signal to perform time synchronization…
¶16: primary controller may be further configured to send a synchronization signal to the at least one node device];
and transmit the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain; [¶16: primary controller may be further configured to send a synchronization signal to the at least one node device…The at least one node device is further configured to correct time of a local clock of the node device based on the received synchronization signal.];
the at least one application domain is based on an event-based programming paradigm. [¶139: the at least one node device 02 is at least one secondary controller,…a task that needs to be executed by the at least one secondary controller 02 each may include one or more of the following tasks: a data transmission task, a data processing task, a sending task of an instruction, and an output task of a drive signal. The instruction may be used to instruct the sensor 03 to collect data, or used to instruct to output the drive signal to the executor 04. Correspondingly, data transmission may be: transmitting data collected by the sensor 03. Data processing may be: processing data collected by the sensor 03…
Examiner notes that, Chen discloses, node device/secondary controller application domain is based on event-based programming paradigm such as sensor output event data based program execution/task completion/data processing], but doesn’t explicitly disclose, and
LIU discloses, distribute an application over the at least one real-time domain and the at least one application domain; [page 5, ¶10: by using micro controller unit and microprocessor unit as domain…The core chips of controller, being handled using micro controller unit has the soft of pre-provisioning request for real-time performance and/or security performance…
(page 6, ¶4) micro controller unit 100 have real-time performance and/or security performance for handling The software function of pre-provisioning request..
(page 5, ¶10) Part function is handled the software function for having pre-provisioning request for calculated performance and/or communication performance using microprocessor unit, is based on The reasonable distribution and redundancy backup of micro controller unit and microprocessor unit,..
(page 6, ¶4) The microprocessor unit 101 has calculated performance and/or communication performance for processing predetermined It is required that software function.],
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to have combined the above described teachings of LIU with the method taught by Chen as discussed above for the same reasons as described above in claim 1, but LIU doesn’t explicitly disclose, and
Paulin discloses, wherein the at least one real-time domain has deterministic execution behavior [¶16: the runtime environment defines the priority order in which the programs are processed.… the runtime environment assigns cyclical time slices to the real-time programs which are processed in real time…
¶46: hardware layer 12 and a layer which is formed by a realtime-capable operating system 14…
Examiner notes that Pauline discloses, deterministic execution behavior such as deterministic scheduling; assignment of fixed cyclical time slices for real time processing in real time domain];
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to have combined the above described teachings of Paulin with the method taught by Chen and LIU as discussed above for the same reasons as described above in claim 1.
Regarding Claim 13 (new):
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein the at least one real-time domain and the at least one application domain are interconnected by a connection for inter-domain communication and notifications. [¶7: The primary controller is configured to perform timing based on a frequency of a local clock signal of the primary controller and execute a task, and is configured to send a reference clock signal to the at least one node device by using the ring network].
Regarding Claim 14 (new):
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein the at least one real-time domain comprises microcontroller cores having cyclical rate-monotonic task scheduling with time sharing. [¶143: the primary controller 01 may uniformly plan and schedule, by using a time division task (TDT) technology, the tasks that need to be executed by the primary controller 01 and the at least one secondary controller 02. Tasks that need to be executed by different controllers are allocated to different timeslots. In this way, the primary controller 01 and the at least one secondary controller 02 may execute each task in an orderly manner based on a preset task scheduling table, to avoid a problem such as resource preemption or contention that occurs when a plurality of tasks are simultaneously executed, and ensure that each task can be executed in an orderly and efficient manner...…
¶24: Because the primary controller can schedule tasks in a unified manner, the primary controller and the at least one secondary controller can execute tasks in an orderly and efficient manner, to avoid a problem such as resource preemption or contention that occurs when a plurality of tasks are simultaneously executed.].
Regarding Claim 15 (new):
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
LIU further disclose(s), wherein the at least one application domain comprises microprocessor cores running a Portable Operating System Interface (POSIX) operating system. [(page 5, ¶6): in the automobile-used domain controller, the microprocessor unit is using the operation for meeting POSIX standard System].
Regarding Claim 16 (new):
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein the basic synchronization event is independent of any data transmitted between the at least one real-time domain and the at least one application domain and is not globally defined for or adjusted to the control device. [¶80: The primary controller in the control system may directly send the reference clock signal to the at least one node device…Compared with sending of a data frame, direct sending of the reference clock signal may improve precision of clock synchronization between the primary controller and the at least one node device to precision equal to a pulse width of the reference clock signal, thereby effectively improving precision of clock synchronization…
Examiner notes that Chen discloses, the synchronization event is not globally defined or adjusted such that the synchronization is performed independent of any other data transfer process where the primary controller independently performs the synchronization].
Regarding Claim 17 (new):
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, and
Chen further disclose(s), wherein synchronization with the basic synchronization event is carried out by a gateway that is a software component independent of an operating system and that supplies data from a communication stack into an application framework on the at least one application domain. [¶45: the control system may further include a gateway. The gateway is connected to the primary controller or the at least one node device. The gateway is configured to: send, to an external device, data from a device connected to the gateway, and send, to the device connected to the gateway,…
¶47: the gateway may include a primary communication module and a secondary communication module connected to the primary communication module….
¶138: as shown in FIG. 8… at least one sensor 03 may be connected to the primary controller 01 or a node device 02,…
¶164: the at least one node device 02 is a secondary controller, as shown in FIG. 8…A first port 051 of the first router 05 is connected to the primary controller 01 or the secondary controller 02. A second port 052 of the first router 05 is connected to at least one sensor 03…
¶145: plurality of different types of sensors 03 that need to synchronously collect data, the primary controller 01 may set, to a same moment, execution moments of tasks used to instruct the sensor 03 to collect data. In other words, the controller in the ring network may send, to the sensor 03 at a same moment, an instruction used to instruct to collect data.].
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, LIU, Paulin and further in view of SATYAVOLU (US20190389484A1) [hereinafter SATYAVOLU].
Regarding Claim 2:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, but they do not explicitly disclose, and
SATYAVOLU disclose(s), wherein the method is executed on a plurality of arithmetic logic units. [(¶43) “The function modules may include for example, include: a periodic proprioceptive sensing and fusion module 116; a periodic exteroreceptive sensing and fusion module 118; an advanced driver assistance (ADAS) control module 120; a periodic control module (not shown);”… (¶54) “FIG. 3…process 300 for algorithmically controlling automotive functions,..Driver 302 can provide an engage ADAS to ADAS control module 304. ADAS control module 304 can send a startpropsense( ) signal to proprioceptive sensing module 306. ADAS control module 304 can send a startextsense( ) signal to exteroceptive sensing 308. ADAS control module 304 can send a startschedule( ) signal to ADAS control module 304. StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule.”… (¶56) “ADAS control module 304 can send a sensebrakecontrol( ) message to brake control module 310.”… (¶57) “ADAS control module 304 can send a sensethrottleontrol( ) message to throttle control module 312.”
SATYAVOLU discloses, as shown in figures 1-2., plurality of ALU such as 116, 118, 120, 122, 124 etc.].
Regarding Claim 3:
Chen, LIU, Paulin and SATYAVOLU disclose(s), The method as recited in claim 2, and
SATYAVOLU further disclose(s), wherein one of the arithmetic logic units functions as a primary arithmetic logic unit and the other arithmetic logic units function as secondary arithmetic logic units, wherein the primary arithmetic logic unit injects the basic synchronization event into one or more of the secondary arithmetic logic units. [(¶54) “FIG. 3 illustrates an example process 300 for algorithmically controlling automotive functions, according to some embodiments. Driver 302 can provide an engage ADAS to ADAS control module 304. ADAS control module 304 can send a startpropsense( ) signal to proprioceptive sensing module 306. ADAS control module 304 can send a startextsense( ) signal to exteroceptive sensing 308. ADAS control module 304 can send a startschedule( ) signal to ADAS control module 304. StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule. This is important to make sure that all the different control tasks run on different cores are synchronized.”… (¶56) “ADAS control module 304 can send a sensebrakecontrol( ) message to brake control module 310.”… (¶57) “ADAS control module 304 can send a sensethrottleontrol( ) message to throttle control module 312.”
SATYAVOLU discloses, as shown in figure 3., primary ALU, ADAS control module that injects basin synchronization event to secondary ALUs such as synchronized events are injected to proprioceptive sensing module, 306 exteroceptive sensing 308 (StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule)].
Regarding Claim 4:
Chen, LIU, Paulin and SATYAVOLU disclose(s), The method as recited in claim 2, and
SATYAVOLU further disclose(s), wherein the arithmetic local units are single-chip systems. [(¶54) “FIG. 3 illustrates an example process 300 for algorithmically controlling automotive functions, according to some embodiments. Driver 302 can provide an engage ADAS to ADAS control module 304. ADAS control module 304 can send a startpropsense( ) signal to proprioceptive sensing module 306. ADAS control module 304 can send a startextsense( ) signal to exteroceptive sensing 308. ADAS control module 304 can send a startschedule( ) signal to ADAS control module 304. StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule. This is important to make sure that all the different control tasks run on different cores are synchronized.”… (¶56) “ADAS control module 304 can send a sensebrakecontrol( ) message to brake control module 310.”… (¶57) “ADAS control module 304 can send a sensethrottleontrol( ) message to throttle control module 312.”
SATYAVOLU discloses, as shown in figure 3., local arithmetic units such as ADAS control module 304, proprioceptive sensing module 306, exteroceptive sensing 308, brake control module 310, throttle control 312 etc. that are local to the system and are single chip system such as single SOC 102].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, LIU, Paulin and further in view of Thorson et al. (US20200225693A1) [hereinafter Thorson].
Regarding Claim 12:
Chen, LIU, and Paulin disclose(s), The method as recited in claim 1, but they do not explicitly disclose, and
Thorson discloses, wherein the control device includes a number of single-chip systems. [(¶13) “FIG. 1 illustrates timing synchronization between two systems according to one embodiment. Features and advantages of the present disclosure include techniques for synchronizing a plurality of systems. In one embodiment, the systems may be multiple chips, such as multiple integrated circuits coupled together through an interface, such as a high speed digital communications channel, for example. FIG. 1 illustrates an example of two chips, chip 1 100 and chip 2 101, coupled together over a data communications link 150.”… (¶14) “Chips 100 and 101 may each include chip-to-chip (C2C) interface circuitry 110 and 111, system circuitry 120 and 121, and execution units 102 and 103 for executing programs 104 and 105, for example.”
Thorson disclose, control device including multiple single chip systems such as system 100 with chip 1 and system 101 with chip 2 as shown in figure 1.].
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to have combined the at least two single chip systems in a control device to have the advantage of performing timing markers on the same cycles in each program on different systems in a reliable and predictable manner taught by Thorson with the system taught by Chen, LIU, and Paulin as discussed above in order to have a reasonable expectation of success such as to have the advantage of performing timing markers on the same cycles in each program on different systems in a reliable and predictable manner [Thorson: (¶21) “Since each operation is known to occur on a particular cycle, execution of timing markers on the same cycles in each program on different systems may be performed in a reliable and predictable manner,”].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed in the PTO-892 Notice of Reference Cited document mailed on 10/01/2025.
Rota (US20180307635A1) - A vehicle safety electronic control system:
(¶12): a vehicle safety electronic control system, including: a master microcontroller and a slave microcontroller;….the master…to issue a corresponding secondary synchronization signal to the slave microcontroller via the general purpose input/output connection, the slave microcontroller being configured to update its synchronization counter in response to receipt of the secondary synchronization signal from the master microcontroller such that the schedule tables of both microcontrollers are synchronized to the network bus.
Böhm et al. (US20100292867A1) - Motor Vehicle Control Device:
(¶21): a motor vehicle control device is provided, comprising software for controlling a plurality of applications, wherein the software has the following layers: an application layer with a plurality of applications; a base software layer with a first plurality of AUTOSAR-based base services and a second plurality of AUTOSAR-independent base services, to carry out the applications; an adaption layer with at least a first run time environment, which is assigned to the first plurality of base services, and a second run time environment, which is assigned to the second plurality of base services, wherein the adaption layer connects the application layer with the base software layer; and an operating system layer with a microkernel.
Atsmon et al. (US20170039084A1) - Enhanced advanced driver assistance system (adas) system on chip:
(¶5): a system on chip (SoC), comprising: an integrated circuit (IC) integrating the following into a single chip: at least one advance driver assistance systems (ADAS) processing unit, at least one application processing unit,…processing vehicle sensor data and VM code for executing on the at least one application processing unit at least one VM separately and independently from an execution of the ADAS code, and a hypervisor which manages an execution of at least one operation system (OS) of the at least one VM and an access to a processor shared memory of the at least one ADAS processing unit for acquiring an outcome of executing the ADAS computer instructions for the completion of an ADAS enhancing function by the execution of the at least one VM on the at least one application processing unit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAFAYET whose telephone number is (571)272-8239. The examiner can normally be reached M-F 8:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.S./
Patent Examiner,
Art Unit 2116
/CHAD G ERDMAN/Primary Examiner, Art Unit 2116
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