DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 1-12 are pending and are rejected.
Response to Amendment
This Office Action is responsive to the amendment filed on 01/02/2026.
Claims 4 and 12 are amended and are being fully considered by the examiner.
In response to applicant’s amendments to claims 4 and 12, all the 35 USC § 112 rejections as set forth in the previous office action has been withdrawn.
This action is MADE FINAL. Please see response to arguments section for further details.
Response to Arguments
Applicant's arguments filed 12/22/2021 have been fully considered but they are not persuasive.
Applicant responds
(a) Rejections under 35 U.S.C. § 102
However, Satyavolu does not disclose "the at least one real-time domain and the at least one application domain." Satyavolu discloses "cores and VCPUs," which are not "the at least one real-time domain and the at least one application domain." Indeed Satyavolu is silent regarding an application distributed over real time domains and application domains.
Therefore, the cited portions of Satyavolu describes a hypervisor software layer that handles scheduling of communication between buses and cores.
Satyavolu does not disclose a "real-time domain" and an "application domain." Indeed, Satyavolu is silent regarding generating a synchronization event in a real-time domain and transmitting the event to an application domain.
Accordingly, Satyavolu fails to disclose "distributing an application over the at least one real-time domain and the at least one application domain; and generating a basic synchronization event in the at least one real-time domain, and transmitting the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain," as recited in claim 1.
(Pages: 4-5)
With respect to (a) above, Examiner appreciates the interpretative description given by Applicant in response.
In broadest reasonable interpretation, claim limitation, distributing an application over the at least one real-time domain and the at least one application domain, means an application is provided over real time domain and application domain. As described in the previous office action, SATYAVOLU discloses, hypervisor layer of software is distributed over the cores 106 and VCPUs 110 as shown in figure 1.
In broadest reasonable interpretation, claim limitation, generating a basic synchronization event in the at least one real-time domain, and transmitting the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain, means a initiating and transmitting basic synchronization from real-time domain to application domain to achieve synchronization between them. Regarding the remarks, Satyavolu does not disclose "the at least one real-time domain and the at least one application domain." Satyavolu discloses "cores and VCPUs," which are not "the at least one real-time domain and the at least one application domain, as described in the previous office action, SATYAVOLU disclose, cores such as the real-time domain and application domain such as the VCPUs. Claim limitations as described above are broad, and doesn’t clearly recite what the application domain is. Therefore, application domain can be any application domain and claim doesn’t further clarify how this application domain is in terms of clock (real time or non-real time). Further, claim is broad regarding synchronization between these two domains and only describes real time domain initiates the synchronization and thereby real time domain and application domains are being synchronized. Accordingly, described in the previous office action, SATYAVOLU discloses, real time core 106 initiates and transmits synchronization event to application domain VCPU 110 to achieve synchronization between core 106 and VCPU 110 to achieve timing coherence.
For the purpose of compact prosecution, examiner suggests to further clarify the application domain in terms of time/clock and how it differs from the real time domain.
Applicant’s arguments are fully considered, but for the above described reasons, they are not persuasive; therefore, the 35 USC § 102 rejections of claims 1-9 and 11 as set forth in the previous office action are maintained.
(b) Rejections under 35 U.S.C. § 103
Claims 10 depends from claim 1 and claim 12 depends from claim 11. As explained above, claims 1 and 11 are patentable over Satyavolu. Thorson does not, and the Office has not shown that it would, cure the deficiencies of Satyavolu. Claims 10 and 12 are therefore patentable over Satyavolu and Thorson for at least the same reasons as set forth above. Reconsideration and withdrawal of the rejection is requested..
(Page: 6)
With respect to (b) above, Examiner appreciates the interpretative description given by Applicant in response.
Applicant’s arguments are fully considered, but for the same reasons as described above in (a), they are not persuasive; therefore, the 35 USC § 103 rejections of claims 10 and 12 as set forth in the previous office action are maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by SATYAVOLU (US20190389484A1) [hereinafter SATYAVOLU].
Regarding claim 1:
SATYAVOLU disclose(s), A method for operating a control device, which has at least one arithmetic logic unit in which at least one real-time and at least one application domain are provided, the method comprising the following steps: [(¶11) “a system, method, and article of manufacture for algorithmically controlling automotive functions”…(¶39) “FIG. 1 illustrates an example system 100 of an architecture for providing multi-function control in an automobile in accordance, according to some embodiments.”… (¶41) “The architecture includes a multicore system on chip (SoC) 102 with” “virtualization through a hypervisor 104),” “The SoC 102 may be a multi-core chip (e.g. includes core's 106 A-H)” “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.”
SATYAVOLU teaches operating control device that has at least one arithmetic logic unit such as system on chip 102 in which at least one real time domain such as cpu core 106 and at least one application domain such as virtual cpu core VCPU 110 as shown in figure 1.];
distributing an application over the at least one real-time domain and the at least one application domain; and [(¶41) “The architecture includes a multicore system on chip (SoC) 102 with” “virtualization through a hypervisor 104),” “The SoC 102 may be a multi-core chip (e.g. includes core's 106 A-H)” “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.”
SATYAVOLU teaches, distributing an application, such as hypervisor layer of software over the cores 106 and VCPUs 110 as shown in figure 1.];
generating a basic synchronization event in the at least one real-time domain, and transmitting the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain. [(¶41) “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.” “The hypervisor may include a time-triggered scheduler (e.g. an ARINC 653, multicore synchronization, etc.) at a global level, and drivers handling the MAC-level scheduling for the buses and inter core (e.g. inter VM, etc.) communications using a deterministic protocol. The hypervisor control over timing aids in achieving timing coherence, composability and a separation of concerns.” “A basic software layer, a runtime-environment (e.g. VFB, etc.) and an application layer are key layers in stack 112 A-F. Stack 112 A-F may also include a local scheduler for real-time multi-tasking at a local level.”
SATYAVOLU teaches, transmitting synchronization event on core 106 to VCPU 110 to achieve synchronization between core 106 and VCPU 110 to achieve timing coherence].
Regarding Claim 2:
SATYAVOLU disclose(s) all the elements of claim 1, and further disclose(s), wherein the method is executed on a plurality of arithmetic logic units. [(¶43) “The function modules may include for example, include: a periodic proprioceptive sensing and fusion module 116; a periodic exteroreceptive sensing and fusion module 118; an advanced driver assistance (ADAS) control module 120; a periodic control module (not shown); a periodic throttle control module 122; a periodic brake control module 124; a periodic steering control module 126; a sporadic error sensing module 128; and an infotainment module 130.”… (¶54) “FIG. 3 illustrates an example process 300 for algorithmically controlling automotive functions, according to some embodiments. Driver 302 can provide an engage ADAS to ADAS control module 304. ADAS control module 304 can send a startpropsense( ) signal to proprioceptive sensing module 306. ADAS control module 304 can send a startextsense( ) signal to exteroceptive sensing 308. ADAS control module 304 can send a startschedule( ) signal to ADAS control module 304. StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule. This is important to make sure that all the different control tasks run on different cores are synchronized.”… (¶56) “ADAS control module 304 can send a sensebrakecontrol( ) message to brake control module 310.”… (¶57) “ADAS control module 304 can send a sensethrottleontrol( ) message to throttle control module 312.”
SATYAVOLU discloses, as shown in figures 1-2., plurality of ALU such as a periodic proprioceptive sensing and fusion module 116; a periodic exteroreceptive sensing and fusion module 118; an advanced driver assistance (ADAS) control module 120; a periodic control module (not shown); a periodic throttle control module 122; a periodic brake control module 124; a periodic steering control module 126; a sporadic error sensing module 128; and an infotainment module 130; and as shown in figure 3, ADAS control module 304, proprioceptive sensing module 306, exteroceptive sensing 308, brake control module 310, throttle control 312 etc.].
Regarding Claim 3:
SATYAVOLU disclose(s) all the elements of claims 1-2, and further disclose(s), wherein one of the arithmetic logic units functions as a primary arithmetic logic unit and the other arithmetic logic units function as secondary arithmetic logic units, wherein the primary arithmetic logic unit injects the basic synchronization event into one or more of the secondary arithmetic logic units. [(¶54) “FIG. 3 illustrates an example process 300 for algorithmically controlling automotive functions, according to some embodiments. Driver 302 can provide an engage ADAS to ADAS control module 304. ADAS control module 304 can send a startpropsense( ) signal to proprioceptive sensing module 306. ADAS control module 304 can send a startextsense( ) signal to exteroceptive sensing 308. ADAS control module 304 can send a startschedule( ) signal to ADAS control module 304. StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule. This is important to make sure that all the different control tasks run on different cores are synchronized.”… (¶56) “ADAS control module 304 can send a sensebrakecontrol( ) message to brake control module 310.”… (¶57) “ADAS control module 304 can send a sensethrottleontrol( ) message to throttle control module 312.”
SATYAVOLU discloses, as shown in figure 3., primary ALU, ADAS control module that injects basin synchronization event to secondary ALUs such as synchronized events are injected to proprioceptive sensing module, 306 exteroceptive sensing 308 (StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule)].
Regarding Claim 4 (amended):
SATYAVOLU disclose(s) all the elements of claims 1-2, and further disclose(s), wherein the arithmetic local units are single-chip systems. [(¶54) “FIG. 3 illustrates an example process 300 for algorithmically controlling automotive functions, according to some embodiments. Driver 302 can provide an engage ADAS to ADAS control module 304. ADAS control module 304 can send a startpropsense( ) signal to proprioceptive sensing module 306. ADAS control module 304 can send a startextsense( ) signal to exteroceptive sensing 308. ADAS control module 304 can send a startschedule( ) signal to ADAS control module 304. StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule. This is important to make sure that all the different control tasks run on different cores are synchronized.”… (¶56) “ADAS control module 304 can send a sensebrakecontrol( ) message to brake control module 310.”… (¶57) “ADAS control module 304 can send a sensethrottleontrol( ) message to throttle control module 312.”
SATYAVOLU discloses, as shown in figure 3., local arithmetic units such as ADAS control module 304, proprioceptive sensing module 306, exteroceptive sensing 308, brake control module 310, throttle control 312 etc. that are local to the system and are single chip system such as single SOC 102].
Regarding Claim 5:
SATYAVOLU disclose(s) all the elements of claim 1, and further disclose(s), wherein at least parts of the application are synchronized with the basic synchronization event. [(¶41) “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.” “The hypervisor may include a time-triggered scheduler (e.g. an ARINC 653, multicore synchronization, etc.) at a global level, and drivers handling the MAC-level scheduling for the buses and inter core (e.g. inter VM, etc.) communications using a deterministic protocol. The hypervisor control over timing aids in achieving timing coherence, composability and a separation of concerns.” “A basic software layer, a runtime-environment (e.g. VFB, etc.) and an application layer are key layers in stack 112 A-F. Stack 112 A-F may also include a local scheduler for real-time multi-tasking at a local level.”
SATYAVOLU teaches, basic synchronization event such as time-triggered multicore synchronization. The hypervisor control over timing aids in achieving timing coherence].
Regarding Claim 6:
SATYAVOLU disclose(s) all the elements of claim 1, and further disclose(s), wherein the method is carried out for a control device that is provided for controlling a system selected from a group including the following: driver assistance systems, industrial manufacturing facilities, systems for transport and data control. [(¶4) “a computerized system for controlling automotive functions of a vehicle”… (¶17) “Advanced Driver Assistance Systems (ADAS can be systems to help the driver in the driving process.”… (¶43) “an advanced driver assistance (ADAS) control module 120;”
Examiner notes that claim requires control device that is provided for controlling only one of these selected systems: driver assistance systems, industrial manufacturing facilities, systems for transport and data control.
SATYAVOLU teaches driver assistance systems, such as Advanced Driver Assistance Systems, ADAS can be systems to help the driver in the driving process].
Regarding Claim 7:
SATYAVOLU disclose(s) all the elements of claim 1, and further disclose(s), wherein the method is used for synchronizing data. [(¶38) “provide a centralized control module for synchronizing drive-by-wire commands, autonomous driving control, and/or connected automobile technologies.”… (¶54) “StartSchedule kicks off a time triggered scheduler to do periods processing with multicore synchronization at the beginning of every period to make sure all the cores run a synchronized schedule. This is important to make sure that all the different control tasks run on different cores are synchronized.”… (¶56) “ADAS control module 304 can send a sensebrakecontrol( ) message to brake control module 310.”… (¶57) “ADAS control module 304 can send a sensethrottleontrol( ) message to throttle control module 312.”
SATYAVOLU teaches, control related data synchronization such as Drive-by-wire commands that are electronic instructions sent to a vehicle's electronic control systems to operate components like the throttle, brakes, and steering].
Regarding Claim 8:
SATYAVOLU disclose(s) all the elements of claim 1, and further disclose(s), wherein the method is used for synchronizing events. [(¶41) “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.” “The hypervisor may include a time-triggered scheduler (e.g. an ARINC 653, multicore synchronization, etc.) at a global level, and drivers handling the MAC-level scheduling for the buses and inter core (e.g. inter VM, etc.) communications using a deterministic protocol. The hypervisor control over timing aids in achieving timing coherence, composability and a separation of concerns.” “A basic software layer, a runtime-environment (e.g. VFB, etc.) and an application layer are key layers in stack 112 A-F. Stack 112 A-F may also include a local scheduler for real-time multi-tasking at a local level.”
SATYAVOLU teaches, event base synchronization such as time-triggered multicore synchronization. The hypervisor control over timing aids in achieving timing coherence].
Regarding Claim 9:
SATYAVOLU disclose(s) all the elements of claim 1, and further disclose(s), wherein the method is used for configuring algorithms. [(¶41) “A throttle and brake control algorithm may be configured to achieve a desired acceleration/deceleration profile. This can be implemented periodic throttle control module 122 and/or periodic brake control module 124. ADAS controller module 120 can be a centralized-control module that provides a direct user interface to engage or disengage the ADAS and/or the sporadic-error sensing module. ADAS controller module 120 can primarily controls all the control functions including the mentioned direct user interface to engage or disengage the ADAS and/or the sporadic-error sensing module.”].
Regarding claim 11:
SATYAVOLU disclose(s), A control device having at least one arithmetic logic unit in which at least one real-time and at least one application domain are provided, the control device configured to: [(¶11) “a system, method, and article of manufacture for algorithmically controlling automotive functions”…(¶39) “FIG. 1 illustrates an example system 100 of an architecture for providing multi-function control in an automobile in accordance, according to some embodiments.”… (¶41) “The architecture includes a multicore system on chip (SoC) 102 with” “virtualization through a hypervisor 104),” “The SoC 102 may be a multi-core chip (e.g. includes core's 106 A-H)” “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.”
SATYAVOLU teaches operating control device that has at least one arithmetic logic unit such as system on chip 102 in which at least one real time domain such as cpu core 106 and at least one application domain such as virtual cpu core VCPU 110 as shown in figure 1.];
distribute an application over the at least one real-time domain and the at least one application domain; and [(¶41) “The architecture includes a multicore system on chip (SoC) 102 with” “virtualization through a hypervisor 104),” “The SoC 102 may be a multi-core chip (e.g. includes core's 106 A-H)” “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.”
SATYAVOLU teaches, distributing an application, such as hypervisor layer of software over the cores 106 and VCPUs 110 as shown in figure 1.];
generate a basic synchronization event in the at least one real-time domain, and transmit the basic synchronization event to the at least one application domain such that synchronization is achieved between the at least one real-time domain and the at least one application domain. [(¶41) “synchronous media oriented interface (e.g. multi-core (MC) synchronization functionalities 108 A-E)” “A hypervisor layer of software is included (in for example, firmware) that abstracts and encapsulates the global timing control and scheduling at a global level for both the computer and communication resources via virtual CPUs 110 A-F communication of each core 106 A-H to each module function.” “The hypervisor may include a time-triggered scheduler (e.g. an ARINC 653, multicore synchronization, etc.) at a global level, and drivers handling the MAC-level scheduling for the buses and inter core (e.g. inter VM, etc.) communications using a deterministic protocol. The hypervisor control over timing aids in achieving timing coherence, composability and a separation of concerns.” “A basic software layer, a runtime-environment (e.g. VFB, etc.) and an application layer are key layers in stack 112 A-F. Stack 112 A-F may also include a local scheduler for real-time multi-tasking at a local level.”
SATYAVOLU teaches, transmitting synchronization event on core 106 to VCPU 110 to achieve synchronization between core 106 and VCPU 110 to achieve timing coherence].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over SATYAVOLU, and further in view of Thorson et al. (US20200225693A1) [hereinafter Thorson].
Regarding Claim 10:
SATYAVOLU disclose(s) all the elements of claim 1, but doesn’t explicitly disclose, wherein the method is used for configuring deterministic frameworks.
However, Thorson discloses, wherein the method is used for configuring deterministic frameworks. [(¶21) “the programs are components of a larger deterministic program generated by the same compiler (e.g., compiler 160 in FIG. 1). For example, a deterministic program may be distinguished from a non-deterministic program in that the operations performed by a deterministic program on each cycle are known prior to execution (although the particular numerical values processed may not be). Since each operation is known to occur on a particular cycle, execution of timing markers on the same cycles in each program on different systems may be performed in a reliable and predictable manner, for example, and the master and slave systems (so called for synchronization purposes) may be configured to send and receive synchronization information at known times within known time ranges,”].
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to have combined the capability of configuring deterministic frameworks to performing timing markers on the same cycles in each program on different systems in a reliable and predictable manner taught by Thorson with the method taught by SATYAVOLU as discussed above in order to have a reasonable expectation of success such as to have the advantage of performing timing markers on the same cycles in each program on different systems in a reliable and predictable manner [Thorson: (¶21) “Since each operation is known to occur on a particular cycle, execution of timing markers on the same cycles in each program on different systems may be performed in a reliable and predictable manner,”].
Regarding Claim 12 (amended):
SATYAVOLU disclose(s) all the elements of claim 11, but doesn’t explicitly disclose, wherein the control device includes a number of single-chip systems.
However, Thorson discloses, wherein the control device includes a number of single-chip systems. [(¶13) “FIG. 1 illustrates timing synchronization between two systems according to one embodiment. Features and advantages of the present disclosure include techniques for synchronizing a plurality of systems. In one embodiment, the systems may be multiple chips, such as multiple integrated circuits coupled together through an interface, such as a high speed digital communications channel, for example. FIG. 1 illustrates an example of two chips, chip 1 100 and chip 2 101, coupled together over a data communications link 150.”… (¶14) “Chips 100 and 101 may each include chip-to-chip (C2C) interface circuitry 110 and 111, system circuitry 120 and 121, and execution units 102 and 103 for executing programs 104 and 105, for example.”
Thorson disclose, control device including multiple single chip systems such as system 100 with chip 1 and system 101 with chip 2 as shown in figure 1.].
Therefore, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to have combined the at least two single chip systems in a control device to have the advantage of performing timing markers on the same cycles in each program on different systems in a reliable and predictable manner taught by Thorson with the system taught by SATYAVOLU as discussed above in order to have a reasonable expectation of success such as to have the advantage of performing timing markers on the same cycles in each program on different systems in a reliable and predictable manner [Thorson: (¶21) “Since each operation is known to occur on a particular cycle, execution of timing markers on the same cycles in each program on different systems may be performed in a reliable and predictable manner,”].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed in the PTO-892 Notice of Reference Cited document mailed on 10/01/2025.
Rota (US20180307635A1) - A vehicle safety electronic control system:
(¶12): a vehicle safety electronic control system, including: a master microcontroller and a slave microcontroller;….the master…to issue a corresponding secondary synchronization signal to the slave microcontroller via the general purpose input/output connection, the slave microcontroller being configured to update its synchronization counter in response to receipt of the secondary synchronization signal from the master microcontroller such that the schedule tables of both microcontrollers are synchronized to the network bus.
Böhm et al. (US20100292867A1) - Motor Vehicle Control Device:
(¶21): a motor vehicle control device is provided, comprising software for controlling a plurality of applications, wherein the software has the following layers: an application layer with a plurality of applications; a base software layer with a first plurality of AUTOSAR-based base services and a second plurality of AUTOSAR-independent base services, to carry out the applications; an adaption layer with at least a first run time environment, which is assigned to the first plurality of base services, and a second run time environment, which is assigned to the second plurality of base services, wherein the adaption layer connects the application layer with the base software layer; and an operating system layer with a microkernel.
Atsmon et al. (US20170039084A1) - Enhanced advanced driver assistance system (adas) system on chip:
(¶5): a system on chip (SoC), comprising: an integrated circuit (IC) integrating the following into a single chip: at least one advance driver assistance systems (ADAS) processing unit, at least one application processing unit,…processing vehicle sensor data and VM code for executing on the at least one application processing unit at least one VM separately and independently from an execution of the ADAS code, and a hypervisor which manages an execution of at least one operation system (OS) of the at least one VM and an access to a processor shared memory of the at least one ADAS processing unit for acquiring an outcome of executing the ADAS computer instructions for the completion of an ADAS enhancing function by the execution of the at least one VM on the at least one application processing unit.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAFAYET whose telephone number is (571)272-8239. The examiner can normally be reached M-F 8:30 AM-5:00 PM.
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/M.S./
Patent Examiner,
Art Unit 2116
/KENNETH M LO/Supervisory Patent Examiner, Art Unit 2116
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