DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (10,867,101 B1) .
Regarding claim 1, Lin et al discloses a semiconductor structure (Figures 1A, 1B, 7C and 7D), comprising: a logic cell (Figures 7C and 7D), comprising: a first transistor (Figure 1B, reference 150) comprising a first gate structure (Figure 1B, reference 127) extending in a first direction and overlapping a first semiconductor fin (Figure 1B, reference 116); and a second transistor (Figure 1B, reference 123), comprising a second gate structure (Figure 1B, reference 124) extending in the first direction and overlapping the first semiconductor fin (Figure 1B, reference 116) and a second semiconductor fin (Figure 1B, reference 120), wherein the first and second semiconductor fins (Figure 1B, references 116 and 120) extend in a second direction that is perpendicular to the first direction, wherein the first and second transistors (Figure 1B, references 123c and 150) share a source/drain region (Figure 1B, reference 114b), and one end of the first gate structure (Figure 1B, reference 150) is formed between the first and second semiconductor fins (Figure 1B, references 116 and 120).
Regarding claim 2, Lin et al discloses wherein the first and second transistors (Figure 1B, references 123c and 127) have the same conductivity type (column 5, lines 24-41).
Regarding claim 3, Lin et al discloses wherein the first and second semiconductor fins have the same length in the logic cell (Figure 1B, references 116 and 120).
Regarding claim 4, Lin et al discloses wherein the logic cell further comprises: a third transistor, comprising the second gate structure extending in the first direction and overlapping a third semiconductor fin, wherein the third semiconductor fin is parallel to the first and second semiconductor fins, and the second and third transistors have different conductivity types (Figures 7C and 7D).
Allowable Subject Matter
Claims 5-20 are allowed over the prior of record.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest a semiconductor structure, comprising: N-type transistors of the first logic cells disposed in the first row of the cell array share a plurality of second continuous fins, wherein the number of the first continuous fins is different from the number of the second continuous fins in the first row of the cell array (claim 5) and a semiconductor structure, comprising: N-type transistors of the logic cells disposed in the first row of the cell array share a plurality of second semiconductor fins extending in the first direction, wherein a first logic cell in the first row of the cell array comprises a first P-type transistor and a first N-type transistor, wherein the number of the first semiconductor fins overlapping a first gate structure of the first P-type transistor is different from the number of the second semiconductor fins overlapping a second gate structure of the first N-type transistor, wherein the first and second gate structures extend in a second direction that is perpendicular to the first direction, and the first and second gate structures are aligned in the second direction (claim 13) as described in the independent claims and in the context of its recited apparatuses, along with their depending claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liaw (12,159,872 B2) discloses an IC including a first P-type FinFET and a second P-type FinFET and first source/drain regions of the first P-type FinFET are formed on a discontinuous semiconductor fin, and second source/drain regions of the second P-type FinFET are formed on a continuous semiconductor fin. However, Liaw does not disclose the allowable claimed subject matter as stated above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
April 24, 2026
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