DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-26 and 28-41 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsumura et al. (US 5,379,257).
Consider claim 21, Matsumura et al. discloses an apparatus, comprising: an array of memory cells; sensing circuitry selectably coupled to the array of memory cells; a plurality of first input/output (I/O) lines configured as a data path that couples the sensing circuitry to a compute unit; and one or more controllers associated with the array of memory cells, wherein the one or more controllers are configured to cause the compute unit to perform, during a first duration, a first number of operations comprising a first type of computation on a first portion of data transferred from the array of memory cells to the compute unit via the plurality of first I/O lines and to perform, during the first duration and simultaneously with the first number of operations, a second number of operations comprising a second type of computation different from the first type of computation on a second portion of the data transferred from the array of memory cells to the compute unit via the plurality of first I/O lines, wherein results of the first number of operations or the second number of operations, or both, are stored in the array of memory cells without enabling one or more second lines to transfer the results from the array of memory cells to circuitry external to the array of memory cells (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use. The claims do not define what a first duration is and therefore the examiner considers any duration to be the first duration and the system of Matsumura et al. discloses performing multiple adds across many add units and the results of the fuller adder are sent to other functional blocks. This is done for multiple commands. Matsumura et al. discloses, in fig. 10 for example, that multiple pieces of data go through the selectors (operations) together, sense amplifiers (operations) together, full adder (operations) together and tri-state buffer circuit (operations) together. Col. 14 lines 16-22 state that the operation circuit may be comprised of any elements having a bit slice structure will produce the same effects as the full adder. That includes adders, subtractors, ALUs and multipliers. The input data into the memory cell arrays can be from data operation results. Data can be stored in the memory array without enabling a line to transfer the results out of the array, at the time the results are being stored in the memory array. This second line could also just not be the I/O line that is used to do transfers out of the memory array.).
Consider claim 22, Matsumura et al. discloses the apparatus of claim 21, wherein the compute unit includes a plurality of logic stripes (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use.).
Consider claim 23, Matsumura et al. discloses the apparatus of claim 22, wherein the plurality of logic stripes include a first portion of logic stripes that perform the first number of operations during the first duration on the first portion of data transferred from the array of memory cells to the first portion of logic stripes (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use.).
Consider claim 24, Matsumura et al. discloses the apparatus of claim 22, wherein the plurality of logic stripes include a second portion of logic stripes and wherein the one or more controller configured to cause the second portion of logic stripes to perform second number of operations on second portion of data transferred from the array of memory cells to the compute unit via the plurality of first I/O lines (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use.).
Consider claim 25, Matsumura et al. discloses the apparatus of claim 21, wherein the first number of operations are the same as the second number of operations (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. “a first number of operations on a first portion of data” and “a second number of operations on a second portion of data” are an arbitrary number of operations that are performed for each portion up to a maximum of the total number of operations performed for each. Therefore, the examiner can interpret these values to be different or the same.).
Consider claim 26, Matsumura et al. discloses the apparatus of claim 21, wherein the first number of operations are different than the second number of operations (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. “a first number of operations on a first portion of data” and “a second number of operations on a second portion of data” are an arbitrary number of operations that are performed for each portion up to a maximum of the total number of operations performed for each. Therefore, the examiner can interpret these values to be different or the same.).
Consider claim 28, Matsumura et al. discloses an apparatus, comprising: an array of memory cells; sensing circuitry selectably coupled to the array of memory cells; a plurality of first input/output (I/O) lines configured as a data path that couples the sensing circuitry to a compute unit, wherein the compute unit includes a plurality of logic stripes; and one or more controllers associated with the compute unit, wherein the one or more controllers are configured to cause a first transfer of first data from a first portion of the sensing circuitry to a first logic stripe of the plurality of logic stripes via the plurality of first I/O lines and a second transfer of second data from a second portion of the sensing circuitry to a second logic stripe of the plurality of logic stripes via the plurality of first I/O lines, wherein the first logic stripe performs a first number of operations comprising a first type of computation on the first data simultaneously with the second logic stripe performing a second number of operations comprising a second type of computation different from the first type of computation on the second data, wherein results of the first number of operations or the second number of operations, or both, are stored in the array of memory cells without enabling one or more second lines to transfer the results from the array of memory cells to circuitry external to the array of memory cells (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use. The claims do not define what a first duration is and therefore the examiner considers any duration to be the first duration and the system of Matsumura et al. discloses performing multiple adds across many add units and the results of the fuller adder are sent to other functional blocks. This is done for multiple commands. Matsumura et al. discloses, in fig. 10 for example, that multiple pieces of data go through the selectors (operations) together, sense amplifiers (operations) together, full adder (operations) together and tri-state buffer circuit (operations) together. Col. 14 lines 16-22 state that the operation circuit may be comprised of any elements having a bit slice structure will produce the same effects as the full adder. That includes adders, subtractors, ALUs and multipliers. The input data into the memory cell arrays can be from data operation results. Data can be stored in the memory array without enabling a line to transfer the results out of the array, at the time the results are being stored in the memory array. This second line could also just not be the I/O line that is used to do transfers out of the memory array.).
Consider claim 29, Matsumura et al. discloses the apparatus of claim 28, wherein the one or more controllers are configured to; direct performance of a first operation on the first data using the first logic stripe of a first portion of the plurality of logic stripes during a first duration; and direct performance of a second operation on a result of the first operation using a third logic stripe of the first portion of the plurality of logic stripes during the first duration (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use.).
Consider claim 30, Matsumura et al. discloses the apparatus of claim 29, wherein the one or more controllers are further configured to: direct movement of the result of the first operation from the first logic stripe to the third logic stripe of the first portion of the plurality of logic stripes in response to completion of the first operation (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches both, the carry output of one adder is the input to another adder and also that the results of the fuller adder are sent to another functional block for use.).
Consider claim 31, Matsumura et al. discloses the apparatus of claim 29, wherein the one or more controllers are further configured to interrupt performance of the second operation on the third logic stripe of the first portion of the plurality of logic stripes and direct the result of the first operation to the array of memory cells (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, whatever operation is waiting on the completion of the fuller adder is considered to be interrupted.).
Consider claim 32, Matsumura et al. discloses the apparatus of claim 29, wherein the one or more controllers are further configured to interrupt performance of the second operation on the third logic stripe of the first portion of the plurality of logic stripes and direct the result of the first operation to the third logic stripe of the first portion of the plurality of logic stripes (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, whatever operation is waiting on the completion of the fuller adder is considered to be interrupted.).
Consider claim 33, Matsumura et al. discloses the apparatus of claim 29, wherein the one or more controllers are further configured to: direct movement of the second data from the array of memory cells to the second logic stripe of a second portion of the plurality of logic stripes in the data path via the plurality of first I/O lines during the first duration (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches both, the carry output of one adder is the input to another adder and also that the results of the fuller adder are sent to another functional block for use.).
Consider claim 34, Matsumura et al. discloses the apparatus of claim 33, wherein the one or more controllers are further configured to: direct performance of a third operation on the second data using the second logic stripe of the second portion of the plurality of logic stripes during a second duration (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches both, the carry output of one adder is the input to another adder and also that the results of the fuller adder are sent to another functional block for use.).
Consider claim 35, Matsumura et al. discloses the apparatus of claim 34, wherein the one or more controllers are further configured to: direct movement of the result of the third operation from the second logic stripe of the second portion of the plurality of logic stripes to a fourth logic stripe of the second portion of the plurality of logic stripes in response to completion of the first operation (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches both, the carry output of one adder is the input to another adder and also that the results of the fuller adder are sent to another functional block for use.).
Consider claim 36, Matsumura et al. discloses a method, comprising: transferring data from sensing circuitry selectably coupled to an array of memory cells to a compute unit via a plurality of first input/output (I/O) lines configured as a data path that couples the sensing circuitry to the compute unit; performing, during a first duration, a first number of operations comprising a first type of computation on a first portion of the data transferred from the sensing circuitry to the compute unit via the plurality of first I/O lines; performing, during the first duration and simultaneously with the first number of operations, a second number of operations comprising a second type of computation different from the first type of computation on a second portion of the data transferred from the sensing circuitry to the compute unit via the plurality of first IO lines; and storing results of the first number of operations or the second number of operations, or both, in the array of memory cells without enabling one or more second lines to transfer the results from the array of memory cells to circuitry external to the array of memory cells (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use. The claims do not define what a first duration is and therefore the examiner considers any duration to be the first duration and the system of Matsumura et al. discloses performing multiple adds across many add units and the results of the fuller adder are sent to other functional blocks. This is done for multiple commands. Matsumura et al. discloses, in fig. 10 for example, that multiple pieces of data go through the selectors (operations) together, sense amplifiers (operations) together, full adder (operations) together and tri-state buffer circuit (operations) together. Col. 14 lines 16-22 state that the operation circuit may be comprised of any elements having a bit slice structure will produce the same effects as the full adder. That includes adders, subtractors, ALUs and multipliers. The input data into the memory cell arrays can be from data operation results. Data can be stored in the memory array without enabling a line to transfer the results out of the array, at the time the results are being stored in the memory array. This second line could also just not be the I/O line that is used to do transfers out of the memory array.).
Consider claim 37, Matsumura et al. discloses the method of claim 36, further including performing the first number of operations using a first portion of logic stripes of a plurality of logic stripes included in the compute unit (Fig. 10 and 12).
Consider claim 38, Matsumura et al. discloses the method of claim 37, further including transferring the first portion of the data from the array of memory cells to the first portion of logic stripes (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use.).
Consider claim 39, Matsumura et al. discloses the method of claim 37, further including performing the second number of operations using a second portion of logic stripes of the plurality of logic stripes included in the compute unit (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. teaches a system with a processor, memory array, I/O lines connected to sensing circuitry. Commands are received, addition operations using a full adder (made of many add units) are performed and results returned. The carry output of one adder is the input to another adder and also the results of the fuller adder are sent to another functional block for use.).
Consider claim 40, Matsumura et al. discloses the method of claim 39, further including transferring the second portion of the data from the array of memory cells to the second portion of logic stripes (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59).
Consider claim 41, Matsumura et al. discloses the method of claim 36, wherein the first number of operations comprises a first logical operation and the second number of operations comprises a second logical operation different from the first logical operation (Fig. 10 and 12, Col. 1 lines 25-28 and 44-48, Col. 2 lines 37-41 and 50-56, Col. 3 lines 17-23, Col. 6 lines 61-68, Col. 8 lines 67-68, Col. 9 lines 1-4 and 18-19, Col. 12 lines 47-59, Matsumura et al. discloses, in fig. 10 for example, that multiple pieces of data go through the selectors (operations) together, sense amplifiers (operations) together, full adder (operations) together and tri-state buffer circuit (operations) together. Col. 14 lines 16-22 state that the operation circuit may be comprised of any elements having a bit slice structure will produce the same effects as the full adder. That includes adders, subtractors, ALUs and multipliers.).
Response to Arguments
Applicant's arguments filed 12/16/2025 have been fully considered but they are not persuasive.
The arguments pertain to the new claim amendments/new claim, which have been addressed in the appropriate claim rejections above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2136