Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s submission filed 6/29/23 has been entered. Claims 1-18 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/29/23 , 2/21/25 and 8/18/25 have been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 13, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over SUMBUL et al. (US 20180181861 A1), in view of XIE et al. (US 20150372746 A1).
Re-claims 1, 2, SUMBUL et al. teach A neuromorphic interface system, the system comprising:
--a first neuron cluster configured to output a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation; and --a first interface circuit configured to store the first neuron data and to output a first response, in response to the first neuron request,
(see e.g. [0035] In some embodiments, the synapse core 204a receives a spike (or a spike request) from the neuron Na2, appropriately weights the spike, and transmits weighted spikes to the neurons Na3, Na6, Nb2, Nb4, Nc1, and Nc3. Because the synapse core 204a receives the spike request from the neuron Na2, from the perspective of the synapse core 204a, the neuron Na2 is a pre-synaptic neuron and the neurons Na3, Na6, Nb2, Nb4, Nc1, and Nc3 are post-synaptic neurons.
[0038] In some embodiments, when the pre-synaptic neuron Na2 is to transmit a spike to the post-synaptic neuron Na3, Na6, Nb2, etc., the neuron Na2 transmits an unweighted spike request 302 (henceforth also referred to as a “request 302”) to the synapse core 204a. The request 302 is unweighted because no weight has so far been applied to the spike request 302 (e.g., since the spike request 302 is utilized for delivering spikes from a single pre-synaptic neuron to multiple post-synaptic neurons through multiple synapses, each with their own corresponding synaptic weight).
[0055] In some embodiments, the synapse core 204a further comprises a memory 304 storing a plurality of synaptic weights. For example, in response to receiving the request 302, the synapse core 204a transmits spikes Sa3, Sa6, Sb2, etc. to post-synaptic neurons Na3, Na6, Nb2, etc., respectively. The spikes Sa3, Sa6, Sb2, etc. are weighted by the synapse core 204a using synaptic weights, e.g., before being transmitted to the respective neurons. The synaptic weights, for example, are stored in the memory 304.
0121] Clause 13. The synapse core of any of clauses 10-12, wherein the synapse core is to: associate a weight to the spike, prior to the transmission of the spike to the address of the post-synaptic neuron.
[0122] Clause 14. The synapse core of any of clause 13, further comprising: a memory to store the weight.)
SUMBUL et al. do not teach the following limitations as claimed.
However, XIE et al. teach ---wherein, the first neuron cluster is configured to output a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response, and-- wherein, before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response based on a fact that the first neuron data is stored.
2. The system of claim 1, wherein the first interface circuit is further configured to: output a first transmission signal including a first transmission request and first transmission data by performing a first transmission operation; and after outputting the first response, output the first transmission signal.
(see e.g. [0134] Upon receiving the information indicating that the data relay request is accepted from the relay device 100, the first communication device 200a may transmit the data to the relay device 100. The relay device 100 may store the received data according to identification information of the second communication device 200b.
[0135] After storing the received data, when the second communication device 200b performs the BLUETOOTH communication function according to the setup of the user or is located within the range of the short distance wireless communication connection of the relay device 100, the relay device 100 may establish the wireless communication connection with the second communication device 200b.)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify SUMBUL et al., and include the steps cited above, as taught by XIE et al., so that the relay device 100 may efficiently control the file transfer between the two communication devices (see e.g.[0174]).
Re-claim 3, SUMBUL et al. teach --The system of claim 2, wherein the first neuron cluster includes a plurality of neuron circuits and a plurality of synaptic circuits, and wherein the first neuron signal is a signal generated as a first neuron circuit among the plurality of neuron circuits fires.
( see e.g. [0028] In some embodiments, a synapse 104 from a first neuron to a second neuron (e.g., from the neuron Na2 to the neuron Nc3) may operate to transmit signals (e.g., spikes) from an output of the first neuron Na2 to an input of the second neuron Nc3.
[0027] In some embodiments, neurons N may be implemented using circuits or logic that receive inputs, integrate inputs into a membrane potential, and decay a membrane potential. In some embodiments, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in an example, neurons N may include comparator circuits or logic that generate an output spike at an output when the result of applying a transfer function to the input exceeds the threshold. Once a neuron fires, the neuron may disregard previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value.
[0030] --. The system 100 may include circuitry or logic that allows synapses 104 to be allocated to different neurons as needed based on the neural network topology and neuron fan-in/fan-out.).
Re-claim 4, SUMBUL et al. teach --the system of claim 2, wherein the first interface circuit includes a first memory device, wherein the first memory device is enabled based on the first neuron request, and wherein, when the first memory device is enabled, the first neuron data is stored in the first memory device.
(see e.g. [0009] The teachings of this disclosure mitigate this issue by, for example, not storing at least part of connectivity information in the neuromorphic computing system. Rather, such connectivity information is generated on-the-fly, as and when required, thereby saving memory space.
[0042] In some embodiments, the synapse core 204a further comprises a connectivity storage 306 (also referred to herein as “storage 306”), which, for example, can be a memory or a set of register files.
[0055] In some embodiments, the synapse core 204a further comprises a memory 304 storing a plurality of synaptic weights. For example, in response to receiving the request 302, the synapse core 204a transmits spikes Sa3, Sa6, Sb2, etc. to post-synaptic neurons Na3, Na6, Nb2, etc., respectively. The spikes Sa3, Sa6, Sb2, etc. are weighted by the synapse core 204a using synaptic weights, e.g., before being transmitted to the respective neurons. The synaptic weights, for example, are stored in the memory 304.)
Re-claim 5, SUMBUL et al. teach The system of claim 4, further comprising: a second interface circuit configured to store the first transmission data and to output a second response, in response to the first transmission request,
(see e.g. [0039] Merely as an example, if a pre-synaptic neuron is connected to more than one synapse core (e.g., as discussed with respect to FIGS. 2B-2C, where the neuron Na2 is connected to more than one synapse core), then the pre-synaptic neuron can transmit, to each connected synapse core a corresponding unweighted spike request. For purposes of FIG. 3, it is assumed that the pre-synaptic neuron Na2 is transmitting the request 302 to the synapse core 204a, e.g., for eventual transmission of weighted spikes to post-synaptic neurons of the cores 102a, 102b, and 102c.)
[0121] Clause 13. The synapse core of any of clauses 10-12, wherein the synapse core is to: associate a weight to the spike, prior to the transmission of the spike to the address of the post-synaptic neuron.
[0122] Clause 14. The synapse core of any of clause 13, further comprising: a memory to store the weight.)
SUMBUL et al. do not teach the following limitations as claimed.
However, XIE et al. teach --- wherein the first interface circuit is configured to output a second transmission signal including a second transmission request and second transmission data by performing a second transmission operation, in response to the second response, and wherein, before the first transmission data is transmitted to the second neuron cluster, the second interface circuit outputs the second response in response to a fact that the first transmission data is stored.
(see e.g. [0134] Upon receiving the information indicating that the data relay request is accepted from the relay device 100, the first communication device 200a may transmit the data to the relay device 100. The relay device 100 may store the received data according to identification information of the second communication device 200b.
[0135] After storing the received data, when the second communication device 200b performs the BLUETOOTH communication function according to the setup of the user or is located within the range of the short distance wireless communication connection of the relay device 100, the relay device 100 may establish the wireless communication connection with the second communication device 200b.)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify SUMBUL et al., and include the steps cited above, as taught by XIE et al., so that the relay device 100 may efficiently control the file transfer between the two communication devices (see e.g.[0174]).
Re-claim 6, SUMBUL et al. teach --The system of claim 5, wherein the second interface circuit is further configured to: output a first routing signal including a first routing request and first routing data by performing a first routing operation; and after outputting the second response, output the first routing signal.
(see e.g. [0119] Clause 11. -- wherein the mapping logic is to: receive a second request, the second request comprising the identification of the post-synaptic neuron that generated the second request; access a second seed number based on the identification of the post-synaptic neuron; and map the second seed number to the identification of the pre-synaptic neuron.
[0120] Clause 12. The synapse core of clause 11, wherein: the mapping logic is to (i) map the seed number to the identification of the post-synaptic neuron request using at least in part a first mathematical function, and (ii) map the second seed number to the identification of the pre-synaptic neuron using at least in part a second mathematical function, wherein the second mathematical function is an inverse of the first mathematical function.
[0121] Clause 13. The synapse core of any of clauses 10-12, wherein the synapse core is to: associate a weight to the spike, prior to the transmission of the spike to the address of the post-synaptic neuron.)
Re-claim 7, SUMBUL et al. anticipate - The system of claim 6, wherein the second interface circuit further includes a second memory device, wherein the second memory device is enabled based on the first transmission request, and wherein, when the second memory device is enabled, the first transmission data is stored in the second memory device.
(see e.g. [0055] In some embodiments, the synapse core 204a further comprises a memory 304 storing a plurality of synaptic weights. For example, in response to receiving the request 302, the synapse core 204a transmits spikes Sa3, Sa6, Sb2, etc. to post-synaptic neurons Na3, Na6, Nb2, etc., respectively. The spikes Sa3, Sa6, Sb2, etc. are weighted by the synapse core 204a using synaptic weights, e.g., before being transmitted to the respective neurons. The synaptic weights, for example, are stored in the memory 304.)
[0010] When the synapse core is to transmit spikes from a pre-synaptic neuron to a plurality of post-synaptic neurons, the synapse core generates (e.g., on-the-fly) the addresses of the plurality of post-synaptic neurons from the seed numbers. For example, the synapse core uses a finite filed mathematical function (e.g., a Galois field function) to map the addresses of the plurality of post-synaptic neurons from the seed numbers.
The Examiner notes that SUMBUL et al. teach a plurality of synapses (second interface) with memories and the synapses transmit data.
Re-claim 8, SUMBUL et al., in view of XIE et al. do not explicitly teach - The system of claim 7, further comprising: a third interface circuit configured to store the first routing data and to output a third response, in response to the first routing request, wherein the second interface circuit is configured to output a second routing signal including a second routing request and second routing data by performing a second routing operation, in response to the third response, and wherein, before the first routing data is transmitted to the second neuron cluster, the third interface circuit outputs the third response in response to a fact that the first routing data is stored.
However, SUMBUL et al. teach a plurality of synapses receiving requests from a plurality of neurons, storing the requests and routing the requests to the correct neurons. (see e.g. [0035, 0039]
Therefore, it is considered an obvious variation of SUMBUL et al. to route data in the manner claimed above.
Claim 13 recites similar limitations as claim 1 and is therefore rejected under the same arts and rationale.
Re-claims 16, 18, SUMBUL et al. teach --An operating method of an interface circuit including a memory device and configured to mediate communication between a first circuit and a second circuit, the method comprising: receiving a first input signal from the first circuit;
(see e.g. [0035] In some embodiments, the synapse core 204a receives a spike (or a spike request) from the neuron Na2, appropriately weights the spike, and transmits weighted spikes to the neurons Na3, Na6, Nb2, Nb4, Nc1, and Nc3. Because the synapse core 204a receives the spike request from the neuron Na2, from the perspective of the synapse core 204a, the neuron Na2 is a pre-synaptic neuron and the neurons Na3, Na6, Nb2, Nb4, Nc1, and Nc3 are post-synaptic neurons.
--storing input data, which is included in the first input signal, in the memory device and transmitting a first response to the first circuit;
[0055] In some embodiments, the synapse core 204a further comprises a memory 304 storing a plurality of synaptic weights. For example, in response to receiving the request 302, the synapse core 204a transmits spikes Sa3, Sa6, Sb2, etc. to post-synaptic neurons Na3, Na6, Nb2, etc., respectively. The spikes Sa3, Sa6, Sb2, etc. are weighted by the synapse core 204a using synaptic weights, e.g., before being transmitted to the respective neurons. The synaptic weights, for example, are stored in the memory 304.
[0122] Clause 14. The synapse core of any of clause 13, further comprising: a memory to store the weight.)
Sumbul et al. do not teach the following limitation as claimed.
However, XIE et al. teach - determining a state of the second circuit based on a second response transmitted from the second circuit; and generating an output signal based on the state of the second circuit.
(see e.g. [0016] The processor is further configured to store the data received from the first communication device, and then, if the short distance wireless communication connection is established between the second communication device and the short distance wireless communication unit, transmit the stored data to the second communication device.
0212] In operation S1240, the first communication device 200a may transmit the relevant file to the relay device 100.
0018] Upon receiving the data relay request, the processor is configured to transmit to the second communication device an acknowledge request requesting the second communication device to acknowledge whether to receive the data, to receive from the second communication device a response to the acknowledge request, and to transmit the data to the second communication device based on the response.
----The method of claim 17, wherein the first response is a signal for requesting the first circuit to generate a second input signal following the first input signal.
(see e.g. [0134] Upon receiving the information indicating that the data relay request is accepted from the relay device 100, the first communication device 200a may transmit the data to the relay device 100. The relay device 100 may store the received data according to identification information of the second communication device 200b.
The Examiner notes that the receipt of information from the relay device prompting the first communication device to transmit the data is considered a request.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumbul et al., and include the steps cited above, as taught by Xie et al., so that the relay device 100 may efficiently control the file transfer between the two communication devices (see e.g.[0174]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumbul et al., in view of XIE et al., and include the steps cited above, as taught by HAN et al., in order to (see e.g.[0174]).
Re-claim 17, Sumbul et al. teach --The method of claim 16, wherein the first circuit includes at least one neuron circuit, and wherein the first input signal is a signal generated as a first neuron circuit among the at least one neuron circuit fires.
(see e.g. [0010] For example, a pre-synaptic neuron may send spikes to a plurality of post-synaptic neurons via a synapse core.
- [0024] In some embodiments, a neuron can communicate with one or more other neurons. For example, the neuron Na2 in FIG. 1 is illustrated to transmit signals or spikes to neurons Na3 and Na6 of the core 102a, neurons Nb2 and Nb4 of the core 102b, and neurons Nc1 and Nc3 of the core 102c.)
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over SUMBUL et al. (US 20180181861 A1), in view of XIE et al. (US 20150372746 A1), in further view of HAN et al. (US 20160155421 A1).
Re-claims 9, 10, SUMBUL et al., in view of XIE et al. do not teach the limitations as claimed.
However, HAN et al. teach— The system of claim 8, wherein the third interface circuit is further configured to: output a first reception signal including a first reception request and first reception data by performing a first reception operation; and after outputting the third response, output the first reception signal. 10. The system of claim 9, wherein the third interface circuit includes a third memory device, wherein the third memory device is enabled based on the first routing request, and wherein, when the third memory device is enabled, the first routing data is stored in the third memory device.
(see e.g. [0185] Referring to FIG. 17, the third TED 800 may include a reception interface 810, a timing generator 820, a line memory 830, an interface 840, a mode signal generator 850, a sync controller 860, a selection circuit 870, a data driver 880 and a mode detector 890.
[0186] The reception interface 810 may receive the third image data DTA33, the third control signal CTL33 and the external clock signal ECLK. The reception interface 810 may provide the external clock signal ECLK and the third control signal CTL33 to the timing generator 820 and may provide the third image data DTA330 to the line memory 830.)
[0187] The line memory 830 may store the third image data DTA33 on an image line basis. The line memory 830 may provide the selection circuit 870 with the stored third image data DTA33 on an image line basis.).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumbul et al., in view of XIE et al., and include the steps cited above, as taught by HAN et al., in order to control data transmission (see e.g.[0236]).
Re-claims 11, SUMBUL et al., teach The system of claim 10, wherein the first interface circuit is a transmission interface circuit for delivering information included in the first neuron signal to the second neuron cluster, wherein the second interface circuit is a router circuit for selecting a path for delivering the information included in the first neuron signal to the second neuron cluster, and
(see e.g. [0030] In some embodiments, the system 100 may include a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect synapses 104 to neurons N. The system 100 may include circuitry or logic that allows synapses 104 to be allocated to different neurons as needed based on the neural network topology and neuron fan-in/fan-out. For example, the synapses 104 may be connected to the neurons N using an interconnect fabric, such as network-on-chip, or with dedicated connections. Synapse interconnections and components thereof may be implemented using circuitry or logic.
[0027] In some embodiments, neurons N may be implemented using circuits or logic that receive inputs,
[0078] The memory 304 accesses the associated entries and outputs the synaptic weights, which are output via a selection circuitry 534 (which, for example, is controlled by a signal 514). The output of the circuitry 534 is the synaptic weights (e.g., weight Aa3 for the spike from the pre-synaptic neuron Na2 to the post-synaptic neuron Na3). The weights output by the circuitry 534 and the post-synaptic neuron addresses output by the block 582 are combined to form the spikes Sa3, Sa6, Sb2, etc., e.g., as also discussed with respect to FIG. 3.).
SUMBUL et al., in view of XIE et al. do not teach the limitations as claimed.
However, HAN et al. teach -- wherein the third interface circuit is a reception interface circuit that receives the information included in the first neuron signal and delivers the information to the second neuron cluster.
(see e.g. [0185] Referring to FIG. 17, the third TED 800 may include a reception interface 810, a timing generator 820, a line memory 830, an interface 840, a mode signal generator 850, a sync controller 860, a selection circuit 870, a data driver 880 and a mode detector 890.
[0186] The reception interface 810 may receive the third image data DTA33, the third control signal CTL33 and the external clock signal ECLK. The reception interface 810 may provide the external clock signal ECLK and the third control signal CTL33 to the timing generator 820 and may provide the third image data DTA330 to the line memory 830.)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumbul et al., in view of XIE et al., and include the steps cited above, as taught by HAN et al., in order to control data transmission (see e.g.[0236]).
Re-claim 12, SUMBUL et al. teach The system of claim 11, wherein each of the first to third interface circuits operates in an asynchronous manner.
(see e.g. [0070] In some embodiments, the spikes Sa3, . . . , Sc3 are transmitted respectively to the post-synaptic neurons Na3, . . . , Nc3 in parallel. In some other embodiments, the spikes Sa3, . . . , Sc3 are transmitted respectively to the post-synaptic neurons Na3, Nc3 serially, e.g., in a time multiplexed manner.).
Claims 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over SUMBUL et al. (US 20180181861 A1), in view of XIE et al. (US 20150372746 A1), in further view of Takeda et al. (US 6922090 B2).
Re-claim 14, SUMBUL et al., in view of XIE et al. do not teach the limitations as claimed.
However, Takeda et al. teach--The interface circuit of claim 13, further comprising: an inverter element configured to receive the second response and to output an inverted second response obtained by inverting the second response; and a muller-C element connected to an output terminal of the inverter element and a first output terminal of the memory device and configured to output a processing enable signal based on the first response and the inverted second response,
(see e.g. (28) This control circuit of the micro-pipeline has the left side block 20-1 and the right side block 20-2 shown in FIG. 8. The left side block 20-1 has a Muller C element with an inverter 10-1 having the same configuration as shown in FIG. 7 where the request event Req (1), which is a transition signal, and the response event Ack (2), which is a transition signal from the right side block 20-2, are input. From the output terminal of this Muller C element with an inverter 10-1, the response event Ack (1), which is a transition signal, is output. The delay element 21-1 which delays the response event Ack (1) for the delay time DELAY 1 and outputs the request event Req (2), which is a transition signal, is connected to the output terminal of the Muller C element with an inverter 10-1.
wherein the memory device is further configured to: transmit the first response to the first circuit and the muller-C element through the first output terminal; and transmit the first input data thus stored, to the processing unit through a second output terminal, and wherein the processing unit is connected to an output terminal of the muller-C element and the second output terminal of the memory device, and is enabled based on the processing enable signal to generate the output signal.
(38) In FIG. 1, in the first Muller C element with an inverter 10-1, a request event ReqIn, which is the first transition signal, is input to the first positive input terminal, a feedback signal S, which is a transition signal, is input to the second negative input terminal, and a response event AckOut, which is the second transition signal, is output from the first output terminal. The first input terminal of the first gate circuit (e.g. two input OR gate) 41-1 is connected to the first output terminal of the Muller C element with an inverter 10-1, and the device enabling signal Grant, which is the first control signal, is input to the second input terminal, and the second output terminal is connected to the second positive input terminal of the second Muller C element with an inverter 10-2. In the Muller C element with an inverter 10-2, a response event AckIn, which is the third transition signal, is input to the second negative input terminal, and a feedback signal S is output from the third output terminal.
Claim 15 recites similar limitations as claim 14 and is therefore rejected under the same arts and rationale.
Furthermore, Takeda et al. teach a local clock generator connected to an output terminal of the muller-C element and configured to output a local clock signal based on the clock enable signal,
and wherein the processing unit is connected to an output terminal of the local clock generator and the second output terminal of the memory device and is further configured to output the output signal based on the local clock signal.
(see e.g. (33) In this sense, in the transition signaling circuit of the present invention, the loop comprised of the OR gate 41-1 and the Muller C element with an inverter 10-2 corresponds to the latch circuit of clocked logic.
(24) As Document 1 states, a pipeline is referred to as a device configuration to process data in a work flow. In the pipeline, data is stored and processed. The pipeline is operated by clock control (each section is operated according to a clock distributed from the outside) or is driven by an event (each section is independently operated each time a local event is generated).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Sumbul et al., in view of XIE et al., and include the steps cited above, as taught by Takeda et al., in order to control the pipeline (see e.g.(3)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CHU et al. (US 20160004964 A1)
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/LUNA CHAMPAGNE/Primary Examiner, Art Unit 3627 February 10, 2026