DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/25/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/25/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements is considered by the examiner.
Response to Arguments
2 Applicant’s arguments filed 03/25/2026 with respect to claim(s) 1-31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1,4,6, 8,10,12-15, 19-21, and 23-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 also has an antecedent basis issue with “one of the second wiring lines” introduced in lines 6-7 and again in lines 9-10.
Claims 4, 6,8, 10, 12 -14 inherit the same deficiency due to dependency on claim 1.
Claim 15 also has an antecedent basis issue with “one of the second wiring lines” introduced in lines 6-7 and again in lines 9-10.
Claims 19 -21 inherit the same deficiency due to dependency on claim 15.
Claim 23 recites the limitation “one of the one or more first wiring lines;" in line 6. In the second to last line of the claim, the claim recites “one of the one or more first wiring lines” It is unclear whether these refer to the same “one of the one or more first wiring lines recited in line 6.
Claim 23 recites the limitation “one of the second wiring lines;" in line 6. In lines 8-9 and 12 the claim recites “one of the second wiring lines” It is unclear whether these refer to the same “one of the second wiring lines recited in line 6.
Claims 24 -27 inherit the same deficiency due to dependency on claim 23.
For purposes of prosecution, “one of the one or more first wiring lines” is interpreted to mean the one of the one or more first wiring lines of line 6
For purposes of prosecution, “one of the second wiring lines” is interpreted to mean the one of the second wiring lines of line 6.
Claims 28-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 28 recites the limitation “a plurality of first wiring lines;" in line 2. In lines 4, 6 and second last of the claim, the claim recites “first wiring lines” and “one of the first wiring lines” It is unclear whether these refer to the same “plurality of first wiring lines recited in line 2.
Claim 28 recites the limitation “one or more second wiring lines;" in line 3. In lines 6, 9, 12, 23, 25, and fourth last line, the claim recites “one or more second wiring lines;” It is unclear whether these refer to the same “one or more second wiring lines” recited in line 3.
Claims 29 -32 inherit the same deficiency due to dependency on claim 28.
For purposes of prosecution, “a plurality of first wiring lines” is interpreted to mean the plurality of first wiring lines of line 2.
For purposes of prosecution, “one or more second wiring lines” is interpreted to mean the one of the second wiring lines of line 3.
Claim Rejections - 35 USC § 103
3 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4 Claims 1, 4, 6, 8, 10, 12-15, 19-21 are rejected under 35 U.S.C. 103(a) as
being unpatentable over Westhues et al. (US 2011/0309956 A1) in view of Crastes et al. (US 20110186737 A1).
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5 Regarding to claim 1, Westhues discloses an element array circuit comprising:
one or more first wiring lines (Figs. 1-5 Item 210 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch. Sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]).
a plurality of second wiring lines (Figs. 1-5 Item 220 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch. Sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]), the second wiring lines each extending in a direction different from a direction in which the one or more first wiring lines each extend (Figs. 1-5 Item 210 & 220 discloses Sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]).
a plurality of (Figs. 1-5 Item 212 discloses a plurality of first resistors including resistor 212 in Paragraph [0017]), or semiconductor elements, the resistors or semiconductor elements each being coupled to both one of the one or more first wiring lines (Figs. 1-5 Item 210 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch. Sensor matrix 120 comprises a plurality of first conductors including conductor 210in Paragraph [0017]) and one of the second wiring lines (Figs. 1-5 Item 220 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch., a plurality of second conductors including conductor 220 in Paragraph [0017]);
one or more operational amplifiers (Figs. 1-5 Item 260 discloses a plurality of comparators 260 which act as operational amplifiers in Paragraph [0020 & 0029]) each including a positive input terminal, a negative input terminal, and an output terminal, the negative input terminal being couplable to one of the second wiring lines; and
one or more switchers (Figs. 1-5 Item 234 discloses each sensor 230 includes a switch 234 in series with a matrix resistor 232 in Paragraph [0019]) and one of the one or more operational amplifiers (Figs. 1-5 Item 260 discloses a plurality of comparators 260 which act as operational amplifiers in Paragraph [0020 & 0029]) and each configured to come into either a conducting state or a nonconducting state (Figs. 1-5 Item 234 discloses FIG. 2 illustrates a schematic of an example embodiment of sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch in Paragraph [0017]).
However Westhues does not explicitly teach one or more conversion elements each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the one or more second wiring lines that is coupled to the negative input terminal into a voltage; and
one or more switchers each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to come into either a conducting state or a nonconducting state.
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However, Crastes teaches one or more conversion elements (Figs. 1-2 Item 20 & 21 discloses read member 20 comprises for its part an integrator 21 in Paragraph [0067]) each coupled to the negative input terminal (Figs. 1-2 Item 28 negative terminal) and the output terminal of corresponding one of the one or more operational amplifiers (Figs. 1-2 Item 28 discloses a capacitor 30 connected between the inverting input (−) of the amplifier 28 and the output thereof; and a reset switch 32 in Paragraph [0070]) and each configured to convert a current flowing through one of the one or more second wiring lines (Figs. 1-2 Item 12 or 14); that is coupled to the negative input terminal into a voltage (Figs. 1-2 Item 28 negative terminal); and
one or more switchers (Figs. 1-2 Item 32 discloses a capacitor 30 connected between the inverting input (−) of the amplifier 28 and the output thereof; and a reset switch 32 in Paragraph [0070]) each coupled to one of the one or more conversion elements (Figs. 1-2 Item 21) in parallel between the negative input terminal (Figs. 1-2 Item 28 negative terminal)and the output terminal of corresponding one of the one or more operational amplifiers (Figs. 1-2 Item 28 discloses a capacitor 30 connected between the inverting input (−) of the amplifier 28 and the output thereof; and a reset switch 32 in Paragraph [0070]) and each configured to come into either a conducting state or a nonconducting state (Figs. 1-2 Item 28 discloses the reset switch 32, which is in an on-state subsequent to a discharge cycle of the capacitor 30, is switched into the off-state by adjusting the “Reset” control to an appropriate value in Paragraph [0073])
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the common feature of a sensor matrix with a first set of conductors arranged in rows and a second set of conductors arranged in column as taught by Westhues to further utilize method for controlling the resistance matrix as taught by Crastes in order to provide a resistance is controlled, particularly for the purposes of reducing remanence phenomena n Paragraph [0002]).
6 Regarding to claim 4, Westhues discloses the element array circuit according to claim 1, further comprising
a second wiring line selector (Figs. 1-5 Item 234) configured to select one of the second wiring lines and to couple the one of the second wiring lines (Figs. 1-5 Item 210 & 220) selected to the negative input terminal (Figs. 1-5 Item 260 has negative input terminal).
7 Regarding to claim 6, Westhues discloses the element array circuit according to claim 1, wherein the one or more operational amplifiers (Figs. 1-5 Item 260) comprise a plurality of the operational amplifiers (Figs. 1-5 Item 260),
the one or more switchers (Figs. 1-5 Item 234) comprise a plurality of the switchers (Figs. 1-5 Item 234),
the operational amplifiers (Figs. 1-5 Item 260) are each coupled to corresponding one of the second wiring lines (Figs. 1-5 Item 220),
the switchers (Figs. 1-5 Item 234) are each coupled to corresponding one of the operational amplifiers (Figs. 1-5 Item 260), and
However Westhues does not explicitly teach the one or more conversion elements comprise a plurality of the conversion elements,
the conversion elements are each coupled to corresponding one of the operational amplifiers.
However, Crastes teaches the one or more conversion elements (Figs. 1-2 Item 21) comprise a plurality of the conversion elements (Figs. 1-2 Item 21),
the conversion elements (Figs. 1-2 Item 21) are each coupled to corresponding one of the operational amplifiers (Figs. 1-2 Item 28)
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the common feature of a sensor matrix with a first set of conductors arranged in rows and a second set of conductors arranged in column as taught by Westhues to further utilize method for controlling the resistance matrix as taught by Crastes in order to provide a resistance is controlled, particularly for the purposes of reducing remanence phenomena n Paragraph [0002]).
8 Regarding to claim 8, Westhues discloses the element array circuit according to claim 1, wherein the one or more first wiring lines (Figs. 1-5 Item 210) comprise a plurality of the first wiring lines (Figs. 1-5 Item 210), and the (Figs. 1-5 Item 212 discloses a plurality of first resistors including resistor 212 in Paragraph [0017]) are each coupled to both one of the first wiring lines (Figs. 1-5 Item 210) and one of the second wiring lines (Figs. 1-5 Item 220).
9 Regarding to claim 10, Westhues discloses the element array circuit according to claim 1. wherein each of the one or more conversion elements (Figs. 1-5 Item 310) is comprises a capacitor (Figs. 1-5 Item 310) is, a first resistor (Figs. 1-5 Item 212) is, or a first semiconductor element (Figs. 1-5 Item 140).
10 Regarding to claim 12, Westhues discloses the electromagnetic wave sensor comprising the element array circuit (Figs. 1-5 Item 120 discloses sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]) according to claim 1.
11 Regarding to claim 13, Westhues discloses a temperature sensor (Figs. 1-5 Item 240 discloses scanning sensing circuit 240 scans resistors 232 for characteristics such as heat or temperature in Paragraph [0019]) comprising the element array circuit (Figs. 1-5 Item 120 discloses sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]) according to claim 1.
12 Regarding to claim 14, Westhues discloses a strain sensor (Figs. 1-5 Item 240 discloses scanning sensing circuit 240 scans resistors 232 for characteristics such as strain in Paragraph [0019]) comprising the element array circuit (Figs. 1-5 Item 120 discloses sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]) according to claim 1.
13 Regarding to claim 15, Westhues discloses an element array circuit comprising:
a plurality of first wiring lines (Figs. 1-5 Item 210 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch. Sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]).;
one or more second wiring lines (Figs. 1-5 Item 220 discloses, a plurality of second conductors including conductor 220 in Paragraph [0017]), each extending in a direction different from a direction in which the first wiring lines each extend (Figs. 1-5 Item 220 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch. Sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]);
a plurality of (Figs. 1-5 Item 212 discloses a plurality of first resistors including resistor 212 in Paragraph [0017]), or semiconductor elements, the resistors or semiconductor elements each being coupled to both one of the one or more first wiring lines (Figs. 1-5 Item 210 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch. Sensor matrix 120 comprises a plurality of first conductors including conductor 210in Paragraph [0017]) and one of the second wiring lines (Figs. 1-5 Item 220 discloses sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch., a plurality of second conductors including conductor 220 in Paragraph [0017]);
one or more operational amplifiers (Figs. 1-5 Item 260 discloses a plurality of comparators 260 which act as operational amplifiers in Paragraph [0020 & 0029]) each including a positive input terminal, a negative input terminal, and an output terminal, the negative input terminal being couplable to one of the one or more second wiring lines (Figs. 1-5 Item 220);
one or more switchers (Figs. 1-5 Item 234 discloses each sensor 230 includes a switch 234 in series with a matrix resistor 232 in Paragraph [0019]) each coupled to one or more operational amplifiers (Figs. 1-5 Item 260 discloses a plurality of comparators 260 which utilize op-amp transimpedance amplifiers in Paragraph [0020 & 0029]) and each configured to come into either a conducting state or a nonconducting state (Figs. 1-5 Item 234 discloses FIG. 2 illustrates a schematic of an example embodiment of sensor matrix 120 configured to wake from a sleep state upon activation of a sensor matrix switch in Paragraph [0017]).
However Westhues does not explicitly teach one or more conversion elements each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the one or more second wiring lines that is coupled to the negative input terminal into a voltage; and
one or more switchers each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to come into either a conducting state or a nonconducting state.
However, Crastes teaches one or more conversion elements (Figs. 1-2 Item 20 & 21 discloses read member 20 comprises for its part an integrator 21 in Paragraph [0067]) each coupled to the negative input terminal (Figs. 1-2 Item 28 negative terminal) and the output terminal of corresponding one of the one or more operational amplifiers (Figs. 1-2 Item 28 discloses a capacitor 30 connected between the inverting input (−) of the amplifier 28 and the output thereof; and a reset switch 32 in Paragraph [0070]) and each configured to convert a current flowing through one of the one or more second wiring (Figs. 1-2 Item 12 or 14) lines that is coupled to the negative input terminal into a voltage (Figs. 1-2 Item 28 negative terminal)); and
one or more switchers (Figs. 1-2 Item 32 discloses a capacitor 30 connected between the inverting input (−) of the amplifier 28 and the output thereof; and a reset switch 32 in Paragraph [0070]) each coupled to one of the one or more conversion elements (Figs. 1-2 Item 21) in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers (Figs. 1-2 Item 28operational amplifiers), and each configured to come into either a conducting state or a nonconducting state (Figs. 1-2 Item 28 discloses the reset switch 32, which is in an on-state subsequent to a discharge cycle of the capacitor 30, is switched into the off-state by adjusting the “Reset” control to an appropriate value in Paragraph [0073])
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the common feature of a sensor matrix with a first set of conductors arranged in rows and a second set of conductors arranged in column as taught by Westhues to further utilize method for controlling the resistance matrix as taught by Crastes in order to provide a resistance is controlled, particularly for the purposes of reducing remanence phenomena n Paragraph [0002]).
14 Regarding to claim 19, Westhues discloses the electromagnetic wave sensor (Figs. 1-5 Item 120 & 240 discloses sensor matrix 120 and scanning sensing circuit 240 which operate electromagnetic wave sensor in Paragraph [0017 & 0024]) comprising the element array circuit (Figs. 1-5 Item 120 discloses sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]) according to claim 15.
15 Regarding to claim 20, Westhues discloses a temperature sensor (Figs. 1-5 Item 240 discloses scanning sensing circuit 240 scans resistors 232 for characteristics such as heat or temperature in Paragraph [0019]) comprising the element array circuit (Figs. 1-5 Item 120 discloses sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]) according to claim 15.
16 Regarding to claim 21, Westhues discloses a strain sensor (Figs. 1-5 Item 240 discloses scanning sensing circuit 240 scans resistors 232 for characteristics such as strain in Paragraph [0019]) comprising the element array circuit (Figs. 1-5 Item 120 discloses sensor matrix 120 comprises a plurality of first conductors including conductor 210, a plurality of second conductors including conductor 220 in Paragraph [0017]) according to claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT J ANDREWS whose telephone number is (571)272-6101. The examiner can normally be reached 10am-5pm.
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/BRENT J ANDREWS/Examiner, Art Unit 2858 /JENNIFER BAHLS/Primary Examiner, Art Unit 2853
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