DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 16-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thiery et al. [US 2004/0228053]. With respect to claim 16 , Thiery discloses a method, comprising: detecting a reverse polarity of a voltage source [ par. 0014-0015 , Fig. 3 ] , wherein the voltage source is configured to provide a voltage to a driver circuit [ VDD ] ; responsive to detecting the reverse polarity of the voltage source, turning on a first transistor [ par. 0017, 0019; i.e. M3 is normally off, however in response to a reverse connection M3 is turned on ] ; responsive to turning on the first transistor, turning on a second transistor [ par. 0019; responsive to M3 turning on, M1 is turned on ] ; and responsive to turning on the second transistor, turning on a third transistor, wherein the third transistor provides a path for a reverse polarity parasitic current in the third transistor [ par. 0020; responsive to M1 turning on M10 is turned on to provide an alternative path around body diode 10 A ] . With respect to claim 1 7 , Thiery further discloses providing the path for the reverse polarity parasitic current through the third transistor responsive to the reverse polarity of the voltage source [ par. 0020; responsive to M1 turning on M10 is turned on to provide an alternative path around body diode 10A ] . With respect to claim 1 9 , Thiery further discloses wherein turning on the first transistor includes providing a first voltage at a first terminal of the first transistor and providing a second voltage at a control terminal of the first transistor, wherein the first voltage is higher than the second voltage responsive to the voltage source being in reverse polarity [ par. 0017, i.e. VDD goes to 0/ground when turned on ] . With respect to claim 20 , Thiery further discloses wherein a diode is coupled between a control terminal of the second transistor and a load terminal, the load terminal coupled to the third transistor [ Fig. 3; see the diode between branches M2 and S2 ] . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thiery et al. [US 2004/0228053] as applied above, and further in view of Laraia [US 6,882,513] . With respect to claim 1 8 , Thiery discloses the second and third transistors are n-type [ as depicted with arrow out ], but fails to explicitly disclose wherein the first transistor is a P-type field effect transistor . First, a person having ordinary skill in the art is enabled to design a circuit with p-type and/ n-type mosfets as such a skill is considered routine in the art. However, looking at Laraia , which relates to a reverse protection circuit utilizing p-type and n-type mosfets , it is taught that a p-type transistor is connected to detect the reverse current and a following transistor in the circuit being n-type. Laraia details such a connection is beneficial based on the natural biasing of the transistors [ col. 7 line 60 to col. 8 line 25 ]. Therefore, it would have been obvious to a person having ordinary skill in the art before the filing date of the instant invention to modify Thiery to use a first transistor of p-type as taught by Laraia for the benefit of reducing the current flow required as explicitly stated by Laraia . Allowable Subject Matter Claims 1-15 are allowed. The following is an examiner’s statement of reasons for allowance: With respect to claims 1 and 10 , the prior art of record does not suggest or disclose the claimed combination of elements or steps as recited, most particularly the claimed , “ a second transistor having a control terminal coupled to the second terminal of the first transistor, having a first terminal coupled to the ground terminal, and having a second terminal … and a third transistor having a control terminal coupled to the second terminal of the second transistor, a first terminal coupled to the voltage terminal, and a second terminal coupled to the load terminal. ” Claims 2-9 and 11-15 depend from the claims above and are allowed for the same reasons. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 7,283,343 to Grose et al. relates to a integrated reverse battery protection circuit with a transistor that turns on in response to the reverse current, however, fails to disclose all three transistors connected as in claims 1/10 and three sequential transistor turning on as in claim 16. US 2019/0027945 to Gagnon et al. relates to a reverse current prevention and discloses three transistors operation in the prevention, however, fails to disclose the transistor connected as in claims 1/10 and only turns on two in sequential manner, with the third one being turned off to prevent the current from flowing. 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