DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgement is made of the response filed on 06/30/2026. No claims were amended to overcome the prior art and put them into condition for allowance, therefore a final rejection is repeated below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thiery et al. [US 2004/0228053].
With respect to claim 16, Thiery discloses a method, comprising: detecting a reverse polarity of a voltage source [par. 0014-0015, Fig. 3], wherein the voltage source is configured to provide a voltage to a driver circuit [VDD]; responsive to detecting the reverse polarity of the voltage source, turning on a first transistor [par. 0017, 0019; i.e. M3 is normally off, however in response to a reverse connection M3 is turned on]; responsive to turning on the first transistor, turning on a second transistor [par. 0019; responsive to M3 turning on, M1 is turned on]; and responsive to turning on the second transistor, turning on a third transistor, wherein the third transistor provides a path for a reverse polarity parasitic current in the third transistor [par. 0020; responsive to M1 turning on M10 is turned on to provide an alternative path around body diode 10A].
With respect to claim 17, Thiery further discloses providing the path for the reverse polarity parasitic current through the third transistor responsive to the reverse polarity of the voltage source [par. 0020; responsive to M1 turning on M10 is turned on to provide an alternative path around body diode 10A].
With respect to claim 19, Thiery further discloses wherein turning on the first transistor includes providing a first voltage at a first terminal of the first transistor and providing a second voltage at a control terminal of the first transistor, wherein the first voltage is higher than the second voltage responsive to the voltage source being in reverse polarity [par. 0017, i.e. VDD goes to 0/ground when turned on].
With respect to claim 20, Thiery further discloses wherein a diode is coupled between a control terminal of the second transistor and a load terminal, the load terminal coupled to the third transistor [Fig. 3; see the diode between branches M2 and S2].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thiery et al. [US 2004/0228053] as applied above, and further in view of Laraia [US 6,882,513].
With respect to claim 18, Thiery discloses the second and third transistors are n-type [as depicted with arrow out], but fails to explicitly disclose wherein the first transistor is a P-type field effect transistor.
First, a person having ordinary skill in the art is enabled to design a circuit with p-type and/ n-type mosfets as such a skill is considered routine in the art. However, looking at Laraia, which relates to a reverse protection circuit utilizing p-type and n-type mosfets, it is taught that a p-type transistor is connected to detect the reverse current and a following transistor in the circuit being n-type. Laraia details such a connection is beneficial based on the natural biasing of the transistors [col. 7 line 60 to col. 8 line 25].
Therefore, it would have been obvious to a person having ordinary skill in the art before the filing date of the instant invention to modify Thiery to use a first transistor of p-type as taught by Laraia for the benefit of reducing the current flow required as explicitly stated by Laraia.
Allowable Subject Matter
Claims 1-15 remain allowed for the reasons detailed in the prior office action.
Response to Arguments
Applicant's arguments filed 06/30/2026 have been fully considered but they are not persuasive.
Applicant argues on pages 6-8 that Thierry’s M1 is not turned on responsive to M3 being turned on, as claimed as a second transistor turning on responsive to a first transistor, and supports that assertion by arguing that M3 and M1 would turn on regardless of the status of each other in response to a reverse current being detected (M4 activating).
The Examiner respectfully disagrees with the argued line of logic. Specifically, the claim simply states “responsive”, whereas the argued logic requires specific order/steps to be taken (this is exactly the reason the apparatus was allowed and the method rejected). Applicant’s detailed arguments clearly set up the scenario where M4 is turned on, and then M3 and M1 are turned on (noting that applicant argues both M1 and M3 are turned on responsive to M4) and then M10 turned on. There is no requirement from the claim that one transistor has to be turned on before the other or that one transistor is specifically directly connected to the gate of another for example. There are a number of simple amendments that would have facilitated an interpretation under BRI as narrow as Applicant is arguing but as currently claimed Thierry’s set of transistors discloses third transistors being responsively turned on in the claimed manner under BRI.
In arguendo, even if Applicant’s arguments were persuasive (which they are not as argued above), Applicant writes their own new grounds of rejection where M4 would be a first transistor which responsive to being turned on, transistor M3/M1 is turned on, which responsive to M3/M1 being turned on, M10 is turned on. Exactly as claimed.
Therefore the rejection is proper, and thus maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANIEL R PELTON whose telephone number is (571)270-1761. The examiner can normally be reached M-F 9am to 5pm.
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/NATHANIEL R PELTON/Primary Examiner, Art Unit 2859
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