DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claims 10-17 and 19-20 require a dual laser chip in a mounting groove with deepening grooves this combination does not appear to be supported in either Chinese priority application. The PCT does appear to at least contain claims directed to the combination. Accordingly, these claims have been examined with an effective U.S. filing date of 05/27/2022. Information Disclosure Statement The information disclosure statement (IDS) submitted on 06/30/2023 was filed after the f iling date of th is application on 06/29/2023 . The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The Office has not considered Foreign Patent Documents cite no. 6 on the IDS filed 06/30/2023. 37 CFR 1.98(a)(2)(i) requires a legible copy of each foreign patent and 37 CFR 1.98(a)(3) requires either a concise explanation of relevance or a copy of an English translation. Applicant has submitted two translations of Foreign Patent Documents cite no. 6 but has not included a legible copy of the foreign patent document. Since applicant has not met the requirements under 37 CFR 1.98(a)(2)(i), the cite no. 6 on the IDS has been lined through. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claims 10-17 and 19-20 require a dual chip laser in a mounting groove with deepening grooves which is not shown together in any figure. Additionally, the dual chip laser is not shown in any figures. The claimed subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 10-17 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 10 and 19 recite “ the laser chip comprises two light emitting chips ”. Applicant’s specification as originally filed discloses “a dual laser chip”. Accordingly, it is unclear if applicant is attempting to claim that the laser chip is two light emitting chips or if the laser chip contains two lasers. For the purpose of this Office Action, the Office will interpret the language as “the laser chip comprises a dual laser chip”. Claim 19 recites “the second positive electrode”. Neither claim 18 nor claim 19 define “a second positive electrode”. Accordingly, this language lacks antecedent basis and it is unclear what electrode applicant is referring too. For the purpose of this Office Action, the first instance of “the second positive electrode” in claim 19 will be interpreted as “a second positive electrode”. Claims 11-17 are indefinite at least based on their dependence from claim 10. Claim 20 is indefinite at least based on its dependence from claim 19. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 1-3, 6 , and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuhama et al. (US20200287349A1), hereafter Matsuhama, in view of Sato et al. (US20 070030872 4A1), hereafter Sato . Regarding claim s 1 and 18 , Matsuhama discloses a n optical module (Figs. 6-7) , comprising: a light emitting component for generating and outputting signal light (Figs. 6 and 7 element 2) , including a laser (Fig. 6 and 7 element 2; [0032]) ; wherein the laser comprises: a laser chip for generating signal light (Fig. 6 and 7 element 2; [0032]) ; a substrate (Fig. 7 element 5(7)) which is provided with a chip mounting groove in its top side (Fig. 7 element M1) , a circuit is laid on a top surface of the substrate (Fig. 6 and 7 elements 58 and 57) , the laser chip is arranged in the chip mounting groove (Figs. 6 and 7 element 2 is in element M1) , with the laser chip being connected to the circuit via bonding wires (Figs. 6 and 7 element L4) ; wherein a bottom of the chip mounting groove comprises a chip carrying surface (Fig. 7 element 2 is on the bottom of M1). Matsuhama does not explicitly disclose a first deepening groove is provided at one side of the chip carrying surface, with a height difference between a bottom surface of the first deepening groove and the top surface of the substrate being greater than a height difference between the chip carrying surface and the top surface of the substrate; and/or, a second deepening groove is provided at the other side of the chip carrying surface, with the height difference between a bottom surface of the second deepening groove and the top surface of the substrate being greater than the height difference between the chip carrying surface and the top surface of the substrate; and the laser chip is arranged on the chip carrying surface, and the first deepening groove and/or the second deepening groove are configured to keep out of the way of corners of the laser chip. However, Sato discloses a first deepening groove is provided at one side of the chip carrying surface (Fig. 9 element s 41B are formed on both side s of the chip carrying surface 41A ), with a height difference between a bottom surface of the first deepening groove and the top surface of the substrate being greater than a height difference between the chip carrying surface and the top surface of the substrate (See annotated Fig. 9 below); and/or, a second deepening groove is provided at the other side of the chip carrying surface (Fig. 9 elements 41B are formed on both sides of the chip carrying surface 41A) , with the height difference between a bottom surface of the second deepening groove and the top surface of the substrate being greater than the height difference between the chip carrying surface and the top surface of the substrate (See annotated Fig. 9 below) ; and the laser chip is arranged on the chip carrying surface (Fig. 9 element 10 is on element 41A) , and the first deepening groove and/or the second deepening groove are configured to keep out of the way of corners of the laser chip (Fig. 9 shows the corners of element 10 are not affected by elements 41B). An advantage is to create space for adhesive/solder to be pushed into during mounting so that it does not contact other electrodes ([0082]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Matsuhama with a first deepening groove is provided at one side of the chip carrying surface, with a height difference between a bottom surface of the first deepening groove and the top surface of the substrate being greater than a height difference between the chip carrying surface and the top surface of the substrate; and/or, a second deepening groove is provided at the other side of the chip carrying surface, with the height difference between a bottom surface of the second deepening groove and the top surface of the substrate being greater than the height difference between the chip carrying surface and the top surface of the substrate; and the laser chip is arranged on the chip carrying surface, and the first deepening groove and/or the second deepening groove are configured to keep out of the way of corners of the laser chip as disclosed by Sato in order to create space for adhesive/solder to be pushed into during mounting so that it does not contact other electrodes. Regarding claim 2 , Matsuhama further discloses the chip mounting groove extends through the substrate (Fig. 7 element M1; [0048] describing the substrate as a “multilayer…substrate”) . Regarding claim 3 , Matsuhama further discloses the substrate comprises a top board and a bottom board ([0048]) , and the chip mounting groove is provided in the top board (Fig. 7 element M1) . Regarding claim 6 , Matsuhama further discloses a difference of the height difference between the chip carrying surface and the top surface of the substrate and the thickness of the laser chip is within ±10 μm (Fig. 7 element 2 is shown to have a top surface at the surface of the substrate 5(7) suggesting a difference of height of 0). Regarding claim 7 , Sato further discloses the chip carrying surface is located at the center of the chip mounting groove (Fig. 9 shows element 41A in the center). Claim s 4 , 5, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuhama in view of Sato , as applied to claim 1, in further view of Han et al. (US20120128290A1), hereafter Han . Regarding claim 4 , Matsuhama further discloses a first circuit is laid on an upper surface of the top board (Figs. 6 and 7 element 57) , a first extension circuit is laid on a lower surface of the top board (Fig. 6 element 5c) , a via hole are provided in the top board, such that the first circuit is connected to the first extension circuit through the via hole (Fig. 7 element 5c is connected to element 57 by a vertical via) . Matsuhama in view of Sato doe not explicitly disclose a plurality of via holes. However, Han discloses a first circuit is laid on an upper surface of the top board (Fig. 2 element 136g), a first extension circuit is laid on a lower surface of the top board (Fig. 3 element 132), via holes (Fig. 2 element 138) are provided in the top board, such that the first circuit is connected to the first extension circuit through the via hole (Fig. 3 element 138). An advantage is to suppress a resonance phenomenon between parts of the circuit ([0050]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Matsuhama in view of Sato with a plurality of via holes connecting the first circuit and the first extension circuit as disclosed by Han in order to suppress a resonance phenomenon between parts of the circuit. Regarding claim 5 , Matsuhama further discloses at least part of the first circuit is arranged on the chip carrying surface (Fig. 7 element 5c extends to where the chip is mounted) , and projections of at least part of the via holes onto the top surface of the substrate are located on the chip carrying surface (Fig. 7 element 5c is exposed at the chip carrying surface at a via hole) . Regarding claim 9 , Matsuhama in view of Sato do not explicitly disclose several electrodes are disposed on the upper surface of the laser chip, and several pads are disposed on the top surface of the substrate, with the electrodes being correspondingly connected to the pads via bonding wires. However, Han discloses several electrodes are disposed on the upper surface of the laser chip (Fig. 3 element 152 has elements 153 on its upper surface) , and several pads are disposed on the top surface of the substrate (Fig. 3 element 137r and 137o) , with the electrodes being correspondingly connected to the pads via bonding wires (Fig. 3 element 139). An advantage is to allow for an integrated modulator and laser ([0041]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Matsuhama in view of Sato with several electrodes are disposed on the upper surface of the laser chip, and several pads are disposed on the top surface of the substrate, with the electrodes being correspondingly connected to the pads via bonding wires as disclosed by Han in order to allow for an integrated modulator and laser. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuhama in view of Sato. Regarding claim 8 , Matsuhama further discloses a wire layer is provided on the chip carrying surface (Fig. 7 element 5c is exposed where element 2 is mounted), with the wire layer being electrically connected to the bottom surface of the laser ([0048]). While likely implied, Matsuhama in view of Sato do not explicitly disclose the wire layer is a metal layer. However, the Office takes Official Notice that wire layers made of metal in multilayer ceramic substrates are well known in the art. An advantage is cost savings using well known damascene processes to form copper interconnects in multilayer substrates. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Matsuhama in view of Sato with the wire layer is a metal layer as is known in the art in order to realize costs savings by using well known damascene processes to form copper interconnects in multilayer substrates. Allowable Subject Matter Claims 10-17, 19, and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claims 10 and 19 require “the circuit on the top surface of the substrate comprises a first high-speed signal line, a second high-speed signal line and a first ground for backflow, the laser chip comprises two light emitting chips, the top surface of which is provided with a first positive electrode and a second positive electrode, and the bottom surface of which is provided with a negative electrode; wherein the first positive electrode is electrically connected to the first high-speed signal line, the second positive electrode is electrically connected to the second high-speed signal line, the negative electrode is electrically connected to the first ground for backflow, and the first high-speed signal line and the second high-speed signal line have different lengths, so that the high-frequency signals transmitted to the first positive electrode and the second positive electrode through the first high-speed signal line and the second high-speed signal line have a preset delay difference” in addition to the limitations found in claims 1 and 18. While all the limitations are individually known in the art (see, e.g., cite no. 7 in the IDS filed 06/30/2023 discloses a dual laser source with a time delay; US20190237934A1 Fig. 4 disclosing multiple high speed signal lines having different lengths ), the Office has no motivation to combine the various features absent improper hindsight. Claims 11-17 and 20 contain allowable subject matter at least based on their dependence from claims 10 and 19. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attached Notice of References Cited. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JOSHUA KING whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1441 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday to Friday 10am-5pm MT . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Min Sun Harvey can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1835 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Joshua King/ Primary Examiner, Art Unit 2828 03/28/2026