DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant’s amendments, filed on 03/11/2026 regarding rejection of claims 1-21 has been considered and entered. Claims 12 and 21 are amended.
Response to Arguments
3. Applicant states in scanned page 2, “Applicant respectfully submits that Chen's detection of when a synchronized block passes through a SerDes interface is not the same as, and does not teach or suggest, "observing an indicated bit location" as recited in claim 1.”
The Examiner respectfully disagrees.
The said limitation “generating a timestamp at least partially responsive to observing the indicated bit location;”
Prior art Chen discloses in para’s [0019] Herein, the first position is the position of a bit corresponding to the first bit of the synchronized block in the SERDES parallel interface. For example, the first bit of the synchronized block is at the eighth bit in the SERDES parallel interface.and in para [0020] Fig. 1, At Step 103, a time point when the synchronized block passes through the SERDES parallel interface is determined as a first time point.
and in para [0021] Herein, the first time point may be understood as the time point when the first bit of the synchronized block passes through the SERDES parallel interface. That is, when the first bit of the synchronized block passes through the SERDES parallel interface, a time stamp is set and used as the first time point.
Also in para [0028]Fig. 1, 105 may be understood as that a data model is built according to the first time point, the first position, the distance and other parameters obtained in the SERDES parallel interface and the interface between the PHY layer and the MAC layer, and the time point when the first bit of the PTP packet passes through the SERDES serial interface is calculated through the built data model.
In this way, the time stamp of the PTP packet at the SERDES serial interface can be obtained more accurately.
Therefore Chen discloses a first bit of the synchronized block is at the eighth bit in the SERDES parallel interface i.e., location of first bit /a first time point. For the first bit/first time point a time stamp is set and obtained more accurately.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (EP 3883151 A1) hereinafter Chen and further in view of Yang et al. (US 20180191802 A1)hereinafter Yang
As to claim 1 Chen teaches a method, comprising: observing an indicated bit location at a parallel interface of a SerDes coupling a PHY with a physical transmission medium; ([0020][0021][0075] Fig. 4, when the first bit of the synchronized block passes through the SERDES parallel interface, a time stamp is set and used as the first time point; composition structure diagram of an apparatus includes a SERDES module 401, a PHY module 402, a MAC module, etc. in the composition structure diagram, modules are connected physically/Fig. 4,)
generating a timestamp at least partially responsive to observing the indicated bit location; ([0019] the first position is the position of a bit corresponding to the first bit of the synchronized block in the SERDES parallel interface; the first bit of the synchronized block is at the eighth bit in the SERDES parallel interface; at Step 103, a time point when the synchronized block passes through the SERDES parallel interface is determined as a first time point)
Chen does not teach and providing the timestamp to a user.
Yang teaches providing the timestamp to a user. ([0041] Fig. 2, high accuracy timestamp assist (HATA) device 271, generated timestamp, corresponding to the captured arrival time, is then transmitted to the time stamp unit TSU 165/slave side, to further clock synchronization between a master side and a slave side of the communication device.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine teachings of Yang with the teachings of Chen because Yang teaches that providing bit arrival timestamp to user would enable an accurate and precise system-wide measurement of time thereby providing accurate timing and synchronization (Yang [0005])
As to claim 2. The combination of Chen and Yang specifically Chen teaches , comprising: detecting a specific bit representative of a Tx path data delay; ([0061] Herein, the first time point is expressed as Tam, and the corresponding delay of the synchronized block from the SERDES serial interface to the SERDES parallel interface/transmit path, is expressed as Tsds,)
and generating an indication of location of the detected specific bit. ([0005] the position of the bit of the synchronized block in the SERDES parallel interface is determined as a first position; a time point when the synchronized block passes through the SERDES parallel interface is determined as a first time point)
As to claim 4. The combination of Chen and Yang specifically Chen teaches wherein the generating the indication of location of the detected specific bit comprises: ([0019] the first position is the position of a bit corresponding to the first bit of the synchronized block in the SERDES parallel interface; the first bit of the synchronized block is at the eighth bit in the SERDES parallel interface, i.e., eighth bit is an indication; at Step 103, a time point when the synchronized block passes through the SERDES parallel interface is determined as a first time point)--
------Chen does not teach generating, with outgoing data, the indication of the location of the detected specific bit.
Yang teaches generating, with outgoing data, the indication of the location of the detected specific bit. ([0046] Fig. 5, Since the start bit of the SFD pattern for a PTP message may appear an any bit position of the SerDes interface 549, Final Compensation and Timestamp report, which is transmitted from the HATA device 271 to the Timestamp Unit 560)--
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine teachings of Yang with the teachings of Chen because Yang teaches that providing bit arrival timestamp to user would enable an accurate and precise system-wide measurement of time thereby providing accurate timing and synchronization (Yang [0005])
As to claim 11. The combination of Chen and Yang specifically Yang teaches, wherein the user is a TimeSync client. ([0033] a Sync message and an optional Follow_Up message that transmit master time from the master clock to a slave clock; a Delay_req message transmitted from the slave clock to the master clock following receipt of the Sync message by the slave clock)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine teachings of Yang with the teachings of Chen because Yang teaches that providing bit arrival timestamp to user would enable an accurate and precise system-wide measurement of time thereby providing accurate timing and synchronization (Yang [0005])
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Yang and further in view of Haulin et al. (US 20130343409 A1) hereinafter Haulin
As to claim 3. The combination of Chen and Yang specifically Chen teaches wherein the detecting the specific bit representative of the Tx path data delay comprises: ([0061] Herein, the first time point is expressed as Tam, and the corresponding delay of the synchronized block from the SERDES serial interface to the SERDES parallel interface/transmit path,is expressed as Tsds,)
The combination of Chen and Yang does not teach detecting, in outgoing data, the specific bit representative of the Tx path data delay.
Haulin teaches detecting, in outgoing data, the specific bit representative of the Tx path data delay. ([0048] the bit b0 in the pattern associated with time stamping will always be found in the same location of a specific parallel word in the receive data 262. Then the transport delay for the bit pattern block through the Serdes is constant.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine teachings of Haulin with the teachings of Chen and Yang because Haulin teaches that delay bit the word and setting the local real time clock later or earlier by an amount reflecting the time required for fixed delay processing would allow to compensate fixed delay. (Haulin [0052])
Allowable Subject Matter
5. Claims 5-10 and 12-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Regarding independent claims 12 and 21,
Prior art Fries; Mark David et al. [US 20130341518 A1]discloses in para [0038] Fig. 3, Fig. 4, the parallel clock counter 132 counts five stop pulse words 232, wherein the fifth stop pulse word 232 includes the stop pulse LSB bit as identified by the count reset signal 252 generated by the leading edge detector 120. Accordingly, in the illustrated embodiment, the parallel clock counter 132 is configured to output a stop pulse most significant bit (MSB) 242 of "5" indicating that the fifth word, e.g. the fifth stop pulse word 232 was identified as having the stop pulse LSB. It should therefore be realized that the stop pulse MSB value 242 of "5" and the stop pulse LSB value 240 of "3" are combined to form a timestamp of "53" of the stop signal 230. In various embodiments, the start pulse MSB 242 is also input to the timestamp calculator 140 and the stop signal uniformity statistics device 152 and processed as described herein.
And also in para [0039] Fig. 3, Fig. 4, In operation, the timestamp calculator 140 is configured to generate a timestamp value 250 that is applied to the signals 230 received at the SERDES receiver 112. In the exemplary embodiment for example, assume that the start signal LSB value 212 is 3, the start signal MSB value 214 is 5, the stop signal LSB value 240 is 7, and the stop signal MSB value 242 is 2. Accordingly, the timestamp value 250 would be 26, e.g. 53-27.
And also prior art Saxtorph; Jakob [US 8949448 B1]discloses in para [0017] Fig. 2, As such, there will be ten different possible alignments of the first bit of the 66-bit input data within the 20-bit output data delivered to the SERDES, which equates to ten different latencies generated by the transmit gearbox 240 from the time the 20-bit output data is delivered to the SERDES interface until the first bit of the 66-bit serial code word is transmitted on the serial link. The difference in latency for each of the various 66-bit input data blocks affects the precision of the timestamp. Knowing the alignment of the 20-bit output data relative to the 66-bit input data will allow a timestamp adjustment value to be determined for each of the 66-bit input data blocks. This timestamp adjustment value can then be used to adjust the timestamp of the 66-bit input data block and the transmission timestamp 225 that will be sent to the system processor.
However, combination or prior arts records Fries and Saxtorph does not teach
For claim 5
combining the SerDes specific bit timestamp with an adjustment value to obtain a packet timestamp; and
providing the packet timestamp as the timestamp provided to the user.
And for claims 12 and claim 21
generate packet timestamps at least partially based thereon by combining a SerDes specific bit timestamp of the timestamps with an adjustment value.
Therefore, claim 5 is allowed for the above reasons. Dependent claims of claim 5, claim 6 to claim 10 are also allowed.
Independent claims 12 and claim 21 are also allowed for these reasons. The respective dependent claims of independent claim 12 are also allowed.
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lamb; Joseph M. [US 20160006677 A1] INVERSE PCP FLOW REMAPPING FOR PFC PAUSE FRAME GENERATION
HE; Li et al. [US 20200412469 A1] METHOD, DEVICE AND APPARATUS FOR DETERMINING TIME INFORMATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ATIQUE AHMED whose telephone number is (571)272-6244. The examiner can normally be reached 9:30 - 7:30 PM M-F Eastern.
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/ATIQUE AHMED/Primary Examiner, Art Unit 2413