DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-11 and 16-20 are pending in this application.
Response to Arguments
The prior objections to the drawings are withdrawn. However, the replacement drawings introduce new objections.
Applicant’s arguments regarding the rejections of claims 1-20 under 35 U.S.C. 112b have been fully considered and some are persuasive. Some of the rejections have been withdrawn. However, new 35 U.S.C. 112b rejections are applied to claims 1-11 and 17-20 based on the amendments. Regarding the rejection of claim 8, Applicant argues that since claim 5 recites a first mapping relationship, the fact that claim 8 recites a second mapping relationship is not indefinite. However, claim 8 is not dependent on claim 5, so the argument is unpersuasive. Regarding the rejection of claim 9, Application argues that claim 8 recites a second mapping relationship and claim 8 recites a third format, so claim 9’s recitation of a third mapping relationship and a fourth format are not indefinite. However, claim 9 is not dependent upon claim 8, so this argument is unpersuasive.
Applicant’s arguments regarding the rejections of claims 1-20 under 35 U.S.C. 101 have been fully considered and some are persuasive. The 35 U.S.C. 101 rejections of claims 16, 17, and 19 are maintained. Claim 16 recites a mental process since converting first data to second data in a second format is a mental process. For example, converting from base 16 to base 2 instructions can be performed in the mind. Claim 16 is different in scope from claim 1, so while claim 1 provides significantly more, claim 16 does not.
Applicant's arguments regarding the 35 U.S.C. 103 rejections of claims 1-20 have been fully considered but are moot in light of the references being applied in the current rejection.
Drawings
Reference number 1309 in Fig. 13 has a lead line and is also underlined. An underlined reference number indicates a surface area, but reference number 1309 does not refer to the surface area that that 1309 is on. Therefore, the underline should be removed and the lead line maintained. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1 and 20 (line numbers refer to claim 1):
Lines 19-24 recite “the at least one accelerator card processor configured, upon execution of the accelerator card instructions, to perform the following steps…execute the AI task suing the second data” but it is unclear how the accelerator card can execute the AI task if it hasn’t received it.
As per claim 8:
Lines 1 and 2 recite “second mapping relationship” but it is unclear how there can be a second mapping relationship and when a first mapping relationship is not recited.
As per claim 9:
Lines 1 and 2 recite “third mapping relationship” but it is unclear how there can be a third mapping relationship and when first and second mapping relationships are not recited.
Line 2 recites “a fourth format” but it is unclear how there can be a fourth format if there isn’t a third format.
As per claims 17-19 (line numbers refer to claim 17):
Line 1 recites “the method” but it is unclear if this refers to “a data processing method”.
Claims 2-11 are dependent claims of claim 1 and fail to resolve the deficiencies of claim 1, so they are rejected for the same reasons.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 16, 17, and 19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
As per claim 16, in step 1 of the 101 analysis, the examiner has determined that the claim is directed to a method. Therefore, the claim is directed to one of the four statutory categories of invention.
In step 2A prong 1 of the 101 analysis, the examiner has determined that the claim recites
a judicial exception. Specifically, the limitations of “the convert instruction…to convert the first data into second data in a second format” is a mental process. Converting from first data to second data is a mental process since humans can mentally perform calculations to change the format of data.
In step 2A prong 2 of the 101 analysis, the examiner has determined that the additional
elements, alone or in combination do not integrate the judicial exceptions into a practical
application for the following rationale:
The limitations "obtaining an AI task and first data corresponding to the AI task from a user, the first data being in a first format; sending the first data to an accelerator card; and sending a convert instruction to the accelerator card in the AI system based on the AI task" represent insignificant, extra-solution activities. The term "extra-solution activity" can be understood as "activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim" (MPEP 2106.05(g)). The examiner has determined that the limitations "obtaining an AI task and first data corresponding to the AI task from a user, the first data being in a first format; sending the first data to an accelerator card; and sending a convert instruction to the accelerator card in the AI system based on the AI task" are directed to mere data gathering activities which is a category of insignificant extra-solution activities (MPEP 2106.05(g)).
The limitations "a data processing method for a host in an artificial intelligence (AI) system, the data processing method comprising" and "instructing the accelerator card " apply judicial exceptions on a generic computer. "Alappat 's rationale that an otherwise ineligible algorithm or software could be made patent-eligible by merely adding a generic computer to the claim was superseded by the Supreme Court's Bilski and Alice Corp. decisions" so therefore applying judicial exceptions on an AI system and accelerator card which are generic computers does not integrate the judicial exceptions into a practical application (MPEP 2106.05(b)).
In step 2B of the 101 analysis, the examiner has determined that the additional elements, alone or in combination do not recite significantly more than the abstract ideas identified above for the following rationale:
The limitations "obtaining an AI task and first data corresponding to the AI task from a user, the first data being in a first format; sending the first data to an accelerator card; and sending a convert instruction to the accelerator card in the AI system based on the AI task" represent insignificant, extra-solution activities. The limitations "obtaining an AI task and first data corresponding to the AI task from a user, the first data being in a first format; sending the first data to an accelerator card; and sending a convert instruction to the accelerator card in the AI system based on the AI task" are well-understood, routine, or conventional because they are directed to "receiving or transmitting data" (MPEP 2106.05(d)). These are additional elements that the courts have recognized as well understood, routine, or conventional (MPEP 2106.05(d)). The citation of court cases in the MPEP meets the Berkheimer evidentiary burden since citation of a court case in the MPEP is one of the 4 types of evidentiary support that can be used to prove that the additional elements are well-understood, routine, or conventional (see 125 USPQ2d 1649 Berkheimer v. HP, Inc.). Thus, the limitations do not amount to significantly more than the abstract idea.
The limitations "a data processing method for a host in an artificial intelligence (AI) system, the data processing method comprising" and "instructing the accelerator card" apply judicial exceptions on a generic computer and therefore do not provide significantly more.
As per claim 17, it recites an insignificant extra solution activity that is well understood, routine, or conventional because it is directed to "receiving or transmitting data" (MPEP 2106.05(d)). Therefore, the additional elements neither integrate the judicial exceptions into a practice application nor recite significant more.
As per claim 19, it recites a mental process.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-11 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 20230133337 A1 hereinafter Zhou) in view of Kim et al. (US 20200125820 A1 hereinafter Kim).
As per claim 1, Zhou teaches an artificial intelligence (AI) system, the AI system comprising: a host in communication with an accelerator card, the host comprising: a host memory storing host instructions; and at least one host processor in communication with the host memory, the at least one host processor configured, upon execution of the host instructions, to perform the following steps ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU); [0121] In an embodiment of the present disclosure, the artificial intelligence processor chip may be implemented in a separate device from the computing device 800; [0107] the computing device 800 may include a processor 810 and a memory 820): obtain an AI task and first data corresponding to the AI task, the first data being in a first format ([0111] The memory 820 may store data sets involved in the neural network operation processed or to be processed by the processor 810, such as data of an untrained initial neural network; [0112] parameters of the initial neural network is are a high-precision data representation format in the sense of ensuring the processing accuracy of the neural network, such as a data representation format with a floating point precision of 32 bits); send the first data to the accelerator card; and send a convert instruction to the accelerator card based on the AI task, the convert instruction instructing the accelerator card to convert the first data into second data in a second format ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0079] quantization of data (e.g., activation values, weights, gradients, etc.) in a neural network operation process by an artificial intelligence processor; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits); and the accelerator card comprising: an accelerator card memory storing accelerator card instructions; and at least one accelerator card processor in communication with the accelerator card memory, the at least one accelerator card processor configured, upon execution of the accelerator card instructions, to perform the following steps ([0117] caches in the artificial intelligence processor chip, and avoid the memory access bottleneck. Meanwhile, when an SIMD instruction is executed on the artificial intelligence processor chip, more computing are implemented within one clock period so that the neural network operation can be performed more quickly; [0122] sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction; [0124] an on-chip memory of the artificial intelligence processor chip; [0126] a single-core artificial intelligence processor or a multi-core artificial intelligence processor.): convert the first data into the second data in the second format according to the convert instruction from the host ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits); and execute the AI task using the second data ([0079] The quantized fixed point type data may be used by the artificial intelligence processor for training, tuning, or inference of the neural network.).
Zhou fails to teach the at least one host processor configured, upon execution of the host instructions, to perform the following steps: obtain an AI task and first data corresponding to the AI task from a user.
However, Kim teaches the at least one host processor configured, upon execution of the host instructions, to perform the following steps: obtain an AI task and first data corresponding to the AI task from a user (Fig. 8; [0060] A data recognition system described herein is a system configured to recognize data input from a user; [0120] Referring to FIG. 8, a data recognition apparatus 800 includes a processor 810, a memory 820, and a data acquirer 830; [0121] The processor 810 may extract a feature map from input data; [0123] The data acquirer 830 may obtain the input data. For example, the data acquirer 830 may include a camera sensor, and the camera sensor may capture an image including at least a portion of a body of a user by a single frame or a plurality of frames. The portion of the body may include, for example, a face, an eye, an iris, and a fingerprint, and the like of the user. However, the portion of the body is not limited to the foregoing examples, and may vary based on a design. For another example, the data acquirer 830 may include a voice sensor, and the voice sensor may capture a speech signal of a user; [0056] The neural network may be configured to perform, as non-limiting examples, speech recognition, translation, agent conversation or interaction, and/or image recognition by respectively mutually mapping input data and output data in nonlinear relationships based on learning, e.g., based on deep learning; [0068] The speech recognition server 130 may then receive, from the first terminal 101, the speech signal indicating the instruction of the first user 111).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Zhou with the teachings of Kim so that a user has input on information being processed (see Kim [0149] the input device 1240 may obtain speech data as input data from a user; [0062] The speech recognition apparatus described herein may be configured to collect sound or voice and obtain an audio signal, which is a digital electrical signal, from the collected sound or voice. For example, the speech recognition apparatus may collect speech sound of a human being as nearby sound, and distinguish a voice or speech of a user of the speech recognition apparatus from the nearby sound. In addition, the speech recognition apparatus may recognize a registered user from a speech signal).
As per claim 2, Zhou and Kim teach the AI system according to claim 1. Zhou teaches wherein the host is configured to send the first instruction to the accelerator card based on an operator type comprised in the AI task ([0117] The artificial intelligence processor chip is dedicated hardware used to drive a neural network. Since the artificial intelligence processor chip is implemented with a relatively low power or performance, the technical solution of the present disclosure can implement the neural network operation by fixed point numbers with lower precision, which, compared with high-precision data, requires a narrower memory bandwidth when reading the fixed point numbers with lower precision, and may make better use of caches in the artificial intelligence processor chip, and avoid the memory access bottleneck; [0112] Specifically, most of the computations processed by the neural network are known as various types of convolution computations; [0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network.).
As per claim 3, Zhou and Kim teach the AI system according to claim 1. Zhou teaches wherein the AI task comprises a second instruction, and the second instruction instructs to execute the AI task using the second data in the second format; and the host is configured to send the first instruction to the accelerator card according to the second instruction ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0079] The quantized fixed point type data may be used by the artificial intelligence processor for training, tuning, or inference of the neural network).
As per claim 4, Zhou and Kim teach the AI system according to claim 2. Zhou teaches wherein the host is configured to establish a correspondence between the operator type comprised in the AI task and the second format ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits; [0112] Specifically, most of the computations processed by the neural network are known as various types of convolution computations).
As per claim 5, Zhou and Kim teach the AI system according to claim 1. Zhou teaches wherein the host stores a first mapping relationship for converting the first data in the first format into the second data in the second format, and the first instruction comprises the first mapping relationship; and the accelerator card is configured to convert the first data into the second data based on the first mapping relationship ([0066] When the input data is quantized by the quantization operation shown in FIG. 4, data beyond a threshold ±T will be directly mapped to the fixed point number ±(2.sup.n-1−1) to which the threshold ±T is mapped; [0113] the computing device 800 transmits the corresponding quantization parameter (e.g., a truncated threshold) to the device in which the neural network is deployed so that a fixed point number computation is performed when the artificial intelligence processor chip performs an computation operation such as training, tuning, and the like; [0114] The processor 810 retrieves data from the memory 820 during the neural network operation. The data includes at least one of a neuron, a weight, a bias or a gradient, the corresponding truncated threshold is determined using the technical solution shown in FIGS. 6-7, and then used for quantization of the target data during the neural network operation; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits).
As per claim 6, Zhou and Kim teach the AI system according to claim 1. Kim teaches wherein the AI system is located in a public cloud ([0154] the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers; [0056] Such learning or deep learning is indicative of processor implemented machine learning schemes for solving issues).
As per claim 7, Zhou and Kim teach the AI system according to claim 1. Zhou teaches wherein the AI system processes at least one AI framework, and each of the at least one AI framework supports data in the first format ([0112] The processor 810 may generate a trained neural network by iteratively training (learning) a given initial neural network. In this state, parameters of the initial neural network is are a high-precision data representation format in the sense of ensuring the processing accuracy of the neural network, such as a data representation format with a floating point precision of 32 bits.).
As per claim 8, Zhou and Kim teach the AI system according to claim 1. Zhou teaches wherein the host stores a second mapping relationship, the second mapping relationship being used for converting data in the first format into data in a third format ([0066] When the input data is quantized by the quantization operation shown in FIG. 4, data beyond a threshold ±T will be directly mapped to the fixed point number ±(2.sup.n-1−1) to which the threshold ±T is mapped; [0113] the computing device 800 transmits the corresponding quantization parameter (e.g., a truncated threshold) to the device in which the neural network is deployed so that a fixed point number computation is performed when the artificial intelligence processor chip performs an computation operation such as training, tuning, and the like; [0114] The processor 810 retrieves data from the memory 820 during the neural network operation. The data includes at least one of a neuron, a weight, a bias or a gradient, the corresponding truncated threshold is determined using the technical solution shown in FIGS. 6-7, and then used for quantization of the target data during the neural network operation; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits; [0058] in FIG. 4, 32-bit floating point type data is quantized into n-bit fixed point type data, where n is a bit width of the fixed point number).
As per claim 9, Zhou and Kim teach the AI system according to claim 1. Zhou teaches wherein the host stores a third mapping relationship, the third mapping relationship being used for converting data in a fourth format into data in the second format ([0066] When the input data is quantized by the quantization operation shown in FIG. 4, data beyond a threshold ±T will be directly mapped to the fixed point number ±(2.sup.n-1−1) to which the threshold ±T is mapped; [0113] the computing device 800 transmits the corresponding quantization parameter (e.g., a truncated threshold) to the device in which the neural network is deployed so that a fixed point number computation is performed when the artificial intelligence processor chip performs an computation operation such as training, tuning, and the like; [0114] The processor 810 retrieves data from the memory 820 during the neural network operation. The data includes at least one of a neuron, a weight, a bias or a gradient, the corresponding truncated threshold is determined using the technical solution shown in FIGS. 6-7, and then used for quantization of the target data during the neural network operation; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits; [0058] in FIG. 4, 32-bit floating point type data is quantized into n-bit fixed point type data, where n is a bit width of the fixed point number; [0056] Then, a fixed point type weight gradient 380 computed by the fixed point computing apparatus 330 is dequantized to a floating point type weight gradient 390).
As per claim 10, Zhou and Kim teach the AI system according to claim 1. Zhou teaches wherein the host is configured to: obtain format information of the first data; and determine, based on the format information, that the first data is in the first format ([0111] The memory 820 may store data sets involved in the neural network operation processed or to be processed by the processor 810, such as data of an untrained initial neural network; [0112] parameters of the initial neural network is are a high-precision data representation format in the sense of ensuring the processing accuracy of the neural network, such as a data representation format with a floating point precision of 32 bits).
As per claim 11, Zhou and Kim teach the AI system according to claim 1. Zhou teaches data in the first format ([0112] parameters of the initial neural network is are a high-precision data representation format in the sense of ensuring the processing accuracy of the neural network, such as a data representation format with a floating point precision of 32 bits).
Additionally, Kim teaches wherein the host is further configured to output prompt information, wherein the prompt information indicates the user to enter data ([0149] The input device 1240 may receive an input from a user through a tactile, video, audio, or tough input. The input device 1240 may include, for example, a keyboard, a mouse, a touchscreen, a microphone, and other devices that may detect an input from a user and transmit the detected input to the computing apparatus 1200. For example, the input device 1240 may obtain speech data as input data from a user.).
As per claim 16, Zhou teaches a data processing method for a host in an artificial intelligence (AI) system, the data processing method comprising ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0121] In an embodiment of the present disclosure, the artificial intelligence processor chip may be implemented in a separate device from the computing device 800; [0107] the computing device 800 may include a processor 810 and a memory 820): obtaining an AI task and first data corresponding to the AI task, the first data being in a first format ([0111] The memory 820 may store data sets involved in the neural network operation processed or to be processed by the processor 810, such as data of an untrained initial neural network; [0112] parameters of the initial neural network is are a high-precision data representation format in the sense of ensuring the processing accuracy of the neural network, such as a data representation format with a floating point precision of 32 bits); sending the first data to an accelerator card; and sending a convert instruction to the accelerator card in the AI system based on the AI task, the convert instruction instructing the accelerator card to convert the first data into second data in a second format ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits; [0079] quantization of data (e.g., activation values, weights, gradients, etc.) in a neural network operation process by an artificial intelligence processor).
Zhou fails to teach a data processing method for a host in an artificial intelligence (AI) system, the data processing method comprising: obtaining an AI task and first data corresponding to the AI task from a user.
However, Kim teaches a data processing method for a host in an artificial intelligence (AI) system, the data processing method comprising: obtaining an AI task and first data corresponding to the AI task from a user (Fig. 8; [0060] A data recognition system described herein is a system configured to recognize data input from a user; [0120] Referring to FIG. 8, a data recognition apparatus 800 includes a processor 810, a memory 820, and a data acquirer 830; [0121] The processor 810 may extract a feature map from input data; [0123] The data acquirer 830 may obtain the input data. For example, the data acquirer 830 may include a camera sensor, and the camera sensor may capture an image including at least a portion of a body of a user by a single frame or a plurality of frames. The portion of the body may include, for example, a face, an eye, an iris, and a fingerprint, and the like of the user. However, the portion of the body is not limited to the foregoing examples, and may vary based on a design. For another example, the data acquirer 830 may include a voice sensor, and the voice sensor may capture a speech signal of a user; [0056] The neural network may be configured to perform, as non-limiting examples, speech recognition, translation, agent conversation or interaction, and/or image recognition by respectively mutually mapping input data and output data in nonlinear relationships based on learning, e.g., based on deep learning; [0068] The speech recognition server 130 may then receive, from the first terminal 101, the speech signal indicating the instruction of the first user 111).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Zhou with the teachings of Kim so that a user has input on information being processed (see Kim [0149] the input device 1240 may obtain speech data as input data from a user; [0062] The speech recognition apparatus described herein may be configured to collect sound or voice and obtain an audio signal, which is a digital electrical signal, from the collected sound or voice. For example, the speech recognition apparatus may collect speech sound of a human being as nearby sound, and distinguish a voice or speech of a user of the speech recognition apparatus from the nearby sound. In addition, the speech recognition apparatus may recognize a registered user from a speech signal).
As per claim 17, Zhou and Kim teach the method according to claim 16. Zhou teaches wherein the sending the first instruction to the accelerator card based on the AI task comprises sending the first instruction to the accelerator card based on an operator type comprised in the AI task ([0117] The artificial intelligence processor chip is dedicated hardware used to drive a neural network. Since the artificial intelligence processor chip is implemented with a relatively low power or performance, the technical solution of the present disclosure can implement the neural network operation by fixed point numbers with lower precision, which, compared with high-precision data, requires a narrower memory bandwidth when reading the fixed point numbers with lower precision, and may make better use of caches in the artificial intelligence processor chip, and avoid the memory access bottleneck; [0112] Specifically, most of the computations processed by the neural network are known as various types of convolution computations; [0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network.).
As per claim 18, Zhou and Kim teach the method according to claim 16. Zhou teaches wherein the AI task comprises a second instruction and the second instruction instructs to execute the AI task using the second data in the second format; and the sending the first instruction to the accelerator card based on the AI task comprises sending the first instruction to the accelerator card according to the second instruction ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0079] The quantized fixed point type data may be used by the artificial intelligence processor for training, tuning, or inference of the neural network; ; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits).
As per claim 19, Zhou and Kim teach the method according to claim 17. Zhou teaches wherein the method further comprises: establishing a correspondence between the operator type comprised in the AI task and the second format ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits; [0112] Specifically, most of the computations processed by the neural network are known as various types of convolution computations).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhou.
As per claim 20, Zhou teaches a data processing method for an accelerator card in an artificial intelligence (AI) system, the data processing method comprising ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU): receiving first data and a convert instruction sent by a host in the AI system, the first data being in a first format and corresponding to the AI task ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0112] parameters of the initial neural network is are a high-precision data representation format in the sense of ensuring the processing accuracy of the neural network, such as a data representation format with a floating point precision of 32 bits; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits); converting the first data into second data according to the convert instruction, the second data being in a second format ([0122] In an embodiment of the present disclosure, an operating system of a general purpose processor (such as a CPU) generates an instruction based on the embodiment of the present disclosure, and sends the generated instruction to an artificial intelligence processor chip (such as a GPU) which execute the instruction to perform the processes of calibrating quantization noise and quantizing of a neural network; [0031] Quantization: a process of converting a high-precision number expressed by 32 bits or 64 bits into a fixed point number which occupies less memory space, where the fixed point number is generally 16 bits or 8 bits); and executing an AI task using the second data ([0079] The quantized fixed point type data may be used by the artificial intelligence processor for training, tuning, or inference of the neural network.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSING CHUN LIN whose telephone number is (571)272-8522. The examiner can normally be reached Mon - Fri 9AM-5PM.
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/H.L./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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