Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because:
The opening sentence “The present disclosure generally….” is improper.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-18 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Hsieh in the US Patent Number US 6564986 B1.
Regarding claim 1, Hsieh teaches an electronic system (This invention relates to the field of integrated circuits (ICs), and more specifically to IC packages; Column 1 Line 8-9; an assembly for analyzing solder joint fractures in response to thermal cycling includes an IC package mounted (i.e., soldered) to a test PCB; Column 2 Line 66-67 & Column 3 Line 1; FIG. 4 is a perspective view showing an assembly 200 for testing BGA packages; Column 4 Line 61-62) comprising:
a semiconductor package [120A] (BGA Package 120A as the semiconductor package) (Assembly 200 includes BGA package 120A; Column 4 Line 63-64; BGA package 120A includes package substrate 121; Column 4 Line 66-67; A BGA package (Ball Grid Array) is a specific type of semiconductor package; https://www.bing.com/search?q=semiconductor%20package%20and%20BGA%20package%20same%20&qs=n&form=QBRE&sp=-1&ghc=1&lq=0&pq=semiconductor%20package%20and%20bga%20package%20same%20&sc=9-43&sk=&cvid=7F234D3BA5D24F7F94FA2EFF3EF519FF); and
a circuit board [210] (a test printed circuit board (PCB) 210; Column 4 Line 65),
wherein the semiconductor package [120A] and the circuit board [210] comprise contact structures [125, 126, 128, 205, 215 [1-4], 220] (contact pads 125, solder balls 126, and conductive vias 128, bond wires 205, contact pads 215 and conductive (e.g., metal) lines 220 as the contact structure) (FIG. 4, BGA package 120A includes package substrate 121, contact pads 125, solder balls 126, and conductive vias 128; Column 4 Line 66-67 & Column 5 Line 1; Assembly 200 includes BGA package 120A that includes bond wires 205; Column 4 Line 63-64; FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42) configurable to have an output terminal [225-2] of one contact structure [215-5] connected to an input terminal [225-1] of another contact structure [215-4] (Note also that test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2; Column 5 Line 66-67 & Column 6 Line 1-3) so as to render a continuous electrical pathway through the contact structures [125, 126, 128, 205, 215 [1-4], 220] (FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2. Contact pads 215 are arranged to match the footprint of IC package 120A such that, when BGA package 120A is mounted on test PCB 210, each solder ball 126 (e.g., solder ball 126-1) contacts an associated contact pad 215 (e.g., contact pad 215-1, as indicated by the dashed arrow in FIG. 4). In accordance with another aspect of the present invention, associated pairs of contact pads 215 are connected by conductive lines 220, 230-1 and 230-2 to form a second (lower) half of the daisy chain (the second daisy chain portion) that extends between first test pad 225-1 and second test pad 225-2; Column 5 Line 39-53; For example, when a voltage is applied to test pad 225-1 in Figure 5 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27),
wherein the contact structures [125, 126, 128, 205, 215 [1-4], 220] are configured in a daisy chain manner forming a series connection (Figure 5 shows the series connection) (Accordingly, a segment of the daisy chain is formed between contact pads 125-1 and contact pad 125-4 that passes along wire bond 205-1, conductive line 220-1, and wire bond 205-2. Note also that test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2; Column 5 Line 63-67 & Column 6 Line 1-3), and
wherein the continuous electrical pathway (test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2 makes continuous electrical pathway where current flows: Figure 5 dash line shows the electrical pathway) renders an output pattern in response to an electrical stimulus [voltage/current] introduced to the electronic system [200] (For example, when a voltage is applied to test pad 225-1 in Figure 5 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27; FIG. 5 is a perspective view showing assembly 200 after BGA package 120 is mounted on test PCB 210 (note that BGA substrate 121 and the substrate portion of test PCB 210 are removed for clarity). The dashed-line arrow generally indicates a current path defined by the daisy chain by which a current passes through assembly 200 between test pad 225-1 and test pad 225-2; Column 6 Line 6-12).
Regarding claim 2, Hsieh teaches an electronic system,
wherein the contact structures [125, 126, 128, 205, 215 [1-4], 220] are configured on the semiconductor package [120A] and on the circuit board [210] (FIG. 4, BGA package 120A includes package substrate 121, contact pads 125, solder balls 126, and conductive vias 128; Column 4 Line 66-67 & Column 5 Line 1; Assembly 200 includes BGA package 120A that includes bond wires 205; Column 4 Line 63-64; FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42; The IC package includes solder balls extending from a lower surface thereof that are arranged in a footprint (pattern) and are connected by conductive vias extending through the package body to contact pads formed on an upper surface thereof. Instead of being wire bonded to an IC chip, selected pairs of these contact pads are connected together to form a first daisy chain portion. The test PCB is provided with contact pads, which are arranged to match the IC package footprint. Similar to the IC package, associated pairs of the contact pads are connected by conductive lines to form a second daisy chain portion; Column 3 Line 1-12), and
the contact structures [125, 126, 128, 205, 215 [1-4], 220] are positioned between and in contact with both the semiconductor package [120A] and the circuit board [210] (FIG. 5 is a perspective view showing assembly 200 after BGA package 120 is mounted on test PCB 210 (note that BGA substrate 121 and the substrate portion of test PCB 210 are removed for clarity). The dashed-line arrow generally indicates a current path defined by the daisy chain by which a current passes through assembly 200 between test pad 225-1 and test pad 225-2. That is, by alternating the connections between contact pads 215 on test PCB 210 and the connections between contact pads 125 on BGA package 120A, the resulting daisy chain forms a conductive between (first) test pad 225-1 and (final) test pad 225-2 that passes through all sixty-four solder balls 126; Column 6 Line 6-17).
Regarding claim 3, Hsieh teaches an electronic system,
wherein the circuit board [210] comprises the contact structures [215 [1-4], 220] (FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42), and
some contact structures [215 [1-4], 220] are configured proximal to the semiconductor package [120A] (Figure 5 shows some contact structures [215 [1-4], 220] are configured proximal to the semiconductor package [120A]) and some contact structures [225-1, 225-2] are configured distal from the semiconductor package [120A] (figure 5 shows some contact structures [225-1, 225-2] are configured distal from the semiconductor package [120A]).
Regarding claim 4, Hsieh teaches an electronic system,
wherein the contact structures [215 [1-4], 220] are formed coplanar to the circuit board [210] (Referring to the lower portion of FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42; Figure 4 shows contact pads 215 are formed coplanar to the circuit board 210).
Regarding claim 6, Hsieh teaches an electronic system,
wherein the semiconductor package [120A] together with the circuit board [210] are configurable as one or more regions for identifying any warpage in the one or more regions,
wherein the semiconductor package together with the circuit board are
configurable as one region having the contact structures for rendering an overall output
pattern to identify any warpage, and if warpage is identified, the semiconductor package
together with the circuit board are configurable as two or more regions, each region
comprising at least one contact structure for rendering a regional output pattern so as to
identify a location of the warpage from the two or more regions (FIG. 6 is a flow diagram showing a method for testing IC package 120A for solder joint fractures in accordance with another aspect of the present invention. First, the daisy chain structure of assembly 200 (see FIGS. 4 and 5) is formed by connecting associated pairs of solder balls 126 of IC package 120A and associated pairs of contact pads 215 of test PCB 210 (step 610). This process is separated into three parts. Connection of associated pairs of solder balls 126 to form the first daisy chain portion (step 612) and production of test PCB 210 to form the second daisy chain portion (step 614) can be performed in any order. Once package 120A and test PCB 210 are completed, package 120A is mounted on test PCB 210 (step 616) using, for example, well-known reflow soldering techniques such that solder balls 126 are soldered to contact pads 215 to complete the daisy chain structure. Next, thermal cycle testing is initiated by setting a counter to zero (step 620), assembly 200 is heated and cooled according to predefined parameters (step 630), and the counter is incremented to register the number of completed thermal cycles (step 640). Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650). If no open circuit is detected, then thermal cycling is repeated and current measured until an open circuit occurs. When an initial open circuit is detected for a package, the location of the open circuit is noted, and an optional post-failure counter (PFCNT) is initiated. Thermal cycling is again performed (step 660) and the location of each additional open circuit (fracture) on the remaining other packages is identified using methods described below with reference to FIGS. 7 and 8 (step 670). The optional post-failure counter is then incremented, and steps 660 and 670 are repeated for a predetermined amount of time (e.g., 1,000 cycles). Upon completion, an optional post failure analysis is performed; Column 6 Line 28-63).
Regarding claim 7, Hsieh teaches an electronic system,
further comprising one or more test terminals [225-1, 225-2] (test pad 225-1 and 225-2 as the test terminals) for introducing the electrical stimulus (For example, when a voltage is applied to test pad 225-1 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27).
Regarding claim 8, Hsieh teaches an electronic system,
wherein the one or more test terminals [225-1, 225-2] are configured on the semiconductor package and/or on the circuit board [210] (Referring to the lower portion of FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42; Figure 4 shows test pads 225-1, 225-2 as the test terminals are on the circuit board 210).
Regarding claim 9, Hsieh teaches a method for identifying warpage in an electronic system (an assembly for analyzing solder joint fractures in response to thermal cycling includes an IC package mounted (i.e., soldered) to a test PCB; Column 2 Line 66-67 & Column 3 Line 1; This invention relates to the field of integrated circuits (ICs), and more specifically to IC packages; Column 1 Line 8-9; FIG. 6 is a flow diagram showing a method for testing IC package 120A for solder joint fractures; Column 6 Line 28-29; solder joint fractures in response to thermal cycling and warpage means the bent or twisted or distorted shape because of heat and it happens because of the heat. Hsieh is doing thermal cycling by introducing heat to see any open circuit in the solder joint and therefore solder joint fractures can be considered as the warpage of the electronic system) the method comprising:
identifying [610] contact structures [125, 126, 128, 205, 215 [1-4], 220] (contact pads 125, solder balls 126, and conductive vias 128, bond wires 205, contact pads 215 and conductive (e.g., metal) lines 220 as the contact structure) (FIG. 4, BGA package 120A includes package substrate 121, contact pads 125, solder balls 126, and conductive vias 128; Column 4 Line 66-67 & Column 5 Line 1; Assembly 200 includes BGA package 120A that includes bond wires 205; Column 4 Line 63-64; FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42) in the electronic system (FIG. 6 is a flow diagram showing a method for testing IC package 120A for solder joint fractures in accordance with another aspect of the present invention. First, the daisy chain structure of assembly 200 (see FIGS. 4 and 5) is formed by connecting associated pairs of solder balls 126 of IC package 120A and associated pairs of contact pads 215 of test PCB 210 (step 610); Column 6 Line 28-34);
introducing [640] an electrical stimulus (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to the electronic system [200] (Next, thermal cycle testing is initiated by setting a counter to zero (step 620), assembly 200 is heated and cooled according to predefined parameters (step 630), and the counter is incremented to register the number of completed thermal cycles (step 640); Column 6 Line 43-48-7; Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650); Column 6 Line 47-51; For example, when a voltage is applied to test pad 225-1 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27);
wherein the electronic system [200] (Figure 4) comprises:
a semiconductor package [120A] (BGA Package 120A as the semiconductor package) (Assembly 200 includes BGA package 120A; Column 4 Line 63-64; BGA package 120A includes package substrate 121; Column 4 Line 66-67; A BGA package (Ball Grid Array) is a specific type of semiconductor package; https://www.bing.com/search?q=semiconductor%20package%20and%20BGA%20package%20same%20&qs=n&form=QBRE&sp=-1&ghc=1&lq=0&pq=semiconductor%20package%20and%20bga%20package%20same%20&sc=9-43&sk=&cvid=7F234D3BA5D24F7F94FA2EFF3EF519FF); and
a circuit board [210] (a test printed circuit board (PCB) 210; Column 4 Line 65),
wherein the semiconductor package [120A] and the circuit board [210] comprising the contact structures [125, 126, 128, 205, 215 [1-4], 220] (contact pads 125, solder balls 126, and conductive vias 128, bond wires 205, contact pads 215 and conductive (e.g., metal) lines 220 as the contact structure) (FIG. 4, BGA package 120A includes package substrate 121, contact pads 125, solder balls 126, and conductive vias 128; Column 4 Line 66-67 & Column 5 Line 1; Assembly 200 includes BGA package 120A that includes bond wires 205; Column 4 Line 63-64; FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42) configurable to have an output terminal [225-2] of one contact structure [215-5] connected to an input terminal [225-1] of another contact structure [215-4] (Note also that test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2; Column 5 Line 66-67 & Column 6 Line 1-3) so as to render a continuous electrical pathway through the contact structures [125, 126, 128, 205, 215 [1-4], 220] (FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2. Contact pads 215 are arranged to match the footprint of IC package 120A such that, when BGA package 120A is mounted on test PCB 210, each solder ball 126 (e.g., solder ball 126-1) contacts an associated contact pad 215 (e.g., contact pad 215-1, as indicated by the dashed arrow in FIG. 4). In accordance with another aspect of the present invention, associated pairs of contact pads 215 are connected by conductive lines 220, 230-1 and 230-2 to form a second (lower) half of the daisy chain (the second daisy chain portion) that extends between first test pad 225-1 and second test pad 225-2; Column 5 Line 39-53; For example, when a voltage is applied to test pad 225-1 in Figure 5 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27), and
wherein the continuous electrical pathway (test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2 makes continuous electrical pathway where current flows: Figure 5 dash line shows the electrical pathway) renders an output pattern in response to an electrical stimulus [voltage/current] introduced to the electronic system [200] (For example, when a voltage is applied to test pad 225-1 in Figure 5 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27; FIG. 5 is a perspective view showing assembly 200 after BGA package 120 is mounted on test PCB 210 (note that BGA substrate 121 and the substrate portion of test PCB 210 are removed for clarity). The dashed-line arrow generally indicates a current path defined by the daisy chain by which a current passes through assembly 200 between test pad 225-1 and test pad 225-2; Column 6 Line 6-12);
identifying [650] a presence or absence of the output pattern (Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650); Column 6 Line 47-51); and
determining a presence or absence of the warpage in the electronic system based on
the presence or absence of the output pattern (Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650). If no open circuit is detected, then thermal cycling is repeated and current measured until an open circuit occurs. When an initial open circuit is detected for a package, the location of the open circuit is noted, and an optional post-failure counter (PFCNT) is initiated; Column 6 Line 47-55).
Regarding claim 10, Hsieh teaches a method,
wherein introducing the electrical stimulus to the electronic system [200] ((Next, thermal cycle testing is initiated by setting a counter to zero (step 620), assembly 200 is heated and cooled according to predefined parameters (step 630), and the counter is incremented to register the number of completed thermal cycles (step 640); Column 6 Line 43-48-7; Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650); Column 6 Line 47-51) comprises:
introducing the electrical stimulus [voltage/current] via one test terminal [225-1] [a first test pad 225-1 and a second test pad 225-2] (a first test pad 225-1 and a second test pad 225-2 as the test terminals) configured on the semiconductor package [120A] or on the circuit board [210] (Referring to the lower portion of FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42; Figure 4 shows test pads 225-1, 225-2 as the test terminals are on the circuit board 210; Note also that test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2.; Column 5 Line 66-67 & Column 6 Line 1-5; The dashed-line arrow generally indicates a current path defined by the daisy chain by which a current passes through assembly 200 between test pad 225-1 and test pad 225-2; Column 6 Line 9-12); and
receiving an output (resistance) from another test terminal [225-2] configured on the semiconductor package [120A] or on the circuit board [210] (Referring to the lower portion of FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42; For example, when a voltage is applied to test pad 225-1 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27; Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650); Column 6 Line 47-51),
wherein the output is to be rendered as the output pattern (resistance to measure open circuit) (For example, when a voltage is applied to test pad 225-1 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2.; Column 6 Line 17-27; Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650); Column 6 Line 47-51).
Regarding claim 11, Hsieh teaches a method,
wherein introducing the electrical stimulus to the electronic system [200] (Next, thermal cycle testing is initiated by setting a counter to zero (step 620), assembly 200 is heated and cooled according to predefined parameters (step 630), and the counter is incremented to register the number of completed thermal cycles (step 640); Column 6 Line 43-48-7; Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650); Column 6 Line 47-51) comprises:
providing an electrical input [voltage/current] via one test terminal [225-1] which is electrically coupled to the semiconductor package [120A] (For example, when a voltage is applied to test pad 225-1 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2.; Column 6 Line 17-27); and
transmitting the electrical input [voltage/current] through the contact structures [126, 215] to render an output from another test terminal [225-2] electrically coupled to the semiconductor package [120A] (For example, when a voltage is applied to test pad 225-1 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27),
wherein the output [resistance] is to be rendered as the output pattern (resistance to measure open circuit) (Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650); Column 6 Line 47-51).
.
Regarding claim 12, Hsieh teaches a method,
wherein transmitting the electrical input through the contact structures [126, 215] (For example, when a voltage is applied to test pad 225-1 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2.; Column 6 Line 17-27) comprises having the electrical input transmitted through the contact structures which are configured in a daisy chain manner forming a series connection (FIG. 6 is a flow diagram showing a method for testing IC package 120A for solder joint fractures in accordance with another aspect of the present invention. First, the daisy chain structure of assembly 200 (see FIGS. 4 and 5) is formed by connecting associated pairs of solder balls 126 of IC package 120A and associated pairs of contact pads 215 of test PCB 210 (step 610). This process is separated into three parts. Connection of associated pairs of solder balls 126 to form the first daisy chain portion (step 612) and production of test PCB 210 to form the second daisy chain portion (step 614) can be performed in any order. Once package 120A and test PCB 210 are completed, package 120A is mounted on test PCB 210 (step 616) using; Column 6 Line 28-40).
Regarding claim 13, Hsieh teaches a method,
wherein the electronic system comprises an other semiconductor package (the remaining other packages) that is in addition to the semiconductor package (A method and assembly for testing multiple IC packages for solder joint fractures; Abstract Line 1-2),
wherein the method (Figure 6) further comprises
repeating the providing [660] and the transmitting for the other semiconductor
package (When an initial open circuit is detected for a package, the location of the open circuit is noted, and an optional post-failure counter (PFCNT) is initiated. Thermal cycling is again performed (step 660) and the location of each additional open circuit (fracture) on the remaining other packages is identified using methods described below with reference to FIGS. 7 and 8 (step 670). The optional post-failure counter is then incremented, and steps 660 and 670 are repeated for a predetermined amount of time (e.g., 1,000 cycles). Upon completion, an optional post failure analysis is performed; Column 6 Line 53-62).
Regarding claim 14, Hsieh teaches a method,
wherein determining the presence or absence of the warpage (solder joint failure) in the electronic system [200] based on the presence or absence of the output pattern (resistance to determine an open circuit) comprises
comparing, if an output pattern is present, the output pattern or amplitude of the output pattern to a pattern rendered from the electronic system with no warpage (Next, thermal cycle testing is initiated by setting a counter to zero (step 620), assembly 200 is heated and cooled according to predefined parameters (step 630), and the counter is incremented to register the number of completed thermal cycles (step 640). Solder joint fracture testing is then performed as described above (e.g., a voltage is applied at first test pad 225-1 and resistance is measured at final test pad 225-2) to determine if an initial open circuit has occurred (step 650). If no open circuit is detected, then thermal cycling is repeated and current measured until an open circuit occurs. When an initial open circuit is detected for a package, the location of the open circuit is noted, and an optional post-failure counter (PFCNT) is initiated. Thermal cycling is again performed (step 660) and the location of each additional open circuit (fracture) on the remaining other packages is identified using methods described below with reference to FIGS. 7 and 8 (step 670). The optional post-failure counter is then incremented, and steps 660 and 670 are repeated for a predetermined amount of time (e.g., 1,000 cycles). Upon completion, an optional post failure analysis is performed; Column 6 Line 43-63).
Regarding claim 15, Hsieh teaches a method for method for forming an electronic system (an assembly for analyzing solder joint fractures in response to thermal cycling includes an IC package mounted (i.e., soldered) to a test PCB; Column 2 Line 66-67 & Column 3 Line 1; This invention relates to the field of integrated circuits (ICs), and more specifically to IC packages; Column 1 Line 8-9; FIG. 6 is a flow diagram showing a method for testing IC package 120A for solder joint fractures; Column 6 Line 28-29; FIG. 4 is a perspective view showing an assembly 200 for testing BGA packages; Column 4 Line 61-62), the method comprising:
forming a semiconductor package [120A] (BGA Package 120A as the semiconductor package) (Assembly 200 includes BGA package 120A; Column 4 Line 63-64; BGA package 120A includes package substrate 121; Column 4 Line 66-67; A BGA package (Ball Grid Array) is a specific type of semiconductor package; https://www.bing.com/search?q=semiconductor%20package%20and%20BGA%20package%20same%20&qs=n&form=QBRE&sp=-1&ghc=1&lq=0&pq=semiconductor%20package%20and%20bga%20package%20same%20&sc=9-43&sk=&cvid=7F234D3BA5D24F7F94FA2EFF3EF519FF); and
coupling the semiconductor package [120A] to a circuit board [210] (a test printed circuit board (PCB) 210; Column 4 Line 65) (FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2. Contact pads 215 are arranged to match the footprint of IC package 120A such that, when BGA package 120A is mounted on test PCB 210, each solder ball 126 (e.g., solder ball 126-1) contacts an associated contact pad 215 (e.g., contact pad 215-1, as indicated by the dashed arrow in FIG. 4). In accordance with another aspect of the present invention, associated pairs of contact pads 215 are connected by conductive lines 220, 230-1 and 230-2 to form a second (lower) half of the daisy chain (the second daisy chain portion) that extends between first test pad 225-1 and second test pad 225-2; Column 5 Line 39-53,
arranging contact structures [125, 126, 128, 205, 215 [1-4], 220] (contact pads 125, solder balls 126, and conductive vias 128, bond wires 205, contact pads 215 and conductive (e.g., metal) lines 220 as the contact structure) on the semiconductor package [120A] and the circuit board [210] (FIG. 4, BGA package 120A includes package substrate 121, contact pads 125, solder balls 126, and conductive vias 128; Column 4 Line 66-67 & Column 5 Line 1; Assembly 200 includes BGA package 120A that includes bond wires 205; Column 4 Line 63-64; FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42),
wherein the contact structures [125, 126, 128, 205, 215 [1-4], 220] configured to have an output terminal [225-2] of one contact structure [215-5] connected to an input terminal [225-1] of another contact structure [215-4] (Note also that test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2; Column 5 Line 66-67 & Column 6 Line 1-3) so as to render a continuous electrical pathway through the contact structures [125, 126, 128, 205, 215 [1-4], 220] (FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2. Contact pads 215 are arranged to match the footprint of IC package 120A such that, when BGA package 120A is mounted on test PCB 210, each solder ball 126 (e.g., solder ball 126-1) contacts an associated contact pad 215 (e.g., contact pad 215-1, as indicated by the dashed arrow in FIG. 4). In accordance with another aspect of the present invention, associated pairs of contact pads 215 are connected by conductive lines 220, 230-1 and 230-2 to form a second (lower) half of the daisy chain (the second daisy chain portion) that extends between first test pad 225-1 and second test pad 225-2; Column 5 Line 39-53; For example, when a voltage is applied to test pad 225-1 in Figure 5 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27), and
wherein the continuous electrical pathway (test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2 makes continuous electrical pathway where current flows: Figure 5 dash line shows the electrical pathway) renders an output pattern in response to an electrical stimulus [voltage/current] introduced to the electronic system [200] (For example, when a voltage is applied to test pad 225-1 in Figure 5 and test pad 225-2 is grounded, a current flows from test pad 225-1 to contact pad 215-4, from contact pad 215-4 to solder ball 126-4, from solder ball 126-4 to bond wire 205-3, and from bond wire 205-3 to solder ball 126-5/contact pad 215-5. This pattern is repeated as the current flows along conductive line 220-2 to bond wire 205-4 to conductive line 220-3 to bond wire 205-1 to conductor 220-1, etc., along the path indicated by the dashed-line arrow until it reaches bond wire 205-5 and is transmitted to test pad 225-2; Column 6 Line 17-27; FIG. 5 is a perspective view showing assembly 200 after BGA package 120 is mounted on test PCB 210 (note that BGA substrate 121 and the substrate portion of test PCB 210 are removed for clarity). The dashed-line arrow generally indicates a current path defined by the daisy chain by which a current passes through assembly 200 between test pad 225-1 and test pad 225-2; Column 6 Line 6-12).
Regarding claim 16, Hsieh teaches a method,
further comprising arranging the contact structures [125, 126, 128, 205, 215 [1-4], 220] in a daisy chain manner forming a series connection (Figure 5 shows the series connection) (Accordingly, a segment of the daisy chain is formed between contact pads 125-1 and contact pad 125-4 that passes along wire bond 205-1, conductive line 220-1, and wire bond 205-2. Note also that test pad 225-1 is connected to a first end of the daisy chain (i.e., contact pad 215-4) by conductive line 230-1, and test pad 225-2 is connected to a second end of the daisy chain (i.e., contact pad 215-5) by conductive line 230-2; Column 5 Line 63-67 & Column 6 Line 1-3; FIG. 6 is a flow diagram showing a method for testing IC package 120A for solder joint fractures in accordance with another aspect of the present invention. First, the daisy chain structure of assembly 200 (see FIGS. 4 and 5) is formed by connecting associated pairs of solder balls 126 of IC package 120A and associated pairs of contact pads 215 of test PCB 210 (step 610). This process is separated into three parts. Connection of associated pairs of solder balls 126 to form the first daisy chain portion (step 612) and production of test PCB 210 to form the second daisy chain portion (step 614) can be performed in any order. Once package 120A and test PCB 210 are completed, package 120A is mounted on test PCB 210 (step 616) using; Column 6 Line 28-40).
Regarding claim 17, Hsieh teaches a method, further comprising
arranging some contact structures [215 [1-4], 220] (FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42) proximal to the semiconductor package [120A] (Figure 5 shows some contact structures [215 [1-4], 220] are configured proximal to the semiconductor package [120A]) and arranging some contact structures [225-1, 225-2] distal from the semiconductor package [120A] (figure 5 shows some contact structures [225-1, 225-2] are configured distal from the semiconductor package [120A]).
Regarding claim 18, Hsieh teaches a method of claim 17, comprising
forming the contact structures [215 [1-4], 220] coplanar to the circuit board [210] (Referring to the lower portion of FIG. 4, test PCB 210 includes contact pads 215 that are arranged to match the footprint of IC package 120A, conductive (e.g., metal) lines 220, a first test pad 225-1 and a second test pad 225-2; Column 5 Line 39-42; Figure 4 shows contact pads 215 are formed coplanar to the circuit board 210).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh ‘986 B1 in view of Sunder et al. (Hereinafter, “Sunder”) in the US Patent Application Publication Number US 20210215754 A1.
Regarding claim 5, Hsieh fails to teach an electronic system, wherein one or more of the contact structures are operable as or comprise a resistor, a capacitor, an inductor, a diode, or a transistor.
Sunder teaches an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis (Abstract),
wherein one or more of the contact structures are operable as or comprise a resistor [312, 322] in Figure 3, a capacitor, an inductor, a diode, or a transistor (FIG. 3 illustrates a schematic circuit diagram for an example electronic package, according to embodiments described herein. The package 100 includes the flow path 221, discussed in FIG. 2 The IC 110 also includes a state machine 305 which controls the various flow paths shown in FIG. 3 through a state machine control path 306. A calibration path 310 for the IC 110 includes a switch 311 under control of the state machine 305 and a resistance for the path, resistance 312. A calibration path 320 for the IC 105 includes a switch 321 under control of the state machine 305 and a resistance for the path, resistance 322. The flow path 221 includes a switch 331 under control of the state machine 305 and various resistances, including the resistance of the path in the IC 110, resistance 332, resistance of the connections points (resistances 333), and the resistance of the path in the IC 105 (resistances 334); Paragraph [0026] Line 1-16). The purpose of doing so is to provide an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, to eliminate the need for external testing equipment and analysis, to allow for both real time testing in the assembly process of the electronic packages and during use of the electronic package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the contact structures of Hsieh by introducing resistors a disclosed by Sunder, because Sunder teaches to include resistors as the contact structures provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, eliminates the need for external testing equipment and analysis, allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Liu et al. (US 10159151 B1) discloses, “Chip Package Circuit Board Module- A chip package circuit board module including a circuit board and at least one original chip is provided. The circuit board includes at least one first pad, at least one second pad and at least one substitute pad. The at least one second pad is located besides the at least one first pad and separated from the at least one first pad. The at least one substitute pad is adjacent to the at least one second pad and separated from the at least one first pad and the at least one second pad. The at least one original chip is connected to the at least one first pad and at least one the second pad, respectively (Abstract). FIG. 1 is a schematic diagram of a chip package circuit board module according to an embodiment of the invention. With reference to FIG. 1, a chip package circuit board module 100 of the present embodiment includes a circuit board 110 and at least one original chip 120. The circuit board 110 includes at least one first pad 112, at least one second pad 115 and at least one substitute pad 117. In the present embodiment, the first pad 112 includes at least one first branch 113, and these first branches 113 are connected to one another and correspond to the second pad 115 and the substitute pad 117, respectively. In view of FIG. 1, the first branches 113 of the first pad 112 are connected through a connection portion 111 (Column 3 Line 49-61-However Liu does not disclose wherein the semiconductor package and the circuit board comprise contact structures configurable to have an output terminal of one contact structure connected to an input terminal of another contact structure so as to render a continuous electrical pathway through the contact structures, wherein the contact structures are configured in a daisy chain manner forming a series connection.”
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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