DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/08/2025 has been entered.
Response to Amendment
This office action is in response to the amendment filed on 12/08/2025. Claims 1-20 are pending. Claims 1, 8-9, and 14 are amended.
Response to Arguments
Applicant's arguments filed 12/08/2025 have been fully considered but they are not persuasive.
On page 9 of the Remarks, Applicant submits:
“In Abernathy, the counter associated with an instruction is not used in the same way as the lifetime tracking value in claim 1. In Abernathy, the counter associated with an instruction is not decremented to track execution of the instruction through pipeline stages. Rather, Abernathy's counter is indicative of how long an instruction is allowed to wait in a queue to be executed before being considered at the commit point”
This is the same argument that Applicant submitted on page 9 of the Remarks filed 06/25/2025, which was responded to in the Final Rejection dated 08/06/2025. This argument is not persuasive because Abernathy’s counter is decremented to track execution of the instruction through the pipeline stages. [0011] discloses that “As the instruction progresses through the parallel pipeline, its counter is decremented until it reaches zero.” and Fig. 1 shows that counters are assigned at issue 130 and states that “counters decrement as they proceed through pipelines”. Applicant’s argument cites a partial sentence in [0029] to support the position that Abernathy’s counter is not decremented to track execution of the instruction through pipeline stages, however, the full sentence in [0029] states “During each instruction cycle that the instruction is waiting to be executed by an instruction unit, whether in VSU issue queue 180 or in the execution pipeline, the counter is decremented”, which further supports Examiner’s position that Abernathy’s counter decrements each cycle the instruction is in the execution pipeline.
On pages 9-10 of the Remarks, Applicant submits:
“Moreover, since Abernathy does not track in-progress execution of an instruction, it also fails to teach preemption of in-progress execution to complete an interrupt, which involves storing a state indicating where in pipeline stages execution of the instruction stopped, completing the interrupt and then restoring the pipeline stages for continued execution of the instruction from where the stoppage occurred. To this end, claim 1 further recites specific functionality based on encountering an interrupt and also specific functionality based on completion of the interrupt.
Hsu does not offset these deficiencies in Abernathy. Hsu is directed to a computer processor pipeline that includes working registers connected to form a working pipeline and shadow registers connected to form a shadow register chain. On a context switch, data associated with a process in the working pipeline are swapped with data associated with a different associated with a different process stored in the shadow register chain. There is no equivalent in Hsu of the lifetime tracking counter and its use, as recited in claim 1.”
However, this argument is not persuasive because it does not consider the teachings of the references or how they are combined. As explained above, Abernathy teaches the lifetime tracking counter, which tracks in-progress execution of an instruction. Hsu teaches saving the context/state of the pipeline stages in a capture queue based on an interrupt and restoring the state based on completion of the interrupt, where the context is all of the data and register values that describe a process’s current state of execution (Hsu [0009]). The Office Action modifies Abernathy in view of the teachings of Hsu to save the context/state of the pipeline stages in a capture queue when there is an interrupt, which would include the values of the counters as part of the context/state. Since the counters track in-progress execution of an instruction, the saved counter value of an instruction would indicate where in the set of pipeline stages that execution of the instruction stopped. In the example of Fig. 2 of Abernathy where the counter for each instruction is initialized to 10 and decremented as the instruction passes through the pipeline, a counter value of 6, for example, indicates the location of Instruction H in the pipeline, and if there is an interrupt this counter value would be saved as part of the context/state of the pipeline.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “the instruction” on page 4 lines 6 and 13. It is unclear whether these refer to the instruction introduced in claim 1 or the second instruction introduced in line 8. For purposes of examination these will be interpreted as referring to the second instruction.
Claim 8 recites “the state” on page 4 line 8. It is unclear whether this refers to the state of the set of pipeline stages introduced in claim 1 or the state of the second set of pipeline stages introduced on page 4 line 7. For purposes of examination this will be interpreted as referring to the state of the second set of pipeline stages.
Claim 8 recites “the set of pipeline stages” on page 4 line 9. It is unclear whether this refers to the first set of pipeline stages introduced in line 3 or the second set of pipeline stages introduced in line 7. For purposes of examination this will be interpreted as referring to the second set of pipeline stages.
Claim 8 recites “the stoppage” on page 4 lines 13 and 16. It is unclear whether this refers to the stoppage of the instruction described in claim 1 or the stoppage of the second instruction described on page 4 line 9. For purposes of examination this will be interpreted as referring to the stoppage of the second instruction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7-9, 12-14, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0083742 (hereinafter, Abernathy) in view of US 2006/0294344 (hereinafter, Hsu).
Regarding claim 1, Abernathy teaches:
1. A circuit device comprising:
a processor (Fig. 1) that includes:
a functional unit that includes a set of pipeline stages, each pipeline stage of which is configured to execute a respective portion of an instruction (Fig. 1: fixed point unit 150, which includes 10 pipeline stages, or VMX unit 182/330 (see Fig. 1 and Fig. 3), which also has stages as indicated by [0040], see also [0004]-[0005] indicating that each stage of a pipeline executes a respective portion of an instruction);
a scoreboard coupled to the functional unit ([0029]: issue logic 130/180 and the counters assigned to each instruction are collectively a scoreboard since 130/180 are used to resolve instruction dependencies, see [0034]) and configured to:
store a lifetime tracking value that is initially set to indicate an expected number of cycles to execute the instruction ([0029]: issue logic 130 assigns/stores a counter value, i.e., a lifetime tracking value, to each instruction it receives based on the pipeline length, i.e., the expected number of cycles to execute the instruction, see also [0031] and Fig. 2 220);
decrement the lifetime tracking value to track execution of the instruction through the set of pipeline stages ([0032]: the counter is decremented as the instruction progresses through the pipeline, i.e., to track execution of the instruction through the pipeline stages, see also [0036] describing that the counter is decremented based on being issued from 180 to an execution unit pipeline);
While Abernathy also teaches flushing instructions based on an exception and resuming processing after flushing, see [0039]-[0040], Abernathy does not teach:
a capture queue associated with the functional unit;
the scoreboard coupled to the capture queue;
based on an interrupt, cause execution of the instruction to stop and cause a state of the set of pipeline stages that is associated with the instruction to be stored in the capture queue, the state indicating where in the set of pipeline stages execution of the instruction stopped; and
based on completion of the interrupt and on the lifetime tracking value at completion of the interrupt:
cause the state of the set of pipeline stages to be restored for continued execution of the instruction from where the stoppage occurred; and
cause the execution of the instruction to be resumed from where the stoppage occurred using a subset of the set of pipeline stages.
Hsu teaches:
a capture queue associated with a functional unit (Fig. 1, the shadow registers associated with each of the pipe stages are collectively a capture queue, see also [0026]);
based on an interrupt, cause execution of the instruction to stop and cause a state of the set of pipeline stages that is associated with an instruction to be stored in the capture queue ([0027]-[0028]: based on a context switch/exception (which is an interrupt in the sense that it interrupts the running process, see [0011]), the contents of the working registers, i.e., a state of the set of pipeline stages associated with an executing instruction, are stored in the shadow registers and the process is halted, which includes stopping execution of instructions of the process); and
based on completion of the interrupt:
cause the state of the set of pipeline stages to be restored for continued execution of the instruction from where the stoppage occurred ([0029]-[0030]: based on a second context switch event (which may be a return from exception instruction, i.e., a completion of the interrupt, see [0027]), the contents of the working registers are restored and the first process is resumed, i.e., the instructions of the first process are resumed from where the stoppage occurred); and
cause the execution of the instruction to be resumed from where the stoppage occurred using a subset of the set of pipeline stages ([0029]-[0030]: based on a second context switch event (which may be a return from exception instruction, i.e., a completion of the interrupt, see [0027]), the contents of the working registers are restored and the first process is resumed, i.e., the instructions of the first process are resumed from where the stoppage occurred, using the remaining pipeline stages)).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the issue logic of Abernathy to support context switching as taught by Hsu by coupling working registers and shadow registers to each stage of each pipeline as taught by Hsu. In this combination, the issue logic 130/180 and the counters of Abernathy (which indicates where in the set of pipeline stages execution of an instruction stopped) would be coupled to the working/shadow registers via the pipelines and would cause the state/execution to be restored/resumed on completion of an interrupt/exception based on the counter/lifetime tracking value at completion of the interrupt (since Abernathy teaches maintaining instructions based on their counter values and flushing all other instructions, see [0030]). One of ordinary skill in the art would have been motivated to make this modification to support context switching in the pipeline in one clock cycle (Hsu [0028]).
Regarding claim 4, Abernathy in view of Hsu teaches:
4. The circuit device of claim 1,
Abernathy in view of Hsu, as currently mapped, does not teach:
the capture queue is a first capture queue;
the processor includes a second capture queue; and
the scoreboard is configured to:
based on the interrupt, cause the state of the set of pipeline stages to be stored in the second capture queue via the first capture queue; and
based on completion of the interrupt, cause the state of the set of pipeline stages to be restored from the second capture queue via the first capture queue.
However, Hsu further teaches:
the capture queue is a first capture queue (Fig. 1 shadow registers);
the processor includes a second capture queue (Fig. 1, context cache 18); and
based on an interrupt, cause the state of the set of pipeline stages to be stored in the second capture queue via the first capture queue ([0039] describes that a process context/state stored in the shadow registers may be written to the context cache, where the state is first stored to the shadow register chain based on an exception/interrupt, see [0027]-[0028], that is, based on an interrupt, a state of the pipeline may be stored from the working registers to the shadow registers before being written from the shadow registers to the context cache); and
based on completion of the interrupt, cause the state to be restored to the set of pipeline stages to be restored from the second capture queue via the first capture queue ([0039] further describes loading a process context/state from the context cache into the shadow registers so that the process may be restored to the pipeline by swapping the working registers with the shadow registers, where the process may be restored based on a return from exception/completion of the interrupt, see [0027], that is an exception/interrupt may cause a state of the pipeline to be stored from the working registers to the shadow registers and then to the context cache, and a return from exception/completion of the interrupt may cause the state of the pipeline to be restored from the context cache via the shadow registers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abernathy to further include the context cache of Hsu. One of ordinary skill in the art would have been motivated to make this modification to support more contexts (Hsu Abstract).
Regarding claim 5, Abernathy in view of Hsu teaches:
5. The circuit device of claim 4, wherein the processor includes a cache memory that includes the second capture queue (Hsu [0036]: the context cache/second capture queue is a cache memory).
Regarding claim 7, Abernathy in view of Hsu teaches:
7. The circuit device of claim 1, wherein the set of pipeline stages are configured to write a result of the instruction when the lifetime tracking value is zero (Abernathy [0029]: the counters are initialized to a value corresponding to the length of the pipeline that determines the instruction commit point and then decremented to zero, that is, the instructions will commit (i.e., write their result) when their counter is zero).
Regarding claim 8, Abernathy in view of Hsu teaches:
8. The circuit device of claim 1, wherein:
the functional unit is a first functional unit (Abernathy Fig. 1, 182 (also shown as 330 in Fig. 3) is a first functional unit);
the set of pipeline stages is a first set of pipeline stages (the stages of 182/330 are a first set of pipeline stages, see [0040] which indicates that 182/330 has pipeline stages);
the capture queue is a first capture queue (in the combination, the shadow registers (Hsu Fig. 1) are coupled to each stage of each pipeline, where the shadow registers coupled to the stages of 182/330 are a first capture queue);
the lifetime tracking value is a first lifetime tracking value (the counter value of any instruction sent to 182/330, see Abernathy [0036]);
the processor includes:
a second functional unit that includes a second set of pipeline stages, each pipeline stage of which is configured to execute a respective portion of a second instruction (Abernathy Fig. 1 150 is a second functional unit that includes a set of pipeline stages, see also [0004]-[0005] indicating that each stage of a pipeline executes a respective portion of an instruction); and
a second capture queue associated with the second functional unit (in the combination, the shadow registers (Hsu Fig. 1) are coupled to each stage of each pipeline, where the shadow registers coupled to the stages of 150 are a second capture queue); and
the scoreboard is coupled to the second functional unit (Abernathy Fig. 1 shows the issue logic 130 coupled to 150) and to the second capture queue (in the combination, the issue logic 130 is coupled to the shadow registers of 150 by being coupled to 150) and configured to:
store a second lifetime tracking value that is initially set to indicate an expected number of cycles to execute the second instruction using the second set of pipeline stages (the counter value that the issue logic 130 assigns/stores to any instruction sent to 150 is a second lifetime tracking value, see Abernathy [0029] describing that issue logic 130 assigns/stores a counter value, i.e., a lifetime tracking value, to each instruction it receives based on the pipeline length, i.e., the expected number of cycles to execute the instruction, see also [0031] and Fig. 2 220);
decrement the second lifetime tracking value to track execution of the second instruction through the set of pipeline stages (Abernathy [0032] and claim 9 lines 13-15: the counter is decremented as the instruction progresses through the pipeline, i.e., based on execution of the instruction in the pipeline);
based on the interrupt, cause execution of the instruction to stop and cause a state of the second set of pipeline stages that is associated with the second instruction to be stored in the second capture queue (in the combination, an interrupt/exception would cause the state of 150 associated with an executing instruction to be stored in its shadow registers/the second capture queue and the execution of the instruction to stop), the state indicating where in the set of pipeline stages execution of the second instruction stopped (in the combination, the saved state includes the counter values, which indicate where in the set of pipeline stages execution of an instruction stopped); and
based on completion of the interrupt and on the second lifetime tracking value at the completion of the interrupt:
cause the state of the second set of pipeline stages to be restored for continued execution of the instruction from where the stoppage occurred (in the combination, the state of 150 would be restored based on a return from exception/completion of the interrupt, see Hsu [0029]-[0030], and based on the instruction counter values (since Abernathy teaches maintaining instructions based on their counter values and flushing all other instructions, see [0030]), i.e., the instructions of the process are resumed from where the stoppage occurred); and
cause the execution of the second instruction to be resumed from where the stoppage occurred using a subset of the second set of pipeline stages (in the combination, the execution of second instruction would resume using the remaining stages (i.e., a subset of the second set of stages) based on the state being restored and its process resuming, see Hsu [0029]-[0030], i.e., the instructions of the process are resumed from where the stoppage occurred).
Regarding claim 9, Abernathy teaches:
9. A circuit device comprising:
a processor (Fig. 1) that includes:
a functional unit that includes a set of pipeline stages, each pipeline stage of which is configured to execute a respective portion of an instruction (Fig. 1: fixed point unit 150, which includes 10 pipeline stages, or VMX unit 182/330 (see Fig. 1 and Fig. 3), which also has stages as indicated by [0040], see also [0004]-[0005] indicating that each stage of a pipeline executes a respective portion of an instruction);
a scoreboard coupled to the functional unit ([0029]: issue logic 130/180 and the counters assigned to each instruction are collectively a scoreboard since 130/180 are used to resolve instruction dependencies, see [0034]) and configured to:
store a lifetime tracking value that is initially set to indicate an expected number of cycles to execute the instruction ([0029]: issue logic 130 assigns/stores a counter value, i.e., a lifetime tracking value, to each instruction it receives based on the pipeline length, i.e., the expected number of cycles to execute the instruction, see also [0031] and Fig. 2 220);
decrement the lifetime tracking value to track execution of the instruction through the set of pipeline stages ([0032]: the counter is decremented as the instruction progresses through the pipeline, i.e., to track execution of the instruction through the pipeline stages, see also [0036] describing that the counter is decremented based on being issued from 180 to an execution unit pipeline);
While Abernathy also teaches flushing instructions based on an exception and resuming processing after flushing, see [0039]-[0040], Abernathy does not teach:
a capture queue associated with the functional unit;
the scoreboard coupled to the capture queue;
based on an exception event, cause execution of the instruction to stop and cause a state of the set of pipeline stages that is associated with the instruction to be stored in the capture queue, the state indicating where in the set of pipeline stages execution of the instruction stopped; and
based on completion of the exception event and on the lifetime tracking value at the completion of the exception event:
cause the state of the set of pipeline stages to be restored for continued execution of the instruction from where the stoppage occurred; and
cause the execution of the instruction to be completed from where the stoppage occurred using a subset of the set of pipeline stages.
Hsu teaches:
a capture queue associated with a functional unit (Fig. 1, the shadow registers associated with each of the pipe stages are collectively a capture queue, see also [0026]);
based on an exception event, cause execution of the instruction to stop and cause a state of the set of pipeline stages that is associated with an instruction to be stored in the capture queue ([0027]-[0028]: based on a context switch/exception, the contents of the working registers, i.e., a state of the set of pipeline stages associated with an executing instruction, are stored in the shadow registers and the process is halted, which includes stopping execution of instructions of the process); and
based on completion of the exception event:
cause the state of the set of pipeline stages to be restored for continued execution of the instruction from where the stoppage occurred ([0029]-[0030]: based on a second context switch event (which may be a return from exception instruction, see [0027]), the contents of the working registers are restored and the first process is resumed, i.e., the instructions of the first process are resumed from where the stoppage occurred); and
cause the execution of the instruction to be completed from where the stoppage occurred using a subset of the set of pipeline stages ([0029]-[0030]: based on a second context switch event (which may be a return from exception instruction, see [0027]), the contents of the working registers are restored and the first process is resumed, i.e., the instructions of the first process are completed from where the stoppage occurred, using the remaining pipeline stages).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the issue logic of Abernathy to support context switching as taught by Hsu by coupling working registers and shadow registers to each stage of each pipeline as taught by Hsu. In this combination, the issue logic 130/180 and the counters of Abernathy (which indicates where in the set of pipeline stages execution of an instruction stopped) would be coupled to the working/shadow registers via the pipelines and would cause the state/execution to be restored/resumed on completion of an interrupt/exception based on the counter/lifetime tracking value at completion of the interrupt (since Abernathy teaches maintaining instructions based on their counter values and flushing all other instructions, see [0030]). One of ordinary skill in the art would have been motivated to make this modification to support context switching in the pipeline in one clock cycle (Hsu [0028]).
Regarding claim 12, Abernathy in view of Hsu teaches:
12. The circuit device of claim 9,
Abernathy in view of Hsu, as currently mapped, does not teach:
the capture queue is a first capture queue;
the processor includes a second capture queue; and
the scoreboard is configured to:
based on the exception event, cause the state of the set of pipeline stages to be stored in the second capture queue via the first capture queue; and
based on completion of the exception event, cause the state of the set of pipeline stages to be restored from the second capture queue via the first capture queue.
However, Hsu further teaches:
the capture queue is a first capture queue (Fig. 1 shadow registers);
the processor includes a second capture queue (Fig. 1, context cache 18); and
based on an exception event, cause the state of the set of pipeline stages to be stored in the second capture queue via the first capture queue ([0039] describes that a process context/state stored in the shadow registers may be written to the context cache, where the state is first stored to the shadow register chain based on an exception, see [0027]-[0028], that is, based on an exception, a state of the pipeline may be stored from the working registers to the shadow registers before being written from the shadow registers to the context cache); and
based on completion of the exception event, cause the state to be restored to the set of pipeline stages to be restored from the second capture queue via the first capture queue ([0039] further describes loading a process context/state from the context cache into the shadow registers so that the process may be restored to the pipeline by swapping the working registers with the shadow registers, where the process may be restored based on a return from exception, see [0027], that is an exception may cause a state of the pipeline to be stored from the working registers to the shadow registers and then to the context cache, and a return from exception may cause the state of the pipeline to be restored from the context cache via the shadow registers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abernathy to further include the context cache of Hsu. One of ordinary skill in the art would have been motivated to make this modification to support more contexts (Hsu Abstract).
Regarding claim 13, Abernathy in view of Hsu teaches:
13. The circuit device of claim 12, wherein the processor includes a cache memory that includes the second capture queue (Hsu [0036]: the context cache/second capture queue is a cache memory).
Regarding claim 14, Abernathy teaches:
14. A method comprising:
receiving an instruction for execution using a set of pipeline stages ([0031]: an instruction is received by issue logic at step 210 for execution using a set of pipeline stages of an execution unit), each pipeline stage of which is configured to execute a respective portion of an instruction (Fig. 1: fixed point unit 150, which includes 10 pipeline stages, or VMX unit 182/330 (see Fig. 1 and Fig. 3), which also has stages as indicated by [0040], are a set of pipeline stages, see also [0004]-[0005] indicating that each stage of a pipeline executes a respective portion of an instruction);
based on the receiving of the instruction, determining a lifetime tracking value based on an expected number of cycles to execute the instruction ([0031]: based on the instruction, a counter/lifetime tracking value is initialized/determined based on the pipeline length, i.e., based on the expected number of cycles to execute the instruction, at step 220);
executing one or more portions of the instruction using the set of pipeline stages ([0031]: at step 230 the instruction is issued to the appropriate execution unit pipeline to be executed);
during the executing of the one or more portions of the instruction:
decrementing the lifetime tracking value to track execution of the instruction through the set of pipeline stages ([0032]: the counter is decremented as the instruction progresses through the pipeline, i.e., to track execution of the instruction through the pipeline stages, see also [0036] describing that the counter is decremented based on being issued from 180 to an execution unit pipeline);
While Abernathy also teaches flushing instructions based on an exception and resuming processing after flushing, see [0039]-[0040], Abernathy does not teach:
based on an interrupt, stopping execution of the instruction and storing a state of the set of pipeline stages in a capture queue, the state indicating where in the set of pipeline stages execution of the instruction stopped; and
based on completion of the interrupt and on the lifetime tracking value at the completion of the interrupt:
restoring the state to the set of pipeline stages for continued execution of the instruction from where the stoppage occurred; and
resuming execution of the instruction from where the stoppage occurred using a subset of the set of pipeline stages.
However, Hsu teaches:
based on an interrupt, stopping execution of the instruction and storing a state of the set of pipeline stages in a capture queue ([0027]-[0028]: based on a context switch/exception (which is an interrupt in the sense that it interrupts the running process, see [0011]), the contents of the working registers, i.e., a state of the set of pipeline stages associated with an executing instruction, are stored in the shadow registers); and
based on completion of the interrupt:
restoring the state to the set of pipeline stages for continued execution of the instruction from where the stoppage occurred ([0029]-[0030]: based on a second context switch event (which may be a return from exception instruction, i.e., a completion of the interrupt, see [0027]), the contents of the working registers are restored and the first process is resumed, i.e., the instructions of the first process are resumed from where the stoppage occurred); and
resuming execution of the instruction from where the stoppage occurred using a subset of the set of pipeline stage ([0029]-[0030]: based on a second context switch event (which may be a return from exception instruction, i.e., a completion of the interrupt, see [0027]), the contents of the working registers are restored and the first process is resumed, i.e., the instructions of the first process are resumed from where the stoppage occurred, using the remaining pipeline stages).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the issue logic of Abernathy to support context switching as taught by Hsu by coupling working registers and shadow registers to each stage of each pipeline as taught by Hsu. In this combination, the issue logic 130/180 and the counters of Abernathy (which indicates where in the set of pipeline stages execution of an instruction stopped) would be coupled to the working/shadow registers via the pipelines and would cause the state/execution to be restored/resumed on completion of an interrupt/exception based on the counter/lifetime tracking value at completion of the interrupt (since Abernathy teaches maintaining instructions based on their counter values and flushing all other instructions, see [0030]). One of ordinary skill in the art would have been motivated to make this modification to support context switching in the pipeline in one clock cycle (Hsu [0028]).
Regarding claim 17, Abernathy in view of Hsu teaches:
17. The method of claim 14,
Abernathy in view of Hsu, as currently mapped, does not teach:
the capture queue is a first capture queue;
the method comprises copying the state of the set of pipeline stages from the first capture queue to a second capture queue; and
the restoring of the state to the set of pipeline stages includes copying the state of the set of pipeline stages from the second capture queue via the first capture queue.
However, Hsu further teaches:
the capture queue is a first capture queue (Fig. 1 shadow registers);
the method comprises copying the state of the set of pipeline stages from the first capture queue to a second capture queue ([0039] describes that a process context/state stored in the shadow registers may be written to the context cache, where the state is first stored to the shadow register chain based on an exception/interrupt, see [0027]-[0028], that is, based on an interrupt, a state of the pipeline may be stored from the working registers to the shadow registers before being written from the shadow registers to the context cache); and
the restoring of the state to the set of pipeline stages includes copying the state of the set of pipeline stages from the second capture queue via the first capture queue ([0039] further describes loading a process context/state from the context cache into the shadow registers so that the process may be restored to the pipeline by swapping the working registers with the shadow registers, where the process may be restored based on a return from exception/completion of the interrupt, see [0027], that is an exception/interrupt may cause a state of the pipeline to be stored from the working registers to the shadow registers and then to the context cache, and a return from exception/completion of the interrupt may cause the state of the pipeline to be restored from the context cache via the shadow registers).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abernathy to further include the context cache of Hsu. One of ordinary skill in the art would have been motivated to make this modification to support more contexts (Hsu Abstract).
Regarding claim 19, Abernathy in view of Hsu teaches:
19. The circuit device of claim 1, wherein the scoreboard is configured to cause the execution of the instruction to be resumed starting with a pipeline stage, of the set of pipeline stages, immediately following a last pipeline stage, of the set of pipeline stages, to execute its respective portion of the instruction before the interrupt is received (Hsu teaches saving the state of each stage of a first process to a shadow register on a context switch and restoring the state of the first process on return from the context switch, see [0027]-[0030], this indicates that an instruction of the first process will resume at a stage of the pipeline, the previous pipeline stage that the instruction resumes from is a last pipeline stage to execute its respective portion of the instruction before the context switch/interrupt is received, and the pipeline stage that the instruction resumes from is a stage immediately following the last pipeline stage; in the combination with Abernathy, the issue logic/scoreboard will cause context switch which causes the execution of the instruction to be resumed).
Regarding claim 20, Abernathy in view of Hsu teaches:
20. The method of claim 14, wherein the resuming of the execution of the instruction includes resuming execution of the instruction starting with a pipeline stage, of the set of pipeline stages, immediately following a last pipeline stage, of the set of pipeline stages, to execute its respective portion of the instruction before the interrupt is received (Hsu teaches saving the state of each stage of a first process to a shadow register on a context switch and restoring the state of the first process on return from the context switch, see [0027]-[0030], this indicates that an instruction of the first process will resume at a stage of the pipeline, the previous pipeline stage that the instruction resumes from is a last pipeline stage to execute its respective portion of the instruction before the context switch/interrupt is received, and the pipeline stage that the instruction resumes from is a stage immediately following the last pipeline stage).
Claims 2-3, 10-11, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0083742 (hereinafter, Abernathy) in view of US 2006/0294344 (hereinafter, Hsu) and US 2007/0198814 (hereinafter, Abernathy 2).
Regarding claim 2, Abernathy in view of Hsu teaches:
2. The circuit device of claim 1, wherein the processor includes a vector data path that includes the functional unit ([0041] of Abernathy 2 indicates that the term VMX execution unit refers to a vector multimedia extension unit, thus the path of data to VMX unit 182 is a vector data path).
Regarding claim 3, Abernathy in view of Hsu teaches:
3. The circuit device of claim 1, wherein the processor includes a scalar data path that includes the functional unit (the path of data to fixed point unit 150 is a scalar data path (as opposed to a vector data path) since Fig. 1 of Abernathy indicates that VMX/vector instructions are sent to 180, see [0041] of Abernathy 2 which indicates that the term VMX execution unit refers to a vector multimedia extension unit).
Regarding claim 10, Abernathy in view of Hsu teaches:
10. The circuit device of claim 9, wherein the processor includes a vector data path that includes the functional unit ([0041] of Abernathy 2 indicates that the term VMX execution unit refers to a vector multimedia extension unit, thus the path of data to VMX unit 182 is a vector data path).
Regarding claim 11, Abernathy in view of Hsu teaches:
11. The circuit device of claim 9, wherein the processor includes a scalar data path that includes the functional unit (the path of data to fixed point unit 150 is a scalar data path (as opposed to a vector data path) since Fig. 1 of Abernathy indicates that VMX/vector instructions are sent to 180, see [0041] of Abernathy 2 which indicates that the term VMX execution unit refers to a vector multimedia extension unit).
Regarding claim 15, Abernathy in view of Hsu teaches:
15. The method of claim 14, wherein the set of pipeline stages is associated with a vector data path ([0041] of Abernathy 2 indicates that the term VMX execution unit refers to a vector multimedia extension unit, thus the path of data to VMX unit 182 is a vector data path).
Regarding claim 16, Abernathy in view of Hsu teaches:
16. The method of claim 14, wherein the set of pipeline stages is associated with a scalar data path (the path of data to fixed point unit 150 is a scalar data path (as opposed to a vector data path) since Fig. 1 of Abernathy indicates that VMX/vector instructions are sent to 180, see [0041] of Abernathy 2 which indicates that the term VMX execution unit refers to a vector multimedia extension unit).
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0083742 (hereinafter, Abernathy) in view of US 2006/0294344 (hereinafter, Hsu) and US 2005/0076189 (hereinafter, Wittenburg).
Regarding claim 6, Abernathy in view of Hsu teaches:
6. The circuit device of claim 1,
While Abernathy teaches stalling, see [0027], Abernathy in view of Hsu does not explicitly teach:
wherein the scoreboard is configured to maintain the lifetime tracking value to indicate a stall in a pipeline stage of the set of pipeline stages.
However, Wittenburg teaches pipeline stage counters that are incremented every cycle (analogous to the decrementing counters of Abernathy) if the pipeline is not stalled (i.e., the counters are maintained if the pipeline is stalled), see [0030].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abernathy to maintain its counters when a pipeline is stalled as suggested by Wittenburg to indicate a stall in the pipeline stages. One of ordinary skill in the art would have been motivated to make this modification to keep the counters updated with the pipeline stage (Wittenburg [0031), which would allow for more precise use of the counters.
Regarding claim 18, Abernathy in view of Hsu teaches:
18. The method of claim 14 further comprising, when execution of the instruction is stalled during the executing of the instruction:
Abernathy in view of Hsu does not teach:
maintaining the lifetime tracking value based on the pipeline stage at which the instruction is stalled.
However, Wittenburg teaches pipeline stage counters that are incremented every cycle (analogous to the decrementing counters of Abernathy) if the pipeline is not stalled (i.e., the counters are maintained if the pipeline is stalled), see [0030].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abernathy to maintain its counters when a pipeline is stalled as suggested by Wittenburg, where the value of the counter that is maintained is based on the stage at with the instruction is stalled. One of ordinary skill in the art would have been motivated to make this modification to keep the counters updated with the pipeline stage (Wittenburg [0031), which would allow for more precise use of the counters.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KASIM ALLI whose telephone number is (571)270-1476. The examiner can normally be reached Monday - Friday 9am 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183