Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The present office action is responsive to communication received 04/01/2026. Claims 1-18 are pending.
Claims 1-5, 9-10, and 17-18 have been amended.
Response to Arguments
The 112(a) rejection for claims 9 and 10 has been obviated in relation to the newly amended claim limitations
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner brings in reference Rezeanu to disclose “ a plurality of gating circuits coupled upstream of the plurality of ports, each gating circuit configured to blocking or granting read and write access from a source circuit to at least one of the plurality of ports depending on a release signal”. Rezeanu [column 3, lines 4-8 , lines 24-27, and lines 33-36, and lines 24-27] describes gates 56, 90, and 96 and how each of them may block access to the ports. We can see in Fig 3. of Rezeanu that these gates are positioned upstream.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over by Whetsel et al. (US 8468406) which is cited in IDS received 6/30/2023 in view of Shah et al. (US 11811609) in further view of Rezeanu et al. (US 7813213).
Regarding claim 1,
Whetsel teaches An integrated circuit, comprising:
a plurality of ports;
[The architecture includes the device's JTAG TAP 102, at least one additional access port 604 (Whetsel et al., column 4, lines 59-60, please refer to fig 15.)]
a plurality of configuration registers,
[The instruction register 304 stores an instruction that selects data to be shifted through the single bit bypass register or through a selected data register. (Whetsel et al., column 2, lines12-14)]
and a plurality of comparison circuits coupled to the plurality of gating circuits, each comparison circuit for comparing the [group] identifier with content of one of the configuration registers;
[FIG. 45 illustrates an example implementation of the device address register 4402 of FIG. 44 which includes a device address circuit 4502, a compare circuit 4504, a shift register 4506, and a flip flop (FF) 4508 connected as shown. (Whetsel et al., column 17, lines 1-4)]
[a device address register selectively responsive to the data register control signals to serially input address data from the TDI terminal of the device, comparing the input address to the address of the device, and in response to the addresses being the same, asserting a match signal output from the device address register (Whetsel et al., column 26, 37-42)]
and outputting the release signal to a gating circuit of the plurality of gating circuits.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Whetsel fails to explicitly disclose each configuration register for storing information to which group a gating circuit of the plurality of gating circuits belongs; a tag evaluation circuit for receiving an identifier from an access request from the source circuit and for outputting a group identifier for the access;
However in an analogous art Shah discloses:
each configuration register for storing information to which group a gating circuit of the plurality of gating circuits belongs; a tag evaluation circuit for receiving an identifier from an access request from the source circuit and for outputting a group identifier for the access;
[In operation 504, port groupings are created that logically group together (and therefore divide up) the ports of the target system. Each port grouping includes one or more of the plurality of ports, with certain ports being grouped together in a single port grouping based on at least one shared characteristic of individual ports in the single port grouping. In this way, multiple port groupings may be created, with each port grouping including ports which share common characteristic(s). (Shah et al., column 10, lines 27-35)]
[In operation 508, a particular port grouping which includes the target port on which the target discovery request was received is determined, e.g., which port grouping the target port belongs to is determined. In other words, membership of the target port in a particular port grouping is determined, such that the association between the target port and this particular port grouping is discovered, and any other ports in this particular port grouping (which share at least one characteristic with the target port) may be identified based on their membership in the particular port grouping. Any suitable technique may be used to make this determination, such as identifying a port grouping ID of the port grouping to which the target port belongs, ascertaining the distinguishing characteristic(s) of the target port and which port grouping has this/these distinguishing characteristic(s), etc. (Shah et al., column 11, lines 17-32, please refer to Fig 5. Where determining and outputting of group)]
Whetsel and Shah are considered to be analogous to the claimed invention because they are in the same field of port access. Therefore, it would have been obvious to one of ordinary skill in the art before the instant application effective filing date of the claimed invention to have modified the teachings of Whetsel to incorporate the teachings of Shah et al. to include specifying which group a gating circuit of the plurality of gating circuits belongs and a group identifier, in order to efficiently simplify target discovery and usage of target ports. (Shah et al., column 14, lines 36-40)]
Whetsel in view of Shah fails to explicitly disclose a plurality of gating circuits coupled upstream of the plurality of ports, each gating circuit configured to blocking or granting read and write access from a source circuit to at least one of the plurality of ports depending on a release signal;
However in an analogous art Rezeanu discloses a plurality of gating circuits coupled upstream of the plurality of ports, each gating circuit configured to blocking or granting read and write access from a source circuit to at least one of the plurality of ports depending on a release signal;
[The output 68 of the NOR gate 56 is the port one min-word line zero (P1_minwl0) signal that may block the access to port one's [Rezeanu et al., column 3, lines 4-8, please also refer to Fig. 3]
[The output 91 of the NOR gate 90 is the signal that may block the access to port two's (Rezeanu et al., column 3, lines 24-27)]
[The output 102 of the NOR gate 96 is the signal that may block the access to port three’s min-word line zero … (Rezeanu et al., column 3, lines 33-36)]
Whetsel, Shah, and Rezeanu are considered to be analogous to the claimed invention because they are in the same field of port access. Therefore, it would have been obvious to one of ordinary skill in the art before the instant application effective filing date of the claimed invention to have modified the teachings of Whetsel and Shah to incorporate the teachings of Rezeanu et al. to include a plurality of gating circuits coupled upstream of the plurality of ports, each gating circuit configured to blocking or granting read and write access from a source circuit to at least one of the plurality of ports depending on a release signal, in order to eliminate delay matching issues. (Rezeanu et al., column 2, lines 56-59)
Regarding claim 2,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit according to claim 1, whereby the gating circuit is further configured to receive an enable signal that indicates when either a read or write signal from or to the plurality of ports is requested or not requested.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Regarding claim 3,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit according to claim 1,
The integrated circuit according to claim 1, further comprising a programming circuit for the plurality of configuration registers, the programming circuit configured to change the content of the plurality of configuration registers.
[data registers 308 of the access ports 102, 1504, 1506 and 1508 in this disclosure may be used for any type of operation including but not limited to; a test operation, a debug operation, a trace operation, an emulation operation, a programming operation, an instrumentation operation, a functional digital operation, a functional mixed signal operation, and a functional analog operation. (Whetsel et al., column 14, lines 43-45)]
Regarding claim 4,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit according to claim 3, whereby the programming circuit is configured to change a group of the plurality of configuration registers, when the programming circuit receives enable signals from all comparison circuits that are assigned to the group of the plurality configuration registers.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Regarding claim 5,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit according to claim 1,
whereby a size of the group of gating circuits is 2, 4 or 8.
[Fig. 15, FIG. 6 has been replaced with an addressable access port selector 4304 and a gate 4306 has been inserted between the output of OE gating 612 and the enable input of TDO buffer 614. (Whetsel et al., column 16, lines 18-21)]
Regarding claim 6,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit according to claim 1,
The integrated circuit according to claim 1, further comprising
a plurality of tag evaluation circuits.
[the shift register 4506 captures the device address output from the device address circuit 4502, it outputs the captured device address to the comparator. Following the capture operation, the device address output from the shift register is the same as the device address output from the device address circuit, which causes the match output from the comparator 4504 to be set to the enable state. (Whetsel et al., column 17, lines 31-38)]
Regarding claim 7,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit according to claim 6, whereby a plurality of central processing units (CPUs) and/or virtual machines require accesses to one or more of the plurality of ports.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Regarding claim 8,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit according to claim 1,
whereby a plurality of groups of configuration registers can be configured concurrently.
[FIG. 45 illustrates an example implementation of the device address register 4402 of FIG. 44 which includes a device address circuit 4502, a compare circuit 4504, a shift register 4506, and a flip flop (FF) 4508 connected as shown. (Whetsel et al., column 17, lines 1-4)]
Regarding claim 9,
Whetsel discloses An integrated circuit, comprising:
a plurality of ports;
[The architecture includes the device's JTAG TAP 102, at least one additional access port 604 (Whetsel et al., column 4, lines 59-60)]
a plurality of tag evaluation circuits having a plurality of tag evaluation inputs, respectively, and having a plurality of tag evaluation outputs, respectively, the plurality of tag evaluation inputs coupled to the data and tag source circuit;
[the shift register 4506 captures the device address output from the device address circuit 4502, it outputs the captured device address to the comparator. Following the capture operation, the device address output from the shift register is the same as the device address output from the device address circuit, which causes the match output from the comparator 4504 to be set to the enable state. (Whetsel et al., column 17, lines 31-38)]
and a first comparison circuit having a first input, a second input, and an output, wherein the first input of the first comparison circuit is coupled to an output of a first tag evaluation circuit of the plurality of tag evaluation circuits,
[a compare circuit having first and second parallel inputs and a match output (Whetsel et al., column 26, lines 59-60)]
Wherein the second input of the first comparison circuit is coupled to a first configuration register,
[a compare circuit having first and second parallel inputs and a match output (Whetsel et al., column 26, lines 59-60)]
And wherein the output of the first comparison circuit is coupled to a first gating circuit of the plurality of gating circuits.
[a compare circuit having first and second parallel inputs and a match output (Whetsel et al., column 26, lines 59-60)]
Whetsel fails to explicitly disclose a data and tag source circuit coupled to each of the plurality of gating circuits, such that the respective ones of the plurality of gating circuits are arranged between the data and tag source circuit and the respective ones of plurality of ports;
However in an analogous art Shah discloses a data and tag source circuit coupled to each of the plurality of gating circuits, such that the respective ones of the plurality of gating circuits are arranged between the data and tag source circuit and the respective ones of plurality of ports;
[a particular port grouping which includes the target port on which the target discovery request was received is determined, e.g., which port grouping the target port belongs to is determined (Shah et al., column 11, lines 17-19)]
Whetsel and Shah are considered to be analogous to the claimed invention because they are in the same field of port access. Therefore, it would have been obvious to one of ordinary skill in the art before the instant application effective filing date of the claimed invention to have modified the teachings of Whetsel to incorporate the teachings of Shah et al. to include a data and tag source circuit coupled to each of the plurality of gating circuits, such that the respective ones of the plurality of gating circuits are arranged between the data and tag source circuit and the respective ones of plurality of ports, in order to efficiently simplify target discovery and usage of target ports. (Shah et al., column 14, lines 36-40)]
Whetsel in view of Shah fails to explicitly disclose a plurality of gating circuits wherein respective ones of the plurality of gating circuits are coupled to respective ones of the plurality of ports;
However in an analogous art Rezeanu discloses a plurality of gating circuits wherein respective ones of the plurality of gating circuits are coupled to respective ones of the plurality of ports;
[The output 68 of the NOR gate 56 is the port one min-word line zero (P1_minwl0) signal that may block the access to port one's [Rezeanu et al., column 3, lines 4-8, please also refer to Fig. 3]
[The output 91 of the NOR gate 90 is the signal that may block the access to port two's (Rezeanu et al., column 3, lines 24-27)]
[The output 102 of the NOR gate 96 is the signal that may block the access to port three's (Rezeanu et al., column 3, lines 33-36)]
Whetsel, Shah, and Rezeanu are considered to be analogous to the claimed invention because they are in the same field of port access. Therefore, it would have been obvious to one of ordinary skill in the art before the instant application effective filing date of the claimed invention to have modified the teachings of Whetsel and Shah to incorporate the teachings of Rezeanu et al. to include a plurality of gating wherein respective ones of the plurality of gating circuits are coupled to respective ones of the plurality of ports, in order to eliminate delay matching issues. (Rezeanu et al., column 2, lines 56-59)
Regarding claim 10,
Whetsel in view of Shah in further view of Rezeanu discloses The integrated circuit of claim 9, further comprising:
a second comparison circuit having a first input, a second input, and an output, wherein the first input of the second comparison circuit is coupled to an output of a second tag evaluation circuit of the plurality of tag evaluation circuits, wherein the second input of the second comparison circuit is coupled to a second configuration register, and the output of the second comparison circuit is coupled to a second gating circuit of the plurality of gating circuits.
[a compare circuit having first and second parallel inputs and a match output (Whetsel et al., column 26, lines 59-60)]
Regarding claim 11,
Whetsel in view of Shah in further view of Rezeanu discloses The integrated circuit of claim 10,
wherein the first gating circuit is configured to pass data from the data and tag source circuit to a first port of the plurality of ports when the first tag evaluation circuit determines that a tag ID provided by the data and tag source circuit corresponds to the first port.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Regarding claim 12,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit of claim 11,
wherein the first gating circuit is configured to block data from the data and tag source circuit to the first port when the tag ID provided by the data and tag source circuit corresponds to a second port of the plurality of ports that differs from the first port.
[FF 4508 will again load the match output from the comparator and set the match output of the FF to either the disable state (address mismatch) or enable state (address match). In response to a reset input on the CTL bus from controller 902, the FF 4508 match output will be set to the disable state mentioned in regard to FIG. 44. Also in response to the reset input the shift register may optionally be reset to a state that does not match the device address. (Whetsel et al., column 17, lines 25-30)]
Regarding claim 13,
Whetsel in view of Shah in further view of Rezeanu discloses The integrated circuit of claim 12,
wherein the second gating circuit is configured to pass the data from the data and tag source circuit to the second port when the second tag evaluation circuit determines that the tag ID provided by the data and tag source circuit corresponds to the second port.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Regarding claim 14,
Whetsel in view of Shah in further view of Rezeanu discloses the integrated circuit of claim 13,
wherein the second gating circuit is configured to block the data from the data and tag source circuit to the second port when the tag ID provided by the data and tag source circuit corresponds to the first port.
[FF 4508 will again load the match output from the comparator and set the match output of the FF to either the disable state (address mismatch) or enable state (address match). In response to a reset input on the CTL bus from controller 902, the FF 4508 match output will be set to the disable state mentioned in regard to FIG. 44. Also in response to the reset input the shift register may optionally be reset to a state that does not match the device address. (Whetsel et al., column 17, lines 25-30)]
Regarding claim 15,
Whetsel in view of Shah in further view of Rezeanu discloses The integrated circuit according to claim 10, further comprising
a programming circuit for the first configuration register and the second configuration register, the programming circuit configured to change content of the first configuration register and the second configuration register.
[The modification of the access port selector 606 can be achieved by simply adding additional serial register bits to the port select register 904 to provide the link control outputs 3008 as shown in FIG. 31. (Whetsel et al., column 14, lines 13-16)]
Regarding claim 16,
Whetsel in view of Shah in further view of Rezeanu discloses The integrated circuit according to claim 10,
wherein the plurality of tag evaluation circuits concurrently evaluate a tag identifier provided by the data and tag source circuit, and output a plurality of group identifiers to the first and second comparison circuits.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Regarding claim 17,
Whetsel in view of Shah in further view of Rezeanu discloses The integrated circuit according to claim 10,
wherein a tag evaluation circuit is configured to receive an identifier from an access request from a component and output a group identifier for the access request; wherein the first comparison circuit and the second comparison circuit are configured to compare the group identifier with content of the first configuration register and the second configuration register, respectively, and output release signals to the plurality of gating circuits to block or grant access to at least one of the ports depending on the release signals.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
[unique port grouping identifiers (ID) may be assigned individually to the port groupings. In this way, each port grouping may be referred to quickly and uniquely using the port grouping ID which is assigned thereto. (Shah et al., column 10, lines 65-67)]
Regarding claim 18,
Whetsel in view of Shah in further view of Rezeanu discloses The integrated circuit according to claim 17,
whereby a plurality of central processing units (CPUs) and/or virtual machines access one or more of the plurality of ports.
[If the device address shifted into the shift register matches the device address output from the device address circuit, the comparator outputs an enable state on the match output to FF 4508 that enables the operation of the port select register 4404 and removes the forced tri-state condition on the TDO output buffer 614 as mentioned in regard to FIG. 44. (Whetsel et al., column 17, lines 12-18)]
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hidaka et al. (US 7394717) discloses a plurality of port connection control circuits, arranged corresponding to said plurality of memory regions, each for selectively coupling a corresponding memory region to said plurality of buses, wherein said plurality of port connection control circuits include access control circuits, arranged corresponding to respective memory mats, each for connecting a corresponding memory mat to any of said plurality of buses, and each access control circuit selectively inhibits and allows write access to the corresponding memory mat according to at least an access attribute designating signal
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL ELAHIAN whose telephone number is (703) 756-1284. The examiner can normally be reached on Monday – Friday from 7:30am to 5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Thiaw can be reached at telephone number 571-270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.E./DANIEL ELAHIAN, Examiner, Art Unit 2407
/Catherine Thiaw/Supervisory Patent Examiner, Art Unit 2407 6/26/2026
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