DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the 35 U.S.C. 103 rejections (Remarks pp. 8-9) have been fully considered but are unpersuasive.
1. The Applicant argues that “Zeng does not disclose a hypervisor component that derives an eligibility determination from stored interrupt state, persists that determination in a hypervisor-maintained data structure, and later has a separate hypervisor component retrieve and use that stored determination to control routing. Rather, Zeng's routing decisions are made within the interrupt controller based on predefined classification values.”
The Examiner disagrees with the Applicant’s characterization of Zeng. Zeng suggests the teaching that the hypervisor maintains registers to store interrupt-associated information for determining how to handle the interrupt (
Zeng discloses, “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn),” ¶ 0048.).
However, the disclosure is not explicit. Therefore, the Examiner has introduced added reference Jiang (US 20230124004 A1) to explicitly teach the limitation, thus rendering the argument moot. Jiang teaches that the hypervisor maintains a register that contains status/state information that determines how an interrupt should be handled.
After the combination of Zeng in view of Allen, with Jiang, the hypervisor from Zeng in view of Allen now maintains a register for storing the interrupt as specified by Jiang. This register contains state information that determines whether an interrupt should be routed to the first processing path or the second processing path.
The claimed language also does not require that the retrieval and usage of the stored determination (state information) to control routing has to be done by a separate hypervisor component.
2. The Applicant argues that “Zeng's disclosure of prioritizing or ordering interrupts (e.g., fast versus normal interrupts) does not describe selecting between alternative hypervisor processing paths based on a stored, hypervisor- generated eligibility indicator. Instead, Zeng focuses on how interrupts are queued or routed, not on selectively bypassing portions of hypervisor processing based on previously computed state.”
The Examiner respectfully disagrees with this statement. Zeng does indeed teach selecting between alternative processing paths that allow for selectively bypassing portions of processing, based on previously computed state (
Zeng discloses, “To manage interrupts in such implementations, conventional systems may use a virtual machine monitor or hypervisor software to route secure interrupts to the appropriate virtual machine or processor,” ¶ 0024, “the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt,” ¶ 0038, and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The claimed “first processing path representing a first set of processing operations” is mapped to the path of interrupts before the first normal interrupt, e.g., interrupts in the linked list before the first normal interrupt.
The claimed “second processing path representing a second set of processing operations” is mapped to the path of interrupts before the first fast interrupt, e.g., interrupts in the linked list before the first fast interrupt. The reason why this is smaller is because fast interrupts are placed ahead of normal interrupts in the linked list, so it will take less operations for the fast interrupts to be routed compared to the normal interrupts.
The direct assignment identifier 206 (which contains state information) is used to determine the type of interrupt (fast or normal (slow)), and thus also determines which of the claimed “processing paths” it takes in the linked list.)
Claim Objections
Claim 1 is objected to because of the following minor informalities: regarding the limitation “state information corresponding to the interrupt and that is usable by the hypervisor to determine handling of the interrupt”, it is unclear what “that” refers to, although “that” most likely refers to the “state information.” For the purposes of art rejection, the Examiner is treating “that” as the “state information”. Appropriate correction is required.
Claims 10 and 20 are a computer-implemented method claim and a computer system claim, respectively, corresponding to the computing system Claim 1. Therefore, Claims 10 and 20 are objected to for the same reasons set forth in the objection of Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10-12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng (US 20150127866 A1) in view of Allen (US 9507621 B1) and Jiang (US 20230124004 A1).
Regarding Claim 1, Zeng teaches a computing system, comprising: a processor (
Zeng discloses, “The various aspects described above may also be implemented within a variety of mobile devices, such as a laptop computer 800 illustrated in FIG. 8… A laptop computer 800 will typically include a processor 811 coupled to volatile memory 812 and a large capacity nonvolatile memory, such as a disk drive 813 of Flash memory,” ¶ 0067.);
and a computer-readable storage medium having stored thereon computer-executable instructions representing a hypervisor, the hypervisor having a first processing path representing a first set of processing operations and a second processing path representing a second set of processing operations, the second set of processing operations being smaller than the first set of processing operations (
Zeng discloses, “To manage interrupts in such implementations, conventional systems may use a virtual machine monitor or hypervisor software to route secure interrupts to the appropriate virtual machine or processor,” ¶ 0024, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051, and “The operations of a method or algorithm disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. Non-transitory computer-readable or processor-readable storage media may be any storage media that may be accessed by a computer or a processor,” ¶ 0073.
The claimed “first processing path representing a first set of processing operations” is mapped to the path of interrupts before the first normal interrupt, e.g., interrupts in the linked list before the first normal interrupt.
The claimed “second processing path representing a second set of processing operations” is mapped to the path of interrupts before the first fast interrupt, e.g., interrupts in the linked list before the first fast interrupt. The reason why this is smaller is because fast interrupts are placed ahead of normal interrupts in the linked list, so it will take less operations for the fast interrupts to be routed compared to the normal interrupts.),
the computer-executable instructions being executable by the processor to cause the hypervisor to at least:
receive and process an interrupt from a hardware device prior to the interrupt reaching an operating system (
Zeng discloses, “In an aspect a virtual interrupt direct assignment method and apparatus can alleviate slowdowns in secure interrupt response time caused by an overhead associated with virtual machine monitor (VMM) or hypervisor software routing of secure interrupts to an appropriate virtual machine/processor,” ¶ 0025, and “The interrupt controller 104 may include an interrupt distributor 200, which may be configured to determine the type of interrupt received from an interrupt source 202, such as hardware or software of the mobile device,” ¶ 0033.), processing the interrupt including:
at an interrupt management processing system of the hypervisor, identifying, from a data structure corresponding to the interrupt (
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Zeng discloses, “Continuing with the example illustrated in FIG. 2, the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘10’ may indicate that the received interrupt is a physical interrupt. As another example, an interrupt direct assignment identifier value of ‘11’ may indicate that the received interrupt is an unrecognized signal,” ¶ 0038, and “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn). The ICH_LRn may store values for identifying the virtual interrupts (VirtualID), which are the same as the values identifying the corresponding physical interrupts, and values for identifying the type of interrupt (Grp),” ¶ 0048.
The claimed “data structure” is mapped to the disclosed two-bit data structure that determines whether the interrupts are virtual interrupts or physical interrupts (first digit), and fast virtual interrupts or normal (slow) interrupts (second digit).
The claimed “state information” is mapped to state of whether the interrupt is a virtual interrupt or not. This is further illustrated in the above FIG. 2.
As seen in the disclosures for paragraphs 45 and 48, the interrupt distributor that identifies state information is associated with the hypervisor.),
generating, based on the state information, a fast path eligibility indicator corresponding to the interrupt that indicates whether the interrupt needs the first processing path or the second processing path before being injected by the hypervisor into the operating system (
Zeng discloses, “routing the interrupt to the high level operating system guest virtual machine further includes routing the interrupt to a first interrupt interface dedicated for fast virtual interrupts when the interrupt is the fast interrupt, and routing the interrupt to a second interrupt interface dedicated for normal virtual interrupts when the interrupt is the normal interrupt,” ¶ 0005,
“the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt,” ¶ 0038,
“The direct assignment control register 300 may also store an interrupt controller hypervisor direct assignment disable status value (ICH_AssignDisableSatuts), which may indicate whether there is an available hardware register to accept an interrupt via the virtual interrupt direct assignment,” ¶ 0045,
and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The claimed “fast path eligibility indicator” is mapped to the second digit of the disclosed “interrupt direct assignment identifier value”, which determines whether the virtual interrupt is a fast interrupt, or a normal (slow) interrupt, and thus also indicates whether the virtual interrupt must be routed to the first processing path (path of interrupts before the first normal interrupt, e.g., interrupts in the linked list before the first normal interrupt) or the second processing path (path of interrupts before the first fast interrupt, e.g., interrupts in the linked list before the first fast interrupt), before being injected into the operating system (routing the interrupt to the high level operating system guest virtual machine). This is further illustrated in the above FIG. 2.),
and storing the state information and the fast path eligibility indicator in the data structure corresponding to the interrupt (
Zeng discloses, “the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt,” ¶ 0038, and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts,” ¶ 0051.);
and (
Zeng discloses, “In an aspect the apparatus may implement a virtual interrupt direct assignment upon receiving an interrupt by the interrupt distributor 200. The interrupt distributor 220 may check whether the HLOS Guest's interrupt controller hypervisor hardware running on a processor 102 (having a P_INDEX value) has any available associated list registers 308,” ¶ 0050.),
accessing the fast path eligibility indicator from the data structure corresponding to the interrupt (
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Zeng discloses, “The VMM software may repeatedly poll the ICH_AssignDisableSatuts of the direct assignment control register 300 for the processor 102 until its value changes to signify availability in the list register 308, such as by having a value of ‘1.’,” ¶ 0052. This is further illustrated in the above FIG. 5.),
and routing the interrupt through the first processing path or the second processing path based on the fast path eligibility indicator corresponding to the interrupt (
Zeng discloses, “An aspect method in which the priority of the interrupt comprises a fast interrupt and a normal interrupt, and in which routing the interrupt to the high level operating system guest virtual machine further includes routing the interrupt to a first interrupt interface dedicated for fast virtual interrupts when the interrupt is the fast interrupt, and routing the interrupt to a second interrupt interface dedicated for normal virtual interrupts when the interrupt is the normal interrupt,” ¶ 0005.).
Zeng does not teach receiving the interrupt from the hardware device at an assembly code processing system of the hypervisor, nor does it teach that the data structure is maintained by the hypervisor, or that the state information is usable by the hypervisor to determine handling of the interrupt.
However, Allen teaches receiving the interrupt from the hardware device at an assembly code processing system of the hypervisor (
Allen discloses, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. Accordingly, the one or more instructions may not access the data structure directly or modify the data structure without the access or modification being tracked or facilitated by the hypervisor. Access or modification of the data structure is instead performed by the hypervisor or associated entity. The one or more instructions may be configured or ‘patched’ with a hypercall or an indirect jump to the hypervisor. Further, an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
It can be seen that Allen’s hypervisor, that receives an assembly language-based interrupt, contains an assembly code processing system.).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen provide receiving the interrupt from the hardware device at an assembly code processing system of the hypervisor. Doing so would help provide increased performance from using assembly language, which would take less time than using a high-level language to perform the same task, and/or potentially have access to features unavailable for high-level languages.
Zeng in view of Allen does not teach that the data structure is maintained by the hypervisor, or that the state information is usable by the hypervisor to determine handling of the interrupt.
However, Jiang teaches that the data structure is maintained by the hypervisor, and that the state information is usable by the hypervisor to determine handling of the interrupt (
Jiang discloses, “Therefore, status information required for handling an interrupt may be stored in the ARM register 413, so that the ARM hypervisor 402 obtains, from the ARM register 413, the status information required for handling the interrupt and handles the interrupt.,” ¶ 0113.
Here, the hypervisor maintains an ARM register that contains status information required for handling an interrupt. This status information is required for determining handling of an interrupt.
After the combination of Zeng in view of Allen, with Jiang, the hypervisor from Zeng in view of Allen now maintains a register as specified by Jiang. The register contains status/state information that determines how the interrupt should be handled: whether an interrupt should be routed to the first processing path or the second processing path.).
Zeng in view of Allen, and Jiang are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng in view of Allen to incorporate the teachings of Jiang and provide that the data structure is maintained by the hypervisor, and that the state information is usable by the hypervisor to determine handling of the interrupt. Doing so would help provide a simpler and more efficient means for determining which processing path an interrupt should be routed to, and also improve data security by using the hypervisor to maintain and access the state information.
Regarding Claim 2, Zeng in view of Allen and Jiang teaches the computing system of claim 1, wherein the assembly code processing system performs the second set of processing operations in the second processing path and to inject the interrupt into the operating system, bypassing the first processing path, based on the fast path eligibility indicator corresponding to the interrupt (
Zeng discloses, “An aspect method in which the priority of the interrupt comprises a fast interrupt and a normal interrupt, and in which routing the interrupt to the high level operating system guest virtual machine further includes routing the interrupt to a first interrupt interface dedicated for fast virtual interrupts when the interrupt is the fast interrupt, and routing the interrupt to a second interrupt interface dedicated for normal virtual interrupts when the interrupt is the normal interrupt,” ¶ 0005, and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, … interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
This is “bypassing the first processing path” because fast interrupts are moved to the top/prioritized position ahead of normal interrupts, belonging to the first processing path, in a linked list.).
Regarding Claim 10, Zeng teaches a computer-implemented method, comprising: identifying, from a data structure corresponding to an interrupt (
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Zeng discloses, “Continuing with the example illustrated in FIG. 2, the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘10’ may indicate that the received interrupt is a physical interrupt. As another example, an interrupt direct assignment identifier value of ‘11’ may indicate that the received interrupt is an unrecognized signal,” ¶ 0038, and “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn). The ICH_LRn may store values for identifying the virtual interrupts (VirtualID), which are the same as the values identifying the corresponding physical interrupts, and values for identifying the type of interrupt (Grp),” ¶ 0048.
The claimed “data structure” is mapped to the disclosed two-bit data structure that determines whether the interrupts are virtual interrupts or physical interrupts (first digit), and fast virtual interrupts or normal (slow) interrupts (second digit).
The claimed “state information” is mapped to state of whether the interrupt is a virtual interrupt or not. This is further illustrated in the above FIG. 2.
As seen in the disclosures for paragraphs 45 and 48, the interrupt distributor that identifies state information is associated with the hypervisor.);
generating, based on the state information, a fast path eligibility indicator corresponding to the interrupt that indicates whether the interrupt needs a first processing path or a second processing path before being injected by the hypervisor into an operating system (
Zeng discloses, “routing the interrupt to the high level operating system guest virtual machine further includes routing the interrupt to a first interrupt interface dedicated for fast virtual interrupts when the interrupt is the fast interrupt, and routing the interrupt to a second interrupt interface dedicated for normal virtual interrupts when the interrupt is the normal interrupt,” ¶ 0005,
“the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt,” ¶ 0038,
“The direct assignment control register 300 may also store an interrupt controller hypervisor direct assignment disable status value (ICH_AssignDisableSatuts), which may indicate whether there is an available hardware register to accept an interrupt via the virtual interrupt direct assignment,” ¶ 0045,
and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The claimed “fast path eligibility indicator” is mapped to the second digit of the disclosed “interrupt direct assignment identifier value”, which determines whether the virtual interrupt is a fast interrupt, or a normal (slow) interrupt, and thus also indicates whether the virtual interrupt must be routed to the first processing path (path of interrupts before the first normal interrupt, e.g., interrupts in the linked list before the first normal interrupt) or the second processing path (path of interrupts before the first fast interrupt, e.g., interrupts in the linked list before the first fast interrupt), before being injected into the operating system (routing the interrupt to the high level operating system guest virtual machine). This is further illustrated in the above FIG. 2.);
storing the state information and the fast path eligibility indicator in the data structure corresponding to the interrupt (
Zeng discloses, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts,” ¶ 0051.);
receiving the interrupt, from a hardware device, (
Zeng discloses, “In an aspect the apparatus may implement a virtual interrupt direct assignment upon receiving an interrupt by the interrupt distributor 200. The interrupt distributor 220 may check whether the HLOS Guest's interrupt controller hypervisor hardware running on a processor 102 (having a P_INDEX value) has any available associated list registers 308,” ¶ 0050, and “To manage interrupts in such implementations, conventional systems may use a virtual machine monitor or hypervisor software to route secure interrupts to the appropriate virtual machine or processor,” ¶ 0024, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051, and “The operations of a method or algorithm disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. Non-transitory computer-readable or processor-readable storage media may be any storage media that may be accessed by a computer or a processor,” ¶ 0073.
The claimed “first processing path representing a first set of processing operations” is mapped to the path of interrupts before the first normal interrupt, e.g., interrupts in the linked list before the first normal interrupt.
The claimed “second processing path representing a second set of processing operations” is mapped to the path of interrupts before the first fast interrupt, e.g., interrupts in the linked list before the first fast interrupt. The reason why this is smaller is because fast interrupts are placed ahead of normal interrupts in the linked list, so it will take less operations for the fast interrupts to be routed compared to the normal interrupts.);
accessing, (
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Zeng discloses, “The VMM software may repeatedly poll the ICH_AssignDisableSatuts of the direct assignment control register 300 for the processor 102 until its value changes to signify availability in the list register 308, such as by having a value of ‘1.’,” ¶ 0052. This is further illustrated in the above FIG. 5.);
routing the interrupt, with the assembly code processing system, through the first processing path or the second processing path based on the fast path eligibility indicator corresponding to the interrupt (
Zeng discloses, “An aspect method in which the priority of the interrupt comprises a fast interrupt and a normal interrupt, and in which routing the interrupt to the high level operating system guest virtual machine further includes routing the interrupt to a first interrupt interface dedicated for fast virtual interrupts when the interrupt is the fast interrupt, and routing the interrupt to a second interrupt interface dedicated for normal virtual interrupts when the interrupt is the normal interrupt,” ¶ 0005.);
and injecting the interrupt into the operating system (
Zeng discloses, “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn),” ¶ 0048.).
Zeng does not teach using an assembly code processing system of the hypervisor to receive the interrupt or access the fast path eligibility indicator from the data structure corresponding to the interrupt, nor does it teach that the data structure is maintained by the hypervisor, or that the state information is usable by the hypervisor to determine handling of the interrupt.
However, Allen teaches using an assembly code processing system of the hypervisor to receive the interrupt or access the fast path eligibility indicator from the data structure corresponding to the interrupt (
Allen discloses, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. Accordingly, the one or more instructions may not access the data structure directly or modify the data structure without the access or modification being tracked or facilitated by the hypervisor. Access or modification of the data structure is instead performed by the hypervisor or associated entity. The one or more instructions may be configured or ‘patched’ with a hypercall or an indirect jump to the hypervisor. Further, an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
It can be seen that Allen’s hypervisor, that receives an assembly language-based interrupt, contains an assembly code processing system. After the combination of Zeng with Allen, the operations to receive the interrupt or access the fast path eligibility indicator from the data structure corresponding to the interrupt are done using the assembly code processing system from Allen.).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen and using an assembly code processing system of the hypervisor to receive the interrupt or access the fast path eligibility indicator from the data structure corresponding to the interrupt. Doing so would help provide increased performance from using assembly language to process the interrupt, which would take less time than using a high-level language to perform the same task.
Zeng in view of Allen does not teach that the data structure is maintained by the hypervisor, or that the state information is usable by the hypervisor to determine handling of the interrupt.
However, Jiang teaches that the data structure is maintained by the hypervisor, and that the state information is usable by the hypervisor to determine handling of the interrupt (
Jiang discloses, “Therefore, status information required for handling an interrupt may be stored in the ARM register 413, so that the ARM hypervisor 402 obtains, from the ARM register 413, the status information required for handling the interrupt and handles the interrupt.,” ¶ 0113.
Here, the hypervisor maintains an ARM register that contains status information required for handling an interrupt. This status information is required for determining handling of an interrupt.
After the combination of Zeng in view of Allen, with Jiang, the hypervisor from Zeng in view of Allen now maintains a register as specified by Jiang. The register contains status/state information that determines how the interrupt should be handled: whether an interrupt should be routed to the first processing path or the second processing path.).
Zeng in view of Allen, and Jiang are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng in view of Allen to incorporate the teachings of Jiang and provide that the data structure is maintained by the hypervisor, and that the state information is usable by the hypervisor to determine handling of the interrupt. Doing so would help provide a simpler and more efficient means for determining which processing path an interrupt should be routed to, and also improve data security by using the hypervisor to maintain and access the state information.
Regarding Claim 11, Zeng in view of Allen and Jiang teaches the computer-implemented method of claim 10, wherein routing the interrupt comprises: identifying the second processing path based on the fast path eligibility indicator corresponding to the interrupt (
Zeng discloses, “the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt,” ¶ 0038.);
and performing the second set of processing operations in the second processing path with the assembly code processing system, bypassing the first processing paths and wherein injecting the interrupt comprises injecting the interrupt into the operating system with the assembly code processing system (
Zeng discloses, “And, because the interrupt direct assignment identifier has the value of ‘00’ or ‘01’ the interrupt controller 104 knows that the interrupt is owned by the HLOS Guest 110 by virtue of being a virtual interrupt. Therefore, the interrupt controller 104 may bypass sending the interrupt to the VMM 114 to determine the owner of and route the interrupt,” ¶ 0039, and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051. Either the list register 308 can be designated for fast interrupts, or the fast interrupts can be moved to the head of the linked list, bypassing the normal (slow) interrupts that are part of the first processing path.
Allen teaches the interrupt could be injected by the assembly code processing system, as Allen states, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. … an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
After the combination of Zeng with Allen, the assembly code processing system from Allen is used to write the interrupt information into the linked list-based register from Zeng.).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen and provide wherein routing the interrupt comprises: identifying the second processing path based on the fast path eligibility indicator corresponding to the interrupt; and performing the second set of processing operations in the second processing path with the assembly code processing system, bypassing the first processing paths and wherein injecting the interrupt comprises injecting the interrupt into the operating system with the assembly code processing system. Doing so would help provide increased performance from using assembly language to process the interrupt, which would take less time than using a high-level language to perform the same task).
Regarding Claim 12, Zeng in view of Allen and Jiang teaches the computer-implemented method of claim 10, wherein routing the interrupt comprises: identifying the first processing path based on the fast path eligibility indicator corresponding to the interrupt (
Zeng discloses, “the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt,” ¶ 0038.);
and performing the first set of processing operations in the first processing path with the hypervisor system and wherein injecting the interrupt comprises injecting the interrupt into the operating system with the assembly code processing system (
Zeng discloses, “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn),” ¶ 0048.
Allen teaches the interrupt could be injected by the assembly code processing system, as Allen states, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. … an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
After the combination of Zeng with Allen, the assembly code processing system from Allen is used to write the interrupt information into the register from Zeng).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen and provide injecting the interrupt into the operating system with the assembly code processing system. Doing so would help provide increased performance from using assembly language to process the interrupt, which would take less time than using a high-level language to perform the same task.
Regarding Claim 20, Zeng teaches a computer system comprising: a processor (
Zeng discloses, “The various aspects described above may also be implemented within a variety of mobile devices, such as a laptop computer 800 illustrated in FIG. 8… A laptop computer 800 will typically include a processor 811 coupled to volatile memory 812 and a large capacity nonvolatile memory, such as a disk drive 813 of Flash memory,” ¶ 0067.);
and a computer-readable storage medium having stored thereon computer-executable instructions representing a hypervisor that includes an interrupt state processor, a fast path eligibility processor, (
Zeng discloses, “To manage interrupts in such implementations, conventional systems may use a virtual machine monitor or hypervisor software to route secure interrupts to the appropriate virtual machine or processor,” ¶ 0024, and “The operations of a method or algorithm disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. Non-transitory computer-readable or processor-readable storage media may be any storage media that may be accessed by a computer or a processor,” ¶ 0073.):
at the hypervisor, receive an interrupt from a hardware device (
Zeng discloses, “In an aspect a virtual interrupt direct assignment method and apparatus can alleviate slowdowns in secure interrupt response time caused by an overhead associated with virtual machine monitor (VMM) or hypervisor software routing of secure interrupts to an appropriate virtual machine/processor,” ¶ 0025, and “The interrupt controller 104 may include an interrupt distributor 200, which may be configured to determine the type of interrupt received from an interrupt source 202, such as hardware or software of the mobile device,” ¶ 0033.);
at the interrupt state processor, identify, from a data structure corresponding to the interrupt (
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Zeng discloses, “Continuing with the example illustrated in FIG. 2, the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘10’ may indicate that the received interrupt is a physical interrupt. As another example, an interrupt direct assignment identifier value of ‘11’ may indicate that the received interrupt is an unrecognized signal,” ¶ 0038, and “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn). The ICH_LRn may store values for identifying the virtual interrupts (VirtualID), which are the same as the values identifying the corresponding physical interrupts, and values for identifying the type of interrupt (Grp),” ¶ 0048.
The claimed “data structure” is mapped to the disclosed two-bit data structure that determines whether the interrupts are virtual interrupts or physical interrupts (first digit), and fast virtual interrupts or normal (slow) interrupts (second digit).
The claimed “state information” is mapped to state of whether the interrupt is a virtual interrupt or not. This is further illustrated in the above FIG. 2.
As seen in the disclosures for paragraphs 45 and 48, the interrupt distributor that identifies state information is associated with the hypervisor.);
at the fast path eligibility processor, generate, based on the state information, a fast path eligibility indicator corresponding to the interrupt that indicates whether the interrupt needs a first processing path or a second processing path before being injected by the hypervisor into an operating system (
Zeng discloses, “routing the interrupt to the high level operating system guest virtual machine further includes routing the interrupt to a first interrupt interface dedicated for fast virtual interrupts when the interrupt is the fast interrupt, and routing the interrupt to a second interrupt interface dedicated for normal virtual interrupts when the interrupt is the normal interrupt,” ¶ 0005,
“the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt,” ¶ 0038,
“The direct assignment control register 300 may also store an interrupt controller hypervisor direct assignment disable status value (ICH_AssignDisableSatuts), which may indicate whether there is an available hardware register to accept an interrupt via the virtual interrupt direct assignment,” ¶ 0045,
and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The claimed “fast path eligibility indicator” is mapped to the second digit of the disclosed “interrupt direct assignment identifier value”, which determines whether the virtual interrupt is a fast interrupt, or a normal (slow) interrupt, and thus also indicates whether the virtual interrupt must be routed to the first processing path (path of interrupts before the first normal interrupt, e.g., interrupts in the linked list before the first normal interrupt) or the second processing path (path of interrupts before the first fast interrupt, e.g., interrupts in the linked list before the first fast interrupt), before being injected into the operating system (routing the interrupt to the high level operating system guest virtual machine). This is further illustrated in the above FIG. 2.);
store the state information and the fast path eligibility indicator in the data structure corresponding to the interrupt (
Zeng discloses, “the interrupt distributor 200 may retrieve the interrupt direct assignment identifier 206 and use the value to determine the type of interrupt. For example, an interrupt direct assignment identifier value of ‘00’ may indicate that the received interrupt is a regular virtual interrupt. As another example, an interrupt direct assignment identifier value of ‘01’ may indicate that the received interrupt is a fast virtual interrupt,” ¶ 0038, and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts,” ¶ 0051.);
and (
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Zeng discloses, “The VMM software may repeatedly poll the ICH_AssignDisableSatuts of the direct assignment control register 300 for the processor 102 until its value changes to signify availability in the list register 308, such as by having a value of ‘1.’,” ¶ 0052. This is further illustrated in the above FIG. 5.), and either:
route the interrupt to a first set of processing components of the first processing path based on the fast path eligibility indicator, the first set of processing components performing a first set of processing operations on the interrupt prior to the interrupt being injected into the operating system (
Zeng discloses, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The claimed “first set of processing components performing a first set of processing operations on the interrupt” is mapped to the set of components that process and route each of the fast interrupts in the linked list into the operating system, before it is the first normal interrupt’s turn to be processed and routed to the operating system.),
or route the interrupt to a second set of processing components of the second processing path based on the fast path eligibility indicator, the second set of processing components performing a second set of processing operations on the interrupt prior to the interrupt being injected into the operating system, the second set of processing components being a subset of the first set of processing components (
Zeng discloses, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The claimed “second set of processing components performing a second set of processing operations on the interrupt” is mapped to the set of components that process and route each of the normal interrupts in the linked list into the operating system, before it is the first fast interrupt’s turn to be processed and routed to the operating system. The reason why this is a subset of the first set of processing components is that fast interrupts are given priority over normal interrupts, and thus will reach the head of the linked list sooner than normal interrupts.).
Zeng does not teach an assembly code processing system, nor does it teach access the fast path eligibility indicator from the data structure corresponding to the interrupt using the assembly code processing system, nor does it teach that the data structure is maintained by the hypervisor, or that the state information is usable by the hypervisor to determine handling of the interrupt.
However, Allen teaches an assembly code processing system, and accessing the fast path eligibility indicator from the data structure corresponding to the interrupt using the assembly code processing system (
Allen discloses, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. Accordingly, the one or more instructions may not access the data structure directly or modify the data structure without the access or modification being tracked or facilitated by the hypervisor. Access or modification of the data structure is instead performed by the hypervisor or associated entity. The one or more instructions may be configured or ‘patched’ with a hypercall or an indirect jump to the hypervisor. Further, an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
It can be seen that Allen’s hypervisor, that receives an assembly language-based interrupt, contains an assembly code processing system.).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen and provide an assembly code processing system, and accessing the fast path eligibility indicator from the data structure corresponding to the interrupt using the assembly code processing system. Doing so would help provide increased performance from using assembly language, which would take less time than using a high-level language to perform the same task, and/or potentially have access to features unavailable for high-level languages.
Zeng in view of Allen does not teach that the data structure is maintained by the hypervisor, or that the state information is usable by the hypervisor to determine handling of the interrupt.
However, Jiang teaches that the data structure is maintained by the hypervisor, and that the state information is usable by the hypervisor to determine handling of the interrupt (
Jiang discloses, “Therefore, status information required for handling an interrupt may be stored in the ARM register 413, so that the ARM hypervisor 402 obtains, from the ARM register 413, the status information required for handling the interrupt and handles the interrupt.,” ¶ 0113.
Here, the hypervisor maintains an ARM register that contains status information required for handling an interrupt. This status information is required for determining handling of an interrupt.
After the combination of Zeng in view of Allen, with Jiang, the hypervisor from Zeng in view of Allen now maintains a register as specified by Jiang. The register contains status/state information that determines how the interrupt should be handled: whether an interrupt should be routed to the first processing path or the second processing path.).
Zeng in view of Allen, and Jiang are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng in view of Allen to incorporate the teachings of Jiang and provide that the data structure is maintained by the hypervisor, and that the state information is usable by the hypervisor to determine handling of the interrupt. Doing so would help provide a simpler and more efficient means for determining which processing path an interrupt should be routed to, and also improve data security by using the hypervisor to maintain and access the state information.
Claims 3-7, and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng (US 20150127866 A1) in view of Allen (US 9507621 B1), Jiang (US 20230124004 A1), and Singh (US 20240184556 A1).
Regarding Claim 3, Zeng in view of Allen and Jiang teaches the computing system of claim 2. Zeng in view of Allen and Jiang does not teach wherein the first processing path comprises a language translation system that: receives an assembly language representation of the interrupt from the assembly code processing system, and performs one of the first set of processing operations by generating a higher-level language representation of the interrupt in a language that is a higher-level language than assembly language.
However, Singh teaches wherein the first processing path comprises a language translation system that: receives an assembly language representation of the interrupt from the assembly code processing system, and performs one of the first set of processing operations by generating a higher-level language representation of the interrupt in a language that is a higher-level language than assembly language (
Singh discloses, “receiving first source code in assembly language …; for each of the plurality of code blocks: for each of the plurality of lines of assembly code in the code block, processing the line of assembly code using a first machine learning model to generate a natural language description of the line of assembly code; and processing the code block and the natural language descriptions of the plurality of lines of assembly code in the code block using a second machine learning model to generate a natural language description of the code block; and processing the natural language descriptions of the plurality of code blocks using a third machine learning model to generate a natural language description of the first source code,” ¶ 0008, and “the method further includes automatically generating second source code in a high-level programming language based on the natural language descriptions of the plurality of lines of assembly code in each of the plurality of code blocks, the natural language descriptions of the plurality of code blocks, and the natural language description of the first source code,” ¶ 0009.).
Zeng in view of Allen and Jiang, and Singh are both considered to be analogous to the claimed invention because they are in the same field of computer processors/assembly code. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng in view of Allen and Jiang to incorporate the teachings of Singh and provide wherein the first processing path comprises a language translation system that: receives an assembly language representation of the interrupt from the assembly code processing system, and performs one of the first set of processing operations by generating a higher-level language representation of the interrupt in a language that is a higher-level language than assembly language. Doing so would help eliminate the need to manually translate the assembly code into a higher-level language (Singh discloses, “Accordingly, some or all source code of an application that is written in a lower-level programming language (e.g., assembly) can be translated from the lower-level programming language to a higher-level programming language, without requiring any human intervention,” ¶ 0005.). Doing so would also allow for better interfacing between the assembly code and high-level language code.
Regarding Claim 4, Zeng in view of Allen, Jiang, and Singh teaches the computing system of claim 3, wherein the first processing path comprises a management processing system that performs one of the first set of processing operations by performing a virtual processor management operation based on receiving the interrupt (
Zeng discloses, “In an aspect the apparatus may implement a virtual interrupt direct assignment upon receiving an interrupt by the interrupt distributor 200. The interrupt distributor 220 may check whether the HLOS Guest's interrupt controller hypervisor hardware running on a processor 102 (having a P_INDEX value) has any available associated list registers 308. When there is availability in the list register 308 associated with the processor 102 and the HLOS Guest, the interrupt distributor 200 may check the direct assignment identifier register 302 for the ICD_ASSIGNn value associated with the received interrupt. When the ICD_ASSIGNn value indicates that the interrupt is owned by the HLOS Guest, the interrupt distributor 200 may set the VirtualID value identifying the virtual interrupt to the ICH_LRn at the available spot in the list register 308. When the ICD_ASSIGNn value signifies a normal virtual interrupt, the Grp value ‘1’ may be set to the ICH_LRn to signify the normal virtual interrupt,” ¶ 0050.
The claimed “virtual processor management operation” is mapped to the disclosed direct assignment of a virtual interrupt to a list register.).
Regarding Claim 5, Zeng in view of Allen, Jiang, and Singh teaches the computing system of claim 4, further comprising a plurality of injection registers (
Zeng discloses, “Further, the interrupt controller 104 may include one or more direct assignment control registers 300, direct assignment identifier registers 302, control interfaces 304, processor interfaces 306, and list registers 308,” ¶ 0044.
The claimed “injection registers” is mapped to the disclosed “list registers 308” where the interrupts are assigned.),
wherein the assembly code processing system injects the interrupt into the operating system by writing interrupt information indicative of the interrupt into an allocated injection register that is allocated to the interrupt (
Zeng discloses, “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn),” ¶ 0048.
Allen teaches the interrupt could be injected by the assembly code processing system, as Allen states, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. … an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
After the combination of Zeng with Allen, the assembly code processing system from Allen is used to write the interrupt information into the register from Zeng.).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen provide using the assembly code processing system to inject the interrupt into the operating system. Doing so would help provide increased performance from using assembly language to process the interrupt, which would take less time than using a high-level language to perform the same task, and/or potentially have access to features unavailable for high-level languages.
Regarding Claim 6, Zeng in view of Allen, Jiang, and Singh teaches the computing system of claim 5, wherein the first processing path comprises the interrupt management processing system that performs one of the first set of processing operations by allocating the interrupt to one of the plurality of injection registers (
Zeng discloses, “In an aspect the apparatus may implement a virtual interrupt direct assignment upon receiving an interrupt by the interrupt distributor 200. The interrupt distributor 220 may check whether the HLOS Guest's interrupt controller hypervisor hardware running on a processor 102 (having a P_INDEX value) has any available associated list registers 308. When there is availability in the list register 308 associated with the processor 102 and the HLOS Guest, the interrupt distributor 200 may check the direct assignment identifier register 302 for the ICD_ASSIGNn value associated with the received interrupt. When the ICD_ASSIGNn value indicates that the interrupt is owned by the HLOS Guest, the interrupt distributor 200 may set the VirtualID value identifying the virtual interrupt to the ICH_LRn at the available spot in the list register 308. When the ICD_ASSIGNn value signifies a normal virtual interrupt, the Grp value ‘1’ may be set to the ICH_LRn to signify the normal virtual interrupt,” ¶ 0050.
The claimed “allocation of the interrupt to one of the plurality of injection registers” is mapped to the disclosed setting of the VirtualID value identifying the virtual interrupt to the ICH_LRn at an available spot in the list register 308, before the interrupt is actually stored there.).
Regarding Claim 7, Zeng in view of Allen, Jiang, and Singh teaches the computing system of claim 6, wherein the assembly code processing system determines that the interrupt is already allocated to an injection register (
Zeng discloses, “And, because the interrupt direct assignment identifier has the value of ‘00’ or ‘01’ the interrupt controller 104 knows that the interrupt is owned by the HLOS Guest 110 by virtue of being a virtual interrupt. Therefore, the interrupt controller 104 may bypass sending the interrupt to the VMM 114 to determine the owner of and route the interrupt,” ¶ 0039.);
and injects the interrupt directly into the operating system, bypassing the first processing path, by writing the interrupt into the injection register to which the interrupt is already allocated (
Zeng discloses, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051. Either the list register 308 can be designated for fast interrupts, or the fast interrupts can be moved to the head of the linked list, bypassing the normal (slow) interrupts that are part of the first processing path.
Allen teaches the interrupt could be injected by the assembly code processing system, as Allen states, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. … an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
After the combination of Zeng with Allen, the assembly code processing system from Allen is used to write the interrupt information into the linked list-based register from Zeng.).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen and provide wherein the assembly code processing system determines that the interrupt is already allocated to an injection register; and injects the interrupt directly into the operating system, bypassing the first processing path, by writing the interrupt into the injection register to which the interrupt is already allocated. Doing so would help provide increased performance from using assembly language to process the interrupt, which would take less time than using a high-level language to perform the same task.
Regarding Claim 13, Zeng in view of Allen and Jiang teaches the computer-implemented method of claim 12. Zeng in view of Allen and Jiang does not teach wherein performing the first set of processing operations comprises: receiving an assembly language representation of the interrupt from the assembly code processing system; and performing one or more of the first set of processing operations by generating a higher-level language representation of the interrupt in a language that is a higher-level language than assembly language.
However, Singh teaches wherein performing the first set of processing operations comprises: receiving an assembly language representation of the interrupt from the assembly code processing system; and performing one or more of the first set of processing operations by generating a higher-level language representation of the interrupt in a language that is a higher-level language than assembly language (
Singh discloses, “receiving first source code in assembly language …; for each of the plurality of code blocks: for each of the plurality of lines of assembly code in the code block, processing the line of assembly code using a first machine learning model to generate a natural language description of the line of assembly code; and processing the code block and the natural language descriptions of the plurality of lines of assembly code in the code block using a second machine learning model to generate a natural language description of the code block; and processing the natural language descriptions of the plurality of code blocks using a third machine learning model to generate a natural language description of the first source code.,” ¶ 0008, and “the method further includes automatically generating second source code in a high-level programming language based on the natural language descriptions of the plurality of lines of assembly code in each of the plurality of code blocks, the natural language descriptions of the plurality of code blocks, and the natural language description of the first source code,” ¶ 0009.).
Zeng in view of Allen and Jiang, and Singh are both considered to be analogous to the claimed invention because they are in the same field of computer processors/assembly code. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng in view of Allen and Jiang to incorporate the teachings of Singh and provide wherein performing the first set of processing operations comprises: receiving an assembly language representation of the interrupt from the assembly code processing system; and performing one or more of the first set of processing operations by generating a higher-level language representation of the interrupt in a language that is a higher-level language than assembly language. Doing so would help eliminate the need to manually translate the assembly code into a higher-level language (Singh discloses, “Accordingly, some or all source code of an application that is written in a lower-level programming language (e.g., assembly) can be translated from the lower-level programming language to a higher-level programming language, without requiring any human intervention,” ¶ 0005.). Doing so would also allow for better interfacing between the assembly code and high-level language code.
Regarding Claim 14, Zeng in view of Allen, Jiang, and Singh teaches the computer-implemented method of claim 13, wherein performing the first set of processing operations comprises: performing one or more of the first set of processing operations by performing a virtual processor management operation based on receiving the interrupt (
Zeng discloses, “In an aspect the apparatus may implement a virtual interrupt direct assignment upon receiving an interrupt by the interrupt distributor 200. The interrupt distributor 220 may check whether the HLOS Guest's interrupt controller hypervisor hardware running on a processor 102 (having a P_INDEX value) has any available associated list registers 308. When there is availability in the list register 308 associated with the processor 102 and the HLOS Guest, the interrupt distributor 200 may check the direct assignment identifier register 302 for the ICD_ASSIGNn value associated with the received interrupt. When the ICD_ASSIGNn value indicates that the interrupt is owned by the HLOS Guest, the interrupt distributor 200 may set the VirtualID value identifying the virtual interrupt to the ICH_LRn at the available spot in the list register 308. When the ICD_ASSIGNn value signifies a normal virtual interrupt, the Grp value ‘1’ may be set to the ICH_LRn to signify the normal virtual interrupt,” ¶ 0050.
The claimed “virtual processor management operation” is mapped to the disclosed direct assignment of a virtual interrupt to a list register.).
Regarding Claim 15, Zeng in view of Allen, Jiang, and Singh teaches the computer-implemented method of claim 14, wherein injecting the interrupt comprises: writing, with the assembly code processing system, interrupt information indicative of the interrupt into an allocated injection register, of a plurality of injection registers, that is allocated to the interrupt (
Zeng discloses, “Further, the interrupt controller 104 may include one or more direct assignment control registers 300, direct assignment identifier registers 302, control interfaces 304, processor interfaces 306, and list registers 308,” ¶ 0044.
The claimed “injection registers” is mapped to the disclosed “list registers 308” where the interrupts are assigned.
Zeng also discloses, “The interrupt controller 104 may also include interrupt lists in the form of the list registers 308 which, when they have an open spot, accept the virtual normal and fast interrupts assigned to the HLOS Guest by the interrupt distributor 200 and routed by the from the interrupt distributor interface 310. The list registers 308 may store the interrupt numbers in interrupt controller hypervisor list register structures (ICH_LRn),” ¶ 0048.
Allen teaches the interrupt could be injected by the assembly code processing system, as Allen states, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. … an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
After the combination of Zeng with Allen, the assembly code processing system from Allen is used to write the interrupt information into the register from Zeng).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen provide using the assembly code processing system to write the interrupt information into the operating system. Doing so would help provide increased performance from using assembly language to process the interrupt, which would take less time than using a high-level language to perform the same task, and/or potentially have access to features unavailable for high-level languages.
Regarding Claim 16, Zeng in view of Allen, Jiang, and Singh teaches the computer-implemented method of claim 15, wherein performing the first set of processing operations comprises: allocating the interrupt to one of the plurality of injection registers (
Zeng discloses, “In an aspect the apparatus may implement a virtual interrupt direct assignment upon receiving an interrupt by the interrupt distributor 200. The interrupt distributor 220 may check whether the HLOS Guest's interrupt controller hypervisor hardware running on a processor 102 (having a P_INDEX value) has any available associated list registers 308. When there is availability in the list register 308 associated with the processor 102 and the HLOS Guest, the interrupt distributor 200 may check the direct assignment identifier register 302 for the ICD_ASSIGNn value associated with the received interrupt. When the ICD_ASSIGNn value indicates that the interrupt is owned by the HLOS Guest, the interrupt distributor 200 may set the VirtualID value identifying the virtual interrupt to the ICH_LRn at the available spot in the list register 308. When the ICD_ASSIGNn value signifies a normal virtual interrupt, the Grp value ‘1’ may be set to the ICH_LRn to signify the normal virtual interrupt,” ¶ 0050.
The claimed “allocation of the interrupt to one of the plurality of injection registers” is mapped to the disclosed setting of the VirtualID value identifying the virtual interrupt to the ICH_LRn at an available spot in the list register 308, before the interrupt is actually stored there.).
Regarding Claim 17, Zeng in view of Allen, Jiang, and Singh teaches the computer-implemented method of claim 16, wherein injecting the interrupt comprises: determining that the interrupt is already allocated to an injection register (
Zeng discloses, “And, because the interrupt direct assignment identifier has the value of ‘00’ or ‘01’ the interrupt controller 104 knows that the interrupt is owned by the HLOS Guest 110 by virtue of being a virtual interrupt. Therefore, the interrupt controller 104 may bypass sending the interrupt to the VMM 114 to determine the owner of and route the interrupt,” ¶ 0039.);
and injecting the interrupt directly into the operating system, bypassing the first processing path, by writing the interrupt into the injection register to which the interrupt is already allocated (
Zeng discloses, “And, because the interrupt direct assignment identifier has the value of ‘00’ or ‘01’ the interrupt controller 104 knows that the interrupt is owned by the HLOS Guest 110 by virtue of being a virtual interrupt. Therefore, the interrupt controller 104 may bypass sending the interrupt to the VMM 114 to determine the owner of and route the interrupt,” ¶ 0039, and “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051. Either the list register 308 can be designated for fast interrupts, or the fast interrupts can be moved to the head of the linked list, bypassing the normal (slow) interrupts that are part of the first processing path.
Allen teaches the interrupt could be injected by the assembly code processing system, as Allen states, “The hypervisor modifies 504 the one or more instructions to cause data structure access to be performed by the hypervisor or associated entity. … an assembly language-based execution trap, exception, fault, abort or interrupt may be used to modify the one or more instructions and cause access to the data structure to be performed by the hypervisor upon calling the one or more instructions,” Col 10, Lines 1-14.
After the combination of Zeng with Allen, the assembly code processing system from Allen is used to write the interrupt information into the linked list-based register from Zeng.).
Zeng and Allen are both considered to be analogous to the claimed invention because they are in the same field of computer processors. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng to incorporate the teachings of Allen and provide wherein injecting the interrupt comprises: determining that the interrupt is already allocated to an injection register; and injecting the interrupt directly into the operating system, bypassing the first processing path, by writing the interrupt into the injection register to which the interrupt is already allocated. Doing so would help provide increased performance from using assembly language to process the interrupt, which would take less time than using a high-level language to perform the same task
Regarding Claim 18, Zeng in view of Allen, Jiang, and Singh teaches the computer-implemented method of claim 17, wherein one of the plurality of injection registers is allocated as a fast path injection register that receives the interrupt after being routed through the second processing path (
Zeng discloses, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The fast path injection register, in this case, is at the beginning of the linked list register 308 that is given priority over all other positions in the linked list.)
and all remaining injection registers of the plurality of injection registers comprise slow path injection registers that receive the interrupt after being processed by the first processing path (
Zeng discloses, “Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The slow path injection registers, in this case, are at the subsequent positions of the linked list register 308 that are given less priority than the beginning of the linked list that contains the fast path register.).
Regarding Claim 19, Zeng in view of Allen, Jiang, and Singh teaches the computer-implemented method of claim 18, wherein routing the interrupt comprises: determining that all the slow path injection registers are in use; and routing the interrupt to the first processing path (
Zeng discloses, “When there is no availability in the list register 308 associated with the processor 102 for receiving the interrupt, the control interface 304 may connect the VMM software and the direct assignment control register 300. Through the control interface 304, the VMM software may disable the ability to bypass the VMM by writing a value, such as ‘0’, to the ICH_AssignControl of the direct assignment control register 300 for the processor 102. The VMM software may repeatedly poll the ICH_AssignDisableSatuts of the direct assignment control register 300 for the processor 102 until its value changes to signify availability in the list register 308, such as by having a value of ‘1.’ While the direct assignment control register 300 remains disabled, the VMM software may process the interrupts and assign them by common convention,” ¶ 0052.
Here, when the registers in the list register 308 are in use, the interrupt in question is still processed and assigned/routed.).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng (US 20150127866 A1) in view of Allen (US 9507621 B1), Jiang (US 20230124004 A1), Singh (US 20240184556 A1), and Aggarwal (US 20190108106 A1).
Regarding Claim 8, Zeng in view of Allen, Jiang, and Singh and teaches the computing system of claim 7, wherein one of the plurality of injection registers is allocated as a fast path injection register (
Zeng discloses, “In an aspect, a fast virtual interrupt may have priority over a normal virtual interrupt. When a fast virtual interrupt is identified, it may be assigned to a list register 308 designated for fast virtual interrupts. Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The fast path injection register, in this case, is at the beginning of the linked list register 308 that is given priority over all other positions in the linked list.)
and all remaining injection registers of the plurality of injection registers comprise slow path injection registers that can be allocated by the interrupt management processing system (
Zeng discloses, “Alternatively, interrupts already listed in the list register 308 may be shifted to allow for the fast virtual interrupt to be within the structure of the list register 308, for example a linked list, such that the fast virtual interrupt may be processed sooner than the normal virtual interrupts in the list register 308,” ¶ 0051.
The slow path injection registers, in this case, are at the subsequent positions of the linked list register 308 that are given less priority than the beginning of the linked list that contains the fast path register.).
Zeng in view of Allen, Jiang, and Singh does not teach that the fast path injection register is not allocated by the interrupt management processing system.
However, Aggarwal teaches that the fast path injection register is not allocated by the interrupt management processing system (
Aggarwal discloses, “Fast path accesses 426 by guest driver 424 are issued directly to ADIs 432, 434 behind VDEV 404, while slow path accesses 420 are intercepted and virtualized by VM resource manager (VMRM) 416 and VDCM 402,” ¶ 0054.
This means that a fast path injection register is not required to be allocated by an interrupt management processing system.).
Zeng in view of Allen, Jiang, and Singh, and Aggarwal are both considered to be analogous to the claimed invention because they are in the same field of computer virtualization. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zeng in view of Allen, Jiang, and Singh to incorporate the teachings of Aggarwal and provide that the fast path injection register is not allocated by the interrupt management processing system. Doing so would help allow for directly writing to the fast path injection registers without requiring allocation, and/or allow for faster processing of the fast virtual interrupts (Aggarwal discloses, “Fast path accesses 426 by guest driver 424 are issued directly to ADIs 432, 434 behind VDEV 404, while slow path accesses 420 are intercepted and virtualized by VM resource manager (VMRM) 416 and VDCM 402,” ¶ 0054.).
Regarding Claim 9, Zeng in view of Allen, Jiang, Singh, and Aggarwal teaches the computing system of claim 8, wherein the assembly code processing system determines that all of the slow path injection registers are in use, and routes the interrupt to the first processing path (
Zeng discloses, “When there is no availability in the list register 308 associated with the processor 102 for receiving the interrupt, the control interface 304 may connect the VMM software and the direct assignment control register 300. Through the control interface 304, the VMM software may disable the ability to bypass the VMM by writing a value, such as ‘0’, to the ICH_AssignControl of the direct assignment control register 300 for the processor 102. The VMM software may repeatedly poll the ICH_AssignDisableSatuts of the direct assignment control register 300 for the processor 102 until its value changes to signify availability in the list register 308, such as by having a value of ‘1.’ While the direct assignment control register 300 remains disabled, the VMM software may process the interrupts and assign them by common convention,” ¶ 0052.
Here, when the registers in the list register 308 are in use, the interrupt in question is still processed and assigned/routed.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Arroyo et al. (US 20210034390 A1): Dynamic Assignment of Interrupts based on Input/Output Metrics
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW NMN SUN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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