Prosecution Insights
Last updated: October 27, 2026
Application No. 18/345,127

TECHNOLOGIES FOR BARRIER LAYERS IN PEROVSKITE TRANSISTORS

Non-Final OA
Filed
Jun 30, 2023
Examiner
YUSHINA, GALINA G
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
886 granted / 1111 resolved
+11.7% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
32 currently pending
Career history
1133
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
13.5%
-26.5% vs TC avg
§112
36.4%
-3.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1111 resolved cases

Prosecution Timeline

Jun 30, 2023
Application Filed
Nov 15, 2023
Response after Non-Final Action
Oct 21, 2026
Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772828
SELF-ALIGNED ZERO TRACK SKIP
4y 0m to grant Granted Oct 20, 2026
Patent 12764949
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME
3y 3m to grant Granted Oct 13, 2026
Patent 12764980
SEMICONDUCTOR DEVICE HAVING A LOW RESISTIVITY TRENCH CAPACITOR
2y 10m to grant Granted Oct 13, 2026
Patent 12765190
Display Device
2y 10m to grant Granted Oct 13, 2026
Patent 12757788
DISPLAY PANEL AND DISPLAY DEVICE
3y 6m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+16.3%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1111 resolved cases by this examiner. Grant probability derived from career allowance rate.

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