DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Harriman et al. (Pub. No. US20200226091)
As per claim 1, Harriman discloses an apparatus comprising:
protocol circuitry (paragraph 56, line 11, protocol circuitry (e.g., of ports 520, 525)) to implement an input/output (I/O) interconnect protocol(fig.2, Layered protocol stack 200), wherein the I/O interconnect protocol comprises a flit mode and a non-flit mode (paragraph 53, lines 4-5, a flit mode when high-speed PAM4 encoding is utilized and another (e.g., non-flit) mode)), wherein a set of flit mode header formats are used when in the flit mode (paragraph 53, each flit may include a respective header with information corresponding to the flit and packet) and a set of non-flit mode header formats are used when in the non-flit mode, and the set of non-flit mode header formats comprise one or more non-flit mode fields (paragraph 53, lines 16, second packet header format is utilized for a mode that does not utilize flits); and
interface circuitry to implement an interface to couple to a fabric, wherein the interface circuitry is to: determine that a link is trained to the non-flit mode (paragraph 24, lines 1-2, a fabric composed of point-to-point Links that interconnect a set of components);
generate a header according to the set of flit mode header formats, wherein the header comprises a field to indicate that a corresponding packet originated as a non-flit mode packet (paragraph 54, headers corresponding packet header fields), and one or more fields of the set of flit mode header formats are repurposed in the header to carry the one or more non-flit mode fields(paragraph 54, lines 6-8, a flit-mode TLP header may replace the traditional, orthogonal, Format (Fmt) and Type fields to a fully-decoded 8-bit TLP Type field which may be encoded with values to indicate all (or considerably all) existing TLP Types in PCIe, while adding new TLP types for no-op (NOP) and End Bad (EDB) packets types.); and
send the header over the interface (paragraph 24, lines 1-2, a fabric composed of point-to-point Links that interconnect a set of components).
As per claim 2, Harriman discloses wherein the one or more non-flit mode fields are not included in the set of flit mode header formats (paragraph 53, each flit may include a respective header with information corresponding to the flit and packet).
As per claim 3, Harriman discloses wherein the I/O interconnect protocol comprises a load/store interconnection protocol (paragraph 94, re-order buffers in reorder/retirement unit 1535, ILTB 1520, load/store buffers, and queues may be shared through partitioning).
As per claim 4, Harriman discloses wherein the I/O interconnect protocol comprises one of a Peripheral Component Interconnect Express (PCIe)-based protocol or a Compute Express Link (CXL)-based protocol (paragraph 53, lines 3-5, a link and corresponding protocol may be configured to operate in multiple modes, such as a flit mode when high-speed PAM4 encoding is utilized and another (e.g., non-flit) mode, two (or more) separate packet header formats may be defined for an interconnect (e.g., for PCIe 6.0-based interconnects))
As per claim 6, Harriman discloses wherein the flit mode and the non-flit mode are based on a PCIe-based protocol. (paragraph 53, lines 3-5, a link and corresponding protocol may be configured to operate in multiple modes, such as a flit mode when high-speed PAM4 encoding is utilized and another (e.g., non-flit) mode, two (or more) separate packet header formats may be defined for an interconnect (e.g., for PCIe 6.0-based interconnects))
As per claim 7, Harriman discloses wherein the one or more non-flit mode fields are carried in the one or more fields of the set of flit mode header formats based on a mapping. (paragraph 53, lines 3-5, a link and corresponding protocol may be configured to operate in multiple modes, such as a flit mode when high-speed PAM4 encoding is utilized and another (e.g., non-flit) mode, two (or more) separate packet header formats may be defined for an interconnect (e.g., for PCIe 6.0-based interconnects))
As per claim 8, Harriman discloses wherein the set of flit mode header formats comprise one or more orthogonal content headers and a particular field in a particular one of the one or more orthogonal content headers is to carry a particular field in the one or more non-flit mode fields (paragraph 54, lines 7-10, a flit-mode TLP header may replace the traditional, orthogonal, Format (Fmt) and Type fields to a fully-decoded 8-bit TLP Type field, which may be encoded with values to indicate all (or considerably all) existing TLP Types in PCIe)
As per claim 9, Harriman discloses wherein the set of flit mode header formats comprise one or more prefixes and a particular field in a particular one of the one or more prefixes is to carry a particular field in the one or more non-flit mode fields (paragraph 54, lines 7-10, a flit-mode TLP header may replace the traditional, orthogonal, Format (Fmt) and Type fields to a fully-decoded 8-bit TLP Type field, which may be encoded with values to indicate all (or considerably all) existing TLP Types in PCIe.)
As per claim 10, Harriman discloses wherein the particular prefix comprises a mode field to indicate that the corresponding packet originated as a non-flit mode packet (paragraph 61, lines 1-4, a flit-mode packet may be defined to include zero or more 1DW of local TLP prefixes, a TLP header base (e.g., 3DW or 4DW based on the packet type), a TLP data payload).
As per claim 11, Harriman discloses wherein end-to-end encryption is to be provided on the link based on the flit mode (paragraph 61, end-to-end suffixes).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Harriman et al. (Pub. No. US20200226091) in view of Choudhary et al. (Pub. No. US20200327088)
As per claim 5, Harriman discloses all the limitations as the above but does not explicitly discloses wherein the interface comprises: a header channel (fig.3, channel identifier field 306) implemented on a first subset of a plurality of physical lanes (paragraph 50, lines 7-9, a link or PHY layer may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider), wherein the first subset of lanes comprises first lanes to carry packet headers based on the interconnect protocol (paragraph 53, lines 3-5, a link and corresponding protocol may be configured to operate in multiple modes)and second lanes to carry metadata for the packet headers (paragraph 23, lines 7-9, subdivides the transmission of a single packet into a set of one or more defined flow control units, or “flits,” at the data link or logical PHY layer); and
Harriman discloses all the limitations as the above but does not explicitly disclose a data channel implemented on a separate second subset of the plurality of physical lanes, wherein the second subset of lanes comprises third lanes to carry a packet payloads and fourth lanes to carry metadata for the packet payloads, wherein the header is sent over the header channel. However, Choudhary discloses this (paragraph 31, lines 16-20, an improved streaming interface may bifurcate the header and data of packets into independent physical channels (e.g., a header channel and a data channel) to thereby allow the receiver to start processing the headers while data is still streaming in and thereby helps reduce overall latency and buffer sizing and complexity.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Choudhary with the teaching of Lim so as to allow on the receiving side to enhance the timing when header data is received in relation to the reception of the payload data. That enhanced timing may serve for a more efficient data reception processing reducing the overall latency so as to control efficiently, thus enhance the system performance.
As per claim 12, Choudhary discloses wherein the interface is based on a Streaming Fabric Interface (SFI) specification (paragraph 35, streaming fabric interface architecture (SFI) may be provided in components of a system (e.g., IP blocks and components implementing the fabric of the system) to map Load/Store protocols (e.g., PCIe, CXL.io) between an agent and a fabric.)).
As per claims 13, 16, Harriman discloses a method comprising: identifying a header of a packet (paragraph 60, lines 4, the header base 605 to form the complete header for a packet), wherein the header of the packet is based on a non-flit mode format of a load/store interconnect protocol (fig.2, Layered protocol stack 200), wherein the load/store interconnect protocol further defines a flit mode (paragraph 53, lines 4-5, a flit mode when high-speed PAM4 encoding is utilized and another (e.g., non-flit) mode)); generating a flit mode version of the header of the packet, wherein the flit mode version of the header of the packet is based on a flit mode format, a first subset of fields in the non-flit mode format are also provided in the flit mode format, and a second subset of fields in the non-flit mode format are excluded in the flit mode format (paragraph 53, lines 16, second packet header format is utilized for a mode that does not utilize flits), wherein generating the flit mode version of the header of the packet comprises carrying one or more fields in the second subset of fields in repurposed fields defined in the flit mode format (paragraph 54, lines 6-8, a flit-mode TLP header may replace the traditional, orthogonal, Format (Fmt) and Type fields to a fully-decoded 8-bit TLP Type field which may be encoded with values to indicate all (or considerably all) existing TLP Types in PCIe, while adding new TLP types for no-op (NOP) and End Bad (EDB) packets types); sending the flit mode version of the header of the packet to a fabric over an interface (paragraph 24, lines 1-2, a fabric composed of point-to-point Links that interconnect a set of components), wherein the flit mode version of the header of the packet is sent on a header channel implemented on a first plurality of physical lanes (paragraph 50, lines 7-9, a link or PHY layer may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider); and sending payload data of the packet to the fabric over the interface(paragraph 24, lines 1-2, a fabric composed of point-to-point Links that interconnect a set of components).
Harriman discloses all the limitations as the above but does not explicitly disclose wherein the payload data of the packet is sent over a data channel implemented on a separate, second plurality of physical lanes. However, Choudhary discloses this (paragraph 31, lines 16-20, an improved streaming interface may bifurcate the header and data of packets into independent physical channels (e.g., a header channel and a data channel) to thereby allow the receiver to start processing the headers while data is still streaming in and thereby helps reduce overall latency and buffer sizing and complexity.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Choudhary with the teaching of Lim so as to allow on the receiving side to enhance the timing when header data is received in relation to the reception of the payload data. That enhanced timing may serve for a more efficient data reception processing reducing the overall latency so as to control efficiently, thus enhance the system performance.
As per claim 14, Choudhary discloses wherein the interface is defined according to an SFI specification and the load/store protocol comprises one of PCIe or CXL.io (paragraph 35, streaming fabric interface architecture (SFI) may be provided in components of a system (e.g., IP blocks and components implementing the fabric of the system) to map Load/Store protocols (e.g., PCIe, CXL.io) between an agent and a fabric.)).
As per claim 15, Harriman discloses wherein the flit mode version of the header of the packet is sent on a first subset of the first plurality of physical lanes, and the method comprises: sending header metadata on the interface using a second subset of the second plurality of physical lanes of the header channel (paragraph 50, lines 7-9, a link or PHY layer may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider).
As per claim 17, Harriman discloses the system further comprising a buffer less arbiter to facilitate a one-to-many connection on the interface (paragraph 97, reorder buffers to track instruction results).
As per claim 18, Choudhary discloses the system further comprising a credit gasket to convert dedicated credits used by a transmitter on a first one of the compute blocks to shared credits used by a receiver on a second one of the compute blocks (paragraph 37, lines 14-15, a receiver buffer for the SFI interface 205a for use in maintaining flow control credits (including shared credits for the channels of the SFI interface).
As per claim 19, Harriman discloses wherein the fabric comprises an interconnect fabric of a system on chip (SoC) device, and the SoC device comprises the plurality of compute blocks (paragraph 110, Chipset 1690 also exchanges information with a high-performance graphics circuit 1638 via an interface circuit 1692 along a high-performance graphics interconnect).
As per claim 20, Harriman discloses wherein the interface comprises a header channel comprising a set of dedicated physical lanes to communicate packet headers (paragraph 60, lines 4, the header base 605 to form the complete header for a packet), and the flit mode is to be used for headers communicated on the header channel (paragraph 39, channel identifier field 306).
5.The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Lim et al. [Pub. No. US20230396268] discloses The PCIe supports multiple encoding types and two data stream modes (flit mode and non-flit mode).
Brewer et al. [Pub. No. US20190243700] discloses The protocol layer defines the use of multiple packets to perform higher level operations.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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