Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: Specification paragraph [0049] contains a capital X in ‘eXternal’.
Appropriate correction is required.
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because Figures 1-4 and 7 contain barely legible/faded/unclear text. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-12, and 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Robinson et al. Pat. No. US 5524244 A (hereafter Robinson) in view of MACLEAN et al. Pub. No. US 2016/0239276 A1 (hereafter Maclean).
Regarding claim 1, the Robinson teaches “An apparatus comprising: a processing circuit to perform a task of a … data flow … ([Col. 6, lines 5-34] teaches of general signal processor(s) (GSP) that can perform general processing functions);
an input memory for the task of the … data flow …; an output memory for the task of the … data flow …; a … data flow manager circuit to store user-visible state for the input memory and the output memory (Figs. 4a-4c, 8, & [Col. 15, lines 26-65] teaches of input and output circuitry, and a FIFO buffer is used as the memory as it is implemented within data RAM, capable of outputting and receiving data directed by a data flow manager (DFM), the DFM being able to cause a decoder to write flags to the flag bus (to the GSPs) regarding a status of the buffers such that these represent a user-visible state of the I/O buffers. Also see [Col. 18, line 45 – Col. 19, line 10] for more details regarding flags representing buffer and state of the DFM);
and a … data flow functional circuit to cause the processing circuit to perform the task based on the user-visible state from the … data flow manager circuit ([Col. 10, line 61 – Col. 12, line 67] teaches of GSP components including a block controller, a program control logic block, an ALU block, and a flag block coupled together such that they represent a functional circuit. The blocks may read the status of a plurality of status flags in order to determine the next step of execution)”.
Robinson may not explicitly teach the limitation of a synchronous data flow graph model.
Maclean teaches of a synchronous data flow graph model such that it teaches the limitation “a synchronous data flow graph ([0002-0006] teaches of a synchronous data flow graph schema)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to have applied the known techniques of Maclean to the invention of Robinson to represent processing operations as nodes of a SDFG and managing execution based on the availability of input data. A person having ordinary skill in the art would have been motivated to make this combination in order to provide a deterministic coordination of processing and data movement (Maclean [0003]), as well as providing controlled coordination of data availability and execution, thereby avoiding data flow deadlock (Maclean [0004-0005], achieving overall flexibility when managing data flow (Maclean [0006]). Together, Maclean in combination with Robinson teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said techniques to yield predictable results.
Regarding claims 8 and 14, they are similar to claim 1 and are rejected for the same reasons. Claim 8 is directed towards “A method… ([Col. 83, lines 20 – 35])”. Claim 14 is directed towards “A system comprising: a processor… ([Abs])”.
Regarding claim 2, the combination teaches “The apparatus of claim 1, wherein the synchronous data flow manager circuit is to check if a first memory access request for the input memory is for the task, and if so, update the user-visible state accordingly (Robinson Figs. 4a-4c, 8, & [Col. 15, lines 26-65] teaches the DFM writing flags regarding the status of the buffers, wherein the DFM handles the flow of data in and out of the buffers; Maclean [0062] teaches that each node may have an associated input buffer. Examiner notes that a POSITA could have been motivated to make this combination to monitor incoming data accesses associated with the input buffers, wherein the DFM may write flags regarding the status of buffers respective to their nodes, allowing for informed determinations of whether to fire the node or not once sufficient input data is met).”
Regarding claims 9 and 15, they are similar to claim 2 and are rejected for the same reasons.
Regarding claim 3, the combination teaches “The apparatus of claim 2, wherein the synchronous data flow manager circuit is to check if a second memory access request for the output memory is for the task, and if so, update the user-visible state accordingly (Robinson Figs. 4a-4c, 8, & [Col. 15, lines 26-65] teaches the DFM writing flags regarding the status of the buffers, wherein the DFM handles the flow of data in and out of the buffers; Maclean [0051-0052] teaches of output arcs, wherein N samples are generated after firing a node. Examiner notes that a POSITA could have been motivated to make this combination to have the DFM output the samples in the buffer and write flags accordingly, tracking the progress of a task based on the output transfer ”.
Regarding claims 10 and 16, they are similar to claim 3 and are rejected for the same reasons.
Regarding claim 4, the combination teaches “The apparatus of claim 1, wherein the user-visible state is on a per task granularity for a plurality of tasks of the synchronous data flow graph (Maclean [0062] teaches that each node may have an input buffer, and each arc from node to node may include an independent buffer node serving as a deque such that it may represent an output buffer for storing samples until a threshold is reached. Robinson [Col. 15, lines 26-44] teaches the DFM writing flags regarding the status of buffers such that it would be obvious to have a status defining each of the buffers for each of the nodes)”.
Regarding claims 11 and 17, they are similar to claim 4 and are rejected for the same reasons.
Regarding claim 5, the combination teaches “The apparatus of claim 1, wherein the synchronous data flow manager circuit is to cause an update of a second processing circuit based on an update to the user-visible state (Robinson [Col. 15, lines 26-44] teaches of writing flags regarding the status of buffers to a flag bus which is directed to the plurality of GSPs. Wherein Maclean [0003] teaches of firing a node upon reaching a threshold of input data such that it would require an update from the DFM as data will be moved, changing the status of the buffers. As such, the corresponding flag will be provided to a GSP through the flag bus. The GSP’s wait state is thereby changed in response to the data flow event. Also see Robinson [Col. 12, line 9 – Col. 17, line 14] with regards to the GSP in its wait state)”.
Regarding claims 12 and 18, they are similar to claim 5 and are rejected for the same reasons.
Claims 6, 7, 13, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Robinson and Maclean as used above in claims 1, 8 and 14, and in further view of Chang Pub. No. US 2004/0015969 A1.
Regarding claim 6, the combination may not explicitly teach of a memory access request comprising a metadata field.
Chang teaches of a task cycle format such that it teaches the limitation “The apparatus of claim 1, wherein each of a first memory access request for the input memory and a second memory access request for the output memory comprise a metadata field that identifies the task (Fig. 3 & [0035-0037] teaches a task cycle format that specifies a task identifier, and memory request that specifies a read or write request of the data associated with the task)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Chang to the combination of Robinson and Maclean to have a task cycle format including memory requests and an identifier identifying the task. A person having ordinary skill in the art would have been motivated to make this combination in order to identify which task buffer to direct the request towards.
Regarding claims 13 and 19, they are similar to claim 6 and are rejected for the same reasons.
Regarding claim 7, the combination teaches “The apparatus of claim 6, wherein the metadata field comprises a field that, when set, indicates a memory access request to all terminals of the task (Chang [0039-0057] teaches a start address and a task block size, where all task cycles access blocks of consecutive addresses, effectively tracking the task across different processors; there exists the entry task ID in order to determine whether the task is continued onto another processor or if a task terminator is reached, effectively indicating that the task may be continued to all related processors until terminated).”
Regarding claim 20, it is similar to claim 7 and it is rejected for the same reasons.
Conclusion
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/BRANDON NGUYEN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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