CTNF 18/345,313 CTNF 99378 Detailed Action This action is in responsive to the application filed 06/30/2023, in which: Claims 1 and 11 are the independent claims. Claims 1 - 20 are currently pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 10 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The phrase “ is employed after execution ” in Dependent Claims 10 and 20 is an unclear phrase which renders the claim indefinite as the limitation notes employing the mechanism after execution where the claims are dependent on the independent claim which recite defining, executing , and checkpointing, comprises using a mechanism that improves and/or enhances performance of the checkpointing . It is unclear as the independent claims discuss using the mechanism during the execution (defining; executing; checkpointing); however, the dependent claims discuss being employed after the execution. For the purpose of applying prior art, “ is employed after execution ” phrase within wherein the mechanism is employed after execution of the quantum circuit has been completed has been interpreted as “ wherein the mechanism is employed during or after execution of the quantum circuit has been completed ”. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1 - 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Regarding Claim 1 : Subject Matter Eligibility Analysis Step 1: Claim 1 recites a method , thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 1 further recites the method comprising of: defining a quantum circuit (a human being can mentally apply evaluation and define/explain/describe a quantum a circuit) orchestrating the quantum circuit to a computing infrastructure for execution (a human being can mentally apply evaluation and make a judgement to coordinate/orchestrate a specific circuit to a specific infrastructure for execution/performance) … checkpointing the quantum circuit … (a human being can mentally apply evaluation to checkpoint (a determination/evaluation) of a specific circuit) Claim 1 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the additional elements recited consists of: executing the quantum circuit on the infrastructure (This limitation is recited in a merely generic manner and amounts to executing the quantum circuit on an infrastructure is an insignificant extra solution activity (see MPEP 2106.05(g)) while the quantum circuit is being executed, ... , wherein one of the defining, executing, and checkpointing, comprises using a mechanism that improves and/or enhances performance of the checkpointing (to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)) Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, alone or in combination, do not provide significantly more than the abstract idea itself. Additional element a falls within MPEP 2106.05(d) as well-understood, routine and conventional activities (MPEP 2106.05(d)(I)(2): Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018) ). This limitation is recited in a merely generic manner and amounts to executing the quantum circuit on an infrastructure which is well-understood, routine, and conventional activity. A factual determination that this element is well-understood, routine, and conventional activity (see MPEP 2106.05(d)(I) is supported by, Bravi et. al, “The future of quantum computing with superconducting qubit”, where Page 13, Column 1, Paragraph 1 recites “… we define a quantum circuit as follows: A quantum circuit is a computational routine consisting of coherent quantum operations on quantum data , such as qubits, and concurrent (or real- time) classical computation …”). Additional element b is merely applying the abstract idea on a computer (MPEP 2106.05(f)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claim 2 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 2 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 2 further recites the method comprising of and/or acknowledging to a classical computing infrastructure that execution of the quantum circuit has reached a specified point (a human being can mentally apply evaluation to make a judgement that a specific circuit has reached a specific point). Claim 2 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the additional elements recited consists of: collecting telemetry concerning execution of the quantum circuit (which is insignificant extra-solution activity of data gathering, by MPEP 2106.05(g)) wherein the mechanism comprises including a custom call-back gate in the quantum circuit as part of the defining of the quantum circuit, and the custom call-back gate, when executed, performs, or causes the performance of, one or more of: a portion of the checkpointing (to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)) Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, alone or in combination, do not provide significantly more than the abstract idea itself. Additional element a falls within MPEP 2106.05(d) as well-understood, routine and conventional activities of receiving or transmitting data over a network (MPEP 2106.05(d)(II): buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) ). Additional element b is merely applying the abstract idea on a computer (MPEP 2106.05(f)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claim 3 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 3 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 3 further recites the method comprising of … and the mechanism comprises using quantization … (a mathematical relationship between variables and/or numbers using a mathematical formula/equations). Claim 3 thus recites an abstract idea (that falls into the “mathematical concepts”). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the new sole additional element recited consists of wherein a state of the quantum circuit is captured after execution of a gate of the quantum circuit … to store the state of the quantum circuit (to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)). Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the new sole additional element recited, alone or in combination, does not provide significantly more than the abstract idea itself. The additional element falls is merely applying the abstract idea on a computer (MPEP 2106.05(f)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claim 4 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 4 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 4 does not recite any additional abstract ideas and only inherits the abstract ideas from Claim 1 . Claim 4 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the new sole additional element recited consists of wherein the mechanism comprises using persistent memory and orchestration in the checkpointing, and using the persistent memory comprises at least partly storing a state of the quantum circuit after the checkpointing (to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)). Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the new sole additional element recited, alone or in combination, does not provide significantly more than the abstract idea itself. The additional element falls is merely applying the abstract idea on a computer (MPEP 2106.05(f)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claim 5 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 5 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 5 further recites the method comprising of wherein the mechanism comprises dynamically determining when to perform the checkpointing (a human being can mentally apply evaluation to dynamically determine when to perform an action). Claim 5 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because there are no new additional elements recited. Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because there are no new additional elements recited. Regarding Claim 6 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 6 recites the method of Claim 5 . Claim 5 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 6 further recites the method comprising of wherein dynamically determining when to perform the checkpointing comprises balancing a speed of execution of the quantum circuit with a stability of execution of the quantum circuit (a human being can mentally apply evaluation to determine when to perform the checkpointing based on data for specific speeds/stability of execution). Claim 6 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because there are no new additional elements recited. Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because there are no new additional elements recited. Regarding Claim 7 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 7 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 7 further recites the method comprising of … and the mechanism comprises performing … flattening of the state vector of the quantum circuit (a mathematical relationship between variables and/or numbers using a mathematical formula/equations). Claim 7 thus recites an abstract idea (that falls into the “mathematical concepts”). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the new sole additional element recited consists of wherein a state vector of the quantum circuit is captured during the executing, … automated … (to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)). Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the new sole additional element recited, alone or in combination, does not provide significantly more than the abstract idea itself. The additional element falls is merely applying the abstract idea on a computer (MPEP 2106.05(f)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claim 8 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 8 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 8 does not recite any additional abstract ideas and only inherits the abstract ideas from Claim 1 . Claim 8 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the new sole additional element recited consists of wherein the checkpointing comprises performing a respective checkpointing after each gate, in a group of gates of the quantum circuit, is executed (to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)). Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the new sole additional element recited, alone or in combination, does not provide significantly more than the abstract idea itself. The additional element falls is merely applying the abstract idea on a computer (MPEP 2106.05(f)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claim 9 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 9 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 9 does not recite any additional abstract ideas and only inherits the abstract ideas from Claim 1 . Claim 9 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the new sole additional element recited consists of wherein the computing infrastructure comprises one or both of, a classical computing infrastructure, and a quantum computing infrastructure (to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)). Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the new sole additional element recited, alone or in combination, does not provide significantly more than the abstract idea itself. The additional element falls is merely applying the abstract idea on a computer (MPEP 2106.05(f)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claim 10 : Subject Matter Eligibility Analysis Step 1: Dependent Claim 10 recites the method of Claim 1 . Claim 1 is a method, thus a process, one of the four statutory categories of patentable subject matter. Subject Matter Eligibility Analysis Step 2A Prong 1: However, Claim 10 does not recite any additional abstract ideas and only inherits the abstract ideas from Claim 1 . Claim 10 thus recites an abstract idea (that falls into the “mental processes” group of abstract ideas). Subject Matter Eligibility Analysis Step 2A Prong 2: This judicial exception is not integrated into a practical application because the new sole additional element recited consists of wherein the mechanism is employed after execution of the quantum circuit has been completed (which is restricting the abstract idea to a Particular Technological Environment, by MPEP 2106.05(h)). Subject Matter Eligibility Analysis Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the new sole additional element recited, alone or in combination, does not provide significantly more than the abstract idea itself. The additional element falls is only restricting the abstract idea to a Particular Technological Environment (MPEP 2106.05(h)) which cannot provide significantly more. Thus, the claim is subject-matter ineligible . Regarding Claims 11 - 20 : Claims 11 - 20 incorporates substantively all the limitations of Claims 1 - 10 in a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising (these claim limitations appear to perform a mental process and the performance of an abstract idea on a computer is no more than instructions to “apply it” on a computer, by MPEP 2106.05(f)) and does not appear to integrate the abstract idea into a particular application; thus, the claim is subject matter ineligible as it does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, alone or in combination, and do not provide significantly more than the abstract idea itself); thus, Claims 11 - 20 are rejected for reasons set forth in the rejection of Claims 1 - 10 , respectively. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 - 2 , 8 - 12 , and 18 - 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Narayanan et al., “Reducing Memory Requirements of Quantum Optimal Control” . Regarding Claim 1 : Narayanan teaches: A method, comprising: (Narayanan, Page 1, Abstract, “ Quantum optimal control problems are typically solved by gradient-based algorithms such as GRAPE … We have created a nonstandard automatic differentiation technique … Our approach significantly reduces the memory requirements for GRAPE , at the cost of a reasonable amount of recomputation. We present … an implementation in JAX ”. Narayanan teaches a method for reducing memory requirements of a quantum optimal control problem ). defining a quantum circuit; (Narayanan, Page 1, Paragraph 1, “… In quantum computing , quantum algorithms are often expressed by using a quantum circuit model , in which a computation is a sequence of quantum gates . Quantum gates are the building blocks of quantum circuits …”; Page 2, Equation 3, “ K j = U j U j-1 U j-2 … U 1 U 0 … K j and U j are 2 q X 2 q , where q is the number of qubits in the system … trace distance between K N and a target quantum gate K T … ”; Page 3, Algorithm 1. Equation 3 shows the basis of computing a sequence of unitary operations which represent quantum gates (K i as K is the full circuit and U is a step within the circuit and they are represented as qubits of the system); thus, defining a quantum circuit which can be seen in Algorithm 1 as well ). orchestrating the quantum circuit to a computing infrastructure for execution; (Narayanan, Page 13, Paragraph 1, “… We have implemented a version of quantum optimal control (QOC) using the JAX framework ”; Page 3, Algorithm 1; Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. The JAX framework is used for implementing QOC (quantum optimal control); where defining the quantum circuit via mapping the logical quantum gates onto the physical quantum gates + the gradients via GRAPE (Algorithm 1) for quantum optimal control is implemented on the JAX framework (interpreted by the examiner as the computing infrastructure ; which performs the execution of the QOC methodology) ). executing the quantum circuit on the infrastructure; and (Narayanan, Page 10, Fig. 3: “ Comparison of execution time and device memory requirements for standard AD, periodic checkpointing, and full reversibility with increasing number of qubits”; Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. The quantum circuits are executed within the JAX machine learning framework (classical computer infrastructure due to containing a CPU, memory and I/O devices) ). while the quantum circuit is being executed, checkpointing the quantum circuit, (Narayanan, Page 8, Paragraph 3, “We compared standard AD, periodic checkpointing , and full reversibility or periodic checkpointing with reversibility , as appropriate. We conducted our experiments on a cluster where each compute node was connected to 8 NVIDIA A100 40GB GPUs. Each node contained 1TB DDR4 memory and 320GB GPU memory. We validated the output of the checkpointing and reversibility approaches against the standard approach implemented using JAX … We conducted three sets of experiments to evaluate the approaches , varying the number of qubits, the number of time steps, or the checkpoint period .”; Page 5, Fig. 2; Section 3 teaches reduction of memory where three different approaches are utilized for QOC; which execut es quantum circuit (Fig 2. denotes periodic checkpointing execution example via timesteps)with checkpointing and checkpointing with reversibility of the quantum circuit ). wherein one of the defining, executing, and checkpointing, comprises using a mechanism that improves and/or enhances performance of the checkpointing. (Narayanan, Page 13, Paragraph 1, “ … we demonstrated that reversibility can be combined with periodic checkpointing , reducing memory requirements relative to periodic checkpointing alone while ensuring that roundoff errors are not accumulated …”; Page 11, Fig. 5; Page 6, Table 1. Approach 3 within Section 3: Periodic Checkpointing Plus Reversibility teaches using a mechanism (interpreted as a process/function by the examiner) that improves and enhances the performance of checkpointing via reversibility (which reduces memory requirements ) as shown in Figures 5 and Table 1 ). Regarding Claim 2 : Narayanan teaches the method of Claim 1 and further teaches: wherein the mechanism comprises including a custom call-back gate in the quantum circuit as part of the defining of the quantum circuit, (Narayanan, Page 3, Fig. 1; Page 2, Equation 3, “ K j = U j U j-1 U j-2 … U 1 U 0 ”; Page 6, Paragraph 2, “ PNG media_image1.png 52 7 media_image1.png Greyscale (17) (18)… we can combine the two approaches, checkpointing every C time steps and, during the reverse pass, instead of computing forward from these checkpoints, computing backward from the checkpoints by exploiting reversibility ”. The mechanism (process/function) taught by Narayan is reversibility which checkpoints every C time steps within the sequence of gate s (like Fig. 1) to call-back via computing backwards/reversing to define the quantum circuit as shown in Equations 17 & 18 which defin e t he quantum circuit . Thus, the examiner interprets the C time stepped K j gate as the custom call-back gate (would be denoted as time step j in Fig. 1 for K j (gate) which is in part of defining the quantum circuit as K is the full circuit and U is a step in the circuit ). and the custom call-back gate when executed, performs, or causes the performance of, one or more of: a portion of the checkpointing; (Narayanan, Page 6, Paragraph 2, “… checkpointing every C time steps and, during the reverse pass , instead of computing forward from these checkpoints , computing backward from the checkpoints by exploiting reversibility ”. At C time stepped gate Kj ( custom call-back gate ) computes backwards; thus, interpreted a portion of the checkpointing via reversibility ). collecting telemetry concerning execution of the quantum circuit; … (Narayanan, Page 11, Fig. 4: “Comparison of the execution time for standard AD, periodic checkpointing, and periodic reversibility approaches with increasing number of time steps . The QOC simulation consisted of 8 (left) or 9 (right) qubits. The checkpoint period was chosen to be the square root of the number of time steps ”. Fig. 4 shows the collecti on/recordings of execution time via timesteps; thus, interpreted as collecting telemetry (automated collection of data for analysis) concerning the execution time of the quantum circuit ). Regarding Claim 8 : Narayanan teaches the method of Claim 1 and further teaches: wherein the checkpointing comprises performing a respective checkpointing after each gate, in a group of gates of the quantum circuit, is executed. (Narayanan, Page 3, Fig. 1; Page 6, Paragraph 2, “ PNG media_image1.png 52 7 media_image1.png Greyscale (17) (18)… we can combine the two approaches, checkpointing every C time steps and, during the reverse pass, instead of computing forward from these checkpoints, computing backward from the checkpoints by exploiting reversibility ”. The mechanism (process/function) taught by Narayan is periodic checkpointing w/ reversibility which checkpoints every C time steps within the sequence of gate s (like Fig. 1) to define the quantum circuit (shown in Equations 17 & 18) which defines the quantum circuit . Thus, the examiner interprets the periodic checkpointing of the sequence of gates where every C timesteps a group of gates of the quantum circuit (a subset of the full quantum circuit) performs a respective checkpointing after each gate in a group of gates (subset) ). Regarding Claim 9 : Narayanan teaches the method of Claim 1 and further teaches: wherein the computing infrastructure comprises one or both of, a classical computing infrastructure, and a quantum computing infrastructure. (Narayanan, Page 1, Paragraph 1, “ Quantum computing is computing using quantum-mechanical phenomena … solve problems that classical computers practically cannot . In quantum computing , quantum algorithms are often expressed by using a quantum circuit model , in which a computation is a sequence of quantum gates . Quantum gates are the building blocks of quantum circuits and operate on a small number of qubits , similar to how classical logic gates operate on a small number of bits in conventional digital circuits”; Page 13, Paragraph 1, “We have implemented a version of quantum optimal control (QOC) using the JAX framework ”; Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. The JAX framework within Narayan executing on a CPU/GPU which are foundational components of a classical computing infrastructure as and the quantum computing infrastructure is interpreted as the simulated mathematical model which represents a quantum circuit ). Regarding Claim 10 : Narayanan teaches the method of Claim 1 and further teaches: wherein the mechanism employed after execution of the quantum circuit has been completed. (Narayanan, Page 10, Fig. 3: “ Comparison of execution time and device memory requirements for standard AD, periodic checkpointing, and full reversibility …”; Page 13, Paragraph 1, “ … we demonstrated that reversibility can be combined with periodic checkpointing , reducing memory requirements relative to periodic checkpointing alone while ensuring that roundoff errors are not accumulated …”; Page 11, Fig. 5; Page 6, Table 1. The quantum circuits are executed within the JAX machine learning framework where Approach 3 within Section 3: Periodic Checkpointing Plus Reversibility teaches using a mechanism (interpreted as a process/function by the examiner) that improves and enhances the performance of checkpointing via reversibility (which reduces memory requirements ) as shown in Figures 5 and Table 1. The reversibility mechanism is employed after executing a quantum circuit because the checkpointing is able to reverse ; thus, interpreted by the examiner as reversibility ( mechanism ) being employed after execution ). Regarding Claims 11 - 12 and 18 - 20 : Claims 11 - 12 and 18 - 20 incorporates substantively all the limitations of Claims 1 - 2 and 8 - 10 in a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising (see Narayanan, Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. Thus, Narayanan’s methodology implies being incorporated on a device with memory and a processors as they are inherent within a non-transitory storage medium to be able to implement QOC (which was implemented within TensorFlow) with the JAX machine learning framework ); thus, Claims 11 - 12 and 18 - 20 are rejected for reasons set forth in the rejection of Claims 1 - 2 and 8 - 10 , respectively . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 3 , 5 , 13 , and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al., “Reducing Memory Requirements of Quantum Optimal Control”, in view of Dettmers et al., “8-BIT OPTIMIZERS VIA BLOCK-WISE QUANTIZATION” . Regarding Claim 3 : Narayanan teaches the method of Claim 1 and further teaches: wherein a state of the quantum circuit is captured after execution of a gate of the quantum circuit, and the mechanism comprises … to store the state of the quantum circuit. (Narayanan, Page 3, Fig. 1: “… Each of forward … reverse time step j uses the previously stored K j , U j , and ψ j …”; Page 2, Equation 3-4, “ PNG media_image2.png 42 194 media_image2.png Greyscale ”; Page 6, Equations 17 &18 “ PNG media_image1.png 52 7 media_image1.png Greyscale …”; Page 5, Fig, 2: “state”. Fig 1. Notes how each forward step store s the values after execution in memory and when reversing it will use the previous states store d in memory. Thus, the state of the quantum circuit is captured after execution of a gate as Fig.1 shows each K gate has an associate ψ state; and Equation 18 & 4 are for quantum state values ). However, Narayanan does not explicitly disclose storing state values via quantization. However, Dettmers teaches: … and the mechanism comprises using quantization to store the state of the quantum circuit. (Dettmers, Page 2, Figure 1. Figure 1 denotes using quantization for state values that are store d via index values; thus, interpreted by the examiner as mechanism comprising using quantization to store the state values ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Narayanan’s methodology of reducing memory via orchestrating quantum control via checkpointing + reversibility with Dettmers use of quantization to maintain performance, handle outliers, no change in hyperparameters, memory efficiency/footprint, and stability (Dettmers, Page 2, Paragraph 2, “ We introduce a new block-wise quantization approach that addresses all three of these challenges . Block-wise quantization splits input tensors into blocks and performs quantization on each block independently . This block-wise division reduces the effect of outliers on the quantization process since they are isolated to particular blocks , thereby improving stability and performance , especially for large-scale models. Block-wise processing also allows for high optimizer throughput since each normalization can be computed independently in each core … We combine block-wise quantization with two novel methods for stable, high-performance 8-bit optimizers : dynamic quantization and a stable embedding layer . Dynamic quantization is an extension of dynamic tree quantization for unsigned input data. The stable embedding layer is a variation of a standard word embedding layer that supports more aggressive quantization by normalizing the highly non-uniform distribution of inputs to avoid extreme gradient variation . Our 8-bit optimizers maintain 32-bit performance at a fraction of the original memory footprint ”). Regarding Claim 5 : Narayanan teaches the method of Claim 1 and further teaches: wherein the mechanism comprises … determining when to perform the checkpointing. (Narayanan, Page 6, Paragraph 2, “… checkpointing every C time steps and, during the reverse pass , instead of computing forward from these checkpoints , computing backward from the checkpoints by exploiting reversibility ”. Narayanan teaches determining when to perform checkpointing via a static determin ation (predefined checkpoint interval = C)). Narayanan teaches determining when to perform checkpointing via a static determination (predefined checkpoint interval = C) but unfortunately does not explicitly teach: … dynamically determining … However, Dettmers teaches: … dynamically determining … (Dettmers, Page 2, Figure 1: “”. Figure 1 shows the 8-bit optimizer which performs block-wise dynamic quantization which is dynamically determining state values into index values for storage and dequantization ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Narayanan’s methodology of reducing memory via orchestrating quantum control via checkpointing + reversibility with Dettmers use of quantization to maintain performance, handle outliers, no change in hyperparameters, memory efficiency/footprint, and stability (Dettmers, Page 2, Paragraph 2, “ We introduce a new block-wise quantization approach that addresses all three of these challenges . Block-wise quantization splits input tensors into blocks and performs quantization on each block independently . This block-wise division reduces the effect of outliers on the quantization process since they are isolated to particular blocks , thereby improving stability and performance , especially for large-scale models. Block-wise processing also allows for high optimizer throughput since each normalization can be computed independently in each core … We combine block-wise quantization with two novel methods for stable, high-performance 8-bit optimizers : dynamic quantization and a stable embedding layer . Dynamic quantization is an extension of dynamic tree quantization for unsigned input data. The stable embedding layer is a variation of a standard word embedding layer that supports more aggressive quantization by normalizing the highly non-uniform distribution of inputs to avoid extreme gradient variation . Our 8-bit optimizers maintain 32-bit performance at a fraction of the original memory footprint ”). Regarding Claims 13 and 15 : Claims 13 and 15 incorporates substantively all the limitations of Claims 3 and 5 in a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising (see Narayanan, Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. Thus, Narayanan’s methodology implies being incorporated on a device with memory and a processors as they are inherent within a non-transitory storage medium to be able to implement QOC (which was implemented within TensorFlow) with the JAX machine learning framework ); thus, Claims 13 and 15 are rejected for reasons set forth in the rejection of Claims 3 and 5 , respectively . 07-21-aia AIA Claim s 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al., in view of Huang et al., “High Performance Data Persistence in Non-Volatile Memory for Resilient High Performance Computing” . Regarding Claim 4 : Narayanan teaches the method of Claim 1 and further teaches: wherein the mechanism comprises using … memory and orchestration in the checkpointing, and using the … memory comprises at least partly storing a state of the quantum circuit after the checkpointing. (Narayanan, Page 3, Fig. 1: “… Each of forward … reverse time step j uses the previously stored K j , U j , and ψ j …”; Page 2, Equation 3-4, “ PNG media_image2.png 42 194 media_image2.png Greyscale ”; Page 6, Equations 17 &18 “ PNG media_image1.png 52 7 media_image1.png Greyscale …”; Page 5, Fig, 2: “state”. Fig 1. Notes how each forward step store s the values after execution in memory and when reversing it will use the previous states store d in memory . Thus, the state of the quantum circuit is captured after execution of a gate as Fig.1 shows each K gate has an associate ψ state; and Equation 18 & 4 are for quantum state values. Where the Jax machine learning framework orchestrates the checkpointing and gradient computations ). However, Narayanan does not explicitly disclose persistent memory. However, Huang teaches: … persistent memory … (Huang, Page 5, Column 1, Figure 6: “Performance (execution time) of NVM-based checkpoint with optimization ( NVM is used as main memory ). Performance is normalized by that of the native performance without checkpoint”; Page 9, Column 2, Paragraph 6,” Persistent memory . NVM has been explored to implement checkpoint as main memory ”. Huang teaches checkpoint optimization via utilizing an NVM (non-volatile memory) which is a type of persistent memory; thus, teaching checkpointing and orchestrating the checkpointing optimization using persistent memory ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Narayanan’s methodology of reducing memory via orchestrating quantum control via checkpointing + reversibility with Huang’s use of persistent memory to leverage performance and non-volatility/persistence memory characteristics (Huang, Page 9, Column 2, Paragraph 6,” Persistent memory. NVM has been explored to implement checkpoint as main memory . Kannan et al. [21] use NVM only for checkpoint (not computation). To improve performance , they proactively move checkpoint data from DRAM to NVM before checkpoint is started … for load balance … dynamically determine checkpoint granularity … to reduce checkpoint overhead … we focus on how to maximize the benefit of non-volatility of NVM … our work avoids data copying , and does not require hardware assist ”). Regarding Claim 14 : Claim 14 incorporates substantively all the limitations of Claim 4 in a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising (see Narayanan, Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. Thus, Narayanan’s methodology implies being incorporated on a device with memory and a processors as they are inherent within a non-transitory storage medium to be able to implement QOC (which was implemented within TensorFlow) with the JAX machine learning framework ); thus, Claim 14 is rejected for reasons set forth in the rejection of Claim 4 . 07-21-aia AIA Claim s 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al., “Reducing Memory Requirements of Quantum Optimal Control”, in view of Dettmers et al., “8-BIT OPTIMIZERS VIA BLOCK-WISE QUANTIZATION”, in view of Khaneja et al., “Optimal control of coupled spin dynamics: design of NMR pulse sequences by gradient ascent algorithms” . Regarding Claim 6 : Narayanan/Dettmers teach the method of Claim 5 and Narayanan/Dettmers in combination teach dynamically determining when to perform the checkpointing as noted within Claim 5 . Even though Narayan mentions the GRAPE algorithm, Narayanan/Dettmers don’t explicitly disclose the determination to comprise of: … balancing a speed of execution of the quantum circuit with a stability of execution of the quantum circuit. However, Khaneja teaches: … balancing a speed of execution of the quantum circuit with a stability of execution of the quantum circuit. (Khaneja, Page 297, Fig. 1; Page 298, Column 1, Basic Grape Algorithm: “ PNG media_image3.png 137 330 media_image3.png Greyscale ”. Fig. 1 denotes a schematic of control amplitudes utilizing gradients to modify/balance the next iteration for performance by balancing Δt and the vertical arrow (∂ψ/ ∂u(j) gradients (where ψ denotes the performance function and u denotes the control amplitude)) within Fig. 1; thus, interpreted by the examiner as balancing speed of execution and stability of execution (as Δt denotes execution speed via width and the vertical arrows denotes the increase or decrease of the performance function for the next iteration to keep optimizing performance (interpreted as stability) ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Narayanan/Dettmers’ methodology of reducing memory via orchestrating quantum control via checkpointing + reversibility + use of quantization with the explicitly balancing of speed/stability of execution taught by Khaneja to have optimal control/pulses, suppress undesired coherence transfers (stability), and handling of convergence (speed) (Khaneja, Page 303, Column 2, Paragraph 1 “In this paper, we have presented a streamlined derivation of analytical gradients for the design of pulse sequences in NMR spectroscopy. We applied these optimal control related algorithms to the design of pulse shapes for problems involving transfer of coherence between coupled spins and synthesis of unitary propagators in a network of coupled spins . … the proposed algorithms will converge to a stationary point of the performance function . To speed up convergence , the algorithm can be further modified by using adaptive step sizes for updating the control amplitudes as well as by using conjugate gradients instead of ordinary ones …”). Regarding Claim 16 : Claim 16 incorporates substantively all the limitations of Claim 6 in a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising (see Narayanan, Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. Thus, Narayanan’s methodology implies being incorporated on a device with memory and a processors as they are inherent within a non-transitory storage medium to be able to implement QOC (which was implemented within TensorFlow) with the JAX machine learning framework ); thus, Claim 16 is rejected for reasons set forth in the rejection of Claim 6 . 07-21-aia AIA Claim s 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al., in view of Tanveer et al., US-2024/0071049-A1 . Regarding Claim 7 : Narayanan teaches the method of Claim 1 and further teaches: wherein a state … of the quantum circuit is captured during the executing, and the mechanism comprises … (Narayanan, Page 3, Fig. 1: ψ; Page 5: Fig 2: “state”. ψ within Fig.1 denotes the state where Fig.1 is a sequence of gates for a quantum circuit during execution via time steps. Fig. 2 shows the state being captured during the quantum circuit ’s executi on ). Narayanan teaches capturing a state of the quantum circuit during execution. However, Narayana does not explicitly teach capturing a state vector and the mechanism being able to perform automated flattening of the said vector. However, Tanveer teaches: … vector … and the mechanism comprises performing automated flattening of the … vector of the … (Tanveer, FIG. 11; [0071], “ FIG. 11 is a diagram illustrating how each feature map can be encoded to capture its shape and laid out in a combined feature vector for flattening by the flattener 414 … The present techniques provide a different way of flattening altogether in which flattener 414 concatenates the encodings from each of the filters … the present techniques provide a … new way of flattening that preserves the identity of the filter and their shape encodings”. Fig. 11 shows a process for flattening via the flattening step which performs the automated flattening of the vector (combined feature vector) of the image ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Narayanan’s methodology of reducing memory via orchestrating quantum control via checkpointing + reversibility with Tanveer’s performing of flattening of vectors to preserve the identity/shape of the state vector/encodings (Tanveer, [0071], “… Thus, the present techniques provide a novel process and architecture for capturing the shape of the filter through the auto-encoder 412 , a new way of flattening that preserves the identity of the filter and their shape encodings , and finally, training the auto-encoder 412 end-to-end with the target downstream task (in this case classification)”). Regarding Claim 17 : Claim 17 incorporates substantively all the limitations of Claim 7 in a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising (see Narayanan, Page 7, Paragraph 2, “As an initial step we have ported to the JAX machine learning framework [5] a version of QOC that was previously implemented in TensorFlow . JAX provides a NumPy-style interface and supports execution on CPU systems as well as GPU and TPU (tensor processing unit) accelerators ”. Thus, Narayanan’s methodology implies being incorporated on a device with memory and a processors as they are inherent within a non-transitory storage medium to be able to implement QOC (which was implemented within TensorFlow) with the JAX machine learning framework ); thus, Claim 17 is rejected for reasons set forth in the rejection of Claim 7 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM RAHMAN whose telephone number is (703)756-1646. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kakali Chaki can be reached at (571) 272-3719. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /I.R./Examiner, Art Unit 2122 /KAKALI CHAKI/Supervisory Patent Examiner, Art Unit 2122 Application/Control Number: 18/345,313 Page 2 Art Unit: 2122 Application/Control Number: 18/345,313 Page 3 Art Unit: 2122 Application/Control Number: 18/345,313 Page 4 Art Unit: 2122 Application/Control Number: 18/345,313 Page 5 Art Unit: 2122 Application/Control Number: 18/345,313 Page 6 Art Unit: 2122 Application/Control Number: 18/345,313 Page 7 Art Unit: 2122 Application/Control Number: 18/345,313 Page 8 Art Unit: 2122 Application/Control Number: 18/345,313 Page 9 Art Unit: 2122 Application/Control Number: 18/345,313 Page 10 Art Unit: 2122 Application/Control Number: 18/345,313 Page 11 Art Unit: 2122 Application/Control Number: 18/345,313 Page 12 Art Unit: 2122 Application/Control Number: 18/345,313 Page 13 Art Unit: 2122 Application/Control Number: 18/345,313 Page 14 Art Unit: 2122 Application/Control Number: 18/345,313 Page 15 Art Unit: 2122 Application/Control Number: 18/345,313 Page 16 Art Unit: 2122 Application/Control Number: 18/345,313 Page 17 Art Unit: 2122 Application/Control Number: 18/345,313 Page 18 Art Unit: 2122 Application/Control Number: 18/345,313 Page 19 Art Unit: 2122 Application/Control Number: 18/345,313 Page 20 Art Unit: 2122 Application/Control Number: 18/345,313 Page 21 Art Unit: 2122 Application/Control Number: 18/345,313 Page 22 Art Unit: 2122 Application/Control Number: 18/345,313 Page 23 Art Unit: 2122 Application/Control Number: 18/345,313 Page 24 Art Unit: 2122 Application/Control Number: 18/345,313 Page 25 Art Unit: 2122 Application/Control Number: 18/345,313 Page 26 Art Unit: 2122 Application/Control Number: 18/345,313 Page 27 Art Unit: 2122 Application/Control Number: 18/345,313 Page 28 Art Unit: 2122 Application/Control Number: 18/345,313 Page 29 Art Unit: 2122
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