DETAILED ACTION
This action is in response to the submission filed on 6/30/2023. Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 11 recite “restoring a hash”. However no written description for “restoring a hash” is given in the disclosure. Furthermore, a hash cannot be restored – hashing is “lossy,” it loses information. Claims 2-10 and 12-20 are rejected by virtue of their dependency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 11 recite “restoring a hash”. However no written description for “restoring a hash” is given in the disclosure. Furthermore, a hash cannot be restored – hashing is “lossy,” it loses information.
Claims 1 and 11 recite “restoring, from storage, a latest hash of the state vector associated with one gate of the new quantum circuit” which is unclear and it is assumed it should be written in reverse order. It is recommended that the claims be amended to: “restoring, from storage, the state vector associated with the latest hash of one gate of the new quantum circuit”.
Claims 4, 14 recites: “respective hashes are restored in reverse order.” Hashes cannot be restored. Suggested language: “data structure associated with respective hashes are restored in reverse order”, or something similar.
Claims 2-10 and 12-20 are rejected by virtue of their dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 5-6, 9, 11, 13, 15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190095561 A1 (“Penault”) in view of US 20210117324 A1 (“Gunnells”).
Regarding claims 1 and 11, Penault teaches:
A method, comprising:
simulating execution of a quantum circuit on a classical computing infrastructure (Penault: paras [0042] – [0046]);
after one or more times that a gate of the quantum circuit is executed as part of the simulating (Pednault: para [0048], “In the depicted example, a two-qubit gate is being applied…”)
Penault does not teach but Gunnels does teach:
creating, after execution of that gate, a hash of a state vector that captures a state of the execution of the quantum circuit
storing the hash, and respective associated data structure, in storage (Gunnels: teaches caching the state in para [0030] “…can further provide a cached run result”);
calculating a hash of each gate across a new quantum circuit (Gunnels: teaches cache lookup; para [0030], “System 100 can also include a cache lookup component 120 that can detect a match between the normalized quantum circuit produced by the gate rewrite component 110 and a cached quantum circuit, e.g., among a set of cached quantum circuits 122. System 100 can further include a result provision component 130 that can provide a cached run result of the cached quantum circuit identified by the cache lookup component 120, e.g., based on the cache lookup component 120 detecting a match between the normalized quantum circuit and the cached quantum circuit.”);
looking up, in the storage, a hash of a state vector associated with execution of one of the gates of the new quantum circuit (Gunnels: teaches caching single gates [0040] “respective sub-circuits analyzed by the gate rewrite component 110 as shown in diagram 300 can be respective gates or sets of gates”); and
restoring, from storage, a latest hash of the state vector associated with the one gate of the new quantum circuit (Gunnels: teaches using cached state associated with one gate (sub-circuit) [0056] “the statistical analysis component can be used to identify statistically equivalent sub-circuits of a given quantum circuit, which can then be passed back to the cache lookup component”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Penault (directed to simulating quantum circuits) and Gunnels (directed to using cached state associated with a gate) and arrived at simulating quantum circuits and using cached state associated with a gate. One of ordinary skill in the art would have been motivated to make such a combination “to address the problem of further reducing the cost associated with executing quantum programs on quantum hardware” (Gunnels: para [0004]).
Regarding claims 3 and 13, Penault does not teach but Gunnels does teach:
The method as recited in claim 1, wherein the simulated execution process comprises simulating execution of a new quantum circuit that is different from the quantum
circuit but has one or more states in common with the quantum circuit (Gunnels: teaches degree of equivalency with cached circuit in para [0053]).
Regarding claims 5 and 15, Penault does not teach but Gunnels does teach:
The method as recited in claim 1, wherein the creating and storing are performed automatically during the simulating (Gunnels: teaches caching the state in para [0030] “…can further provide a cached run result”).
Regarding claims 6 and 16, Penault does not teach but Gunnels does teach:
The method as recited in claim 1, wherein restoring the latest hash obviates a need to re-execute the gate, and recalculate a state vector, to which that latest hash pertains (Gunnels: teaches applying a cached result instead of running in para [0031]).
Regarding claims 9 and 19, Penault does not teach but Gunnels does teach:
The method as recited in claim 1, wherein hashes are created for fewer than all of the gates of the quantum circuit (Gunnels: teaches caching whole quantum circuits in para [0031]).
Claims 7, 10, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190095561 A1 (“Penault”) in view of US 20210117324 A1 (“Gunnells”), further in view of “Technical Correspondence Techniques for Automatic Memoization with Applications to Context-Free Parsing” (“Norvig”).
Regarding claims 7 and 17, Penault and Gunnels do not teach but Norvig does teach:
The method as recited in claim 1, wherein the hashes of the state vectors are created each time a gate is executed (Norvig: teaches memoization with hash-tables as well known, and also that “caching” term is used in regards to memoization, a type of software cache; pages 91-94, teaches “caching” as automatically run for each operation).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Penault and Gunnels (directed to simulating quantum circuits) and Norvig (directed to memoization with hash-tables) and arrived at simulating quantum circuits hash tables. One of ordinary skill in the art would have been motivated to make such a combination because “programmer is freed from having to remember to declare, allocate, and initialize a rule table, but still gets the benefit of efficient access to the rules. This is the ultimate data abstraction: the programmer is shielded not only from the details of the implementation of the table, but even from the existence of a table at all” (Norvig: Conclusion).
Regarding claims 10 and 20, Penault does not teach but Gunnels does teach:
The method as recited in claim 1, wherein when a gate execution does not affect the state, that state is not hashed (Norvig: teaches memoization with hash-tables as well known, and also that “caching” term is used in regards to memoization, a type of software cache; pages 91-93, only cached if value is not found. If the state doesn’t change, this means that the state was previously cached (in embodiments where caching happens at every step) thus the result is not hashed, because it already exists in the cache).
Allowable Subject Matter
Claims 2, 4, 8, 12, 14, and 18 contain allowable subject matter.
The claims will be allowable if the rejections under 35 USC 112 are overcome.
The independent claims will be in condition for allowance when the allowable dependent claims are incorporated into the independent claims, in addition to overcoming the 112 rejections.
Penault, Gunnels and Norvig teach a method for simulation of a quantum circuit using hashing.
However, these references and the remaining prior art of record, alone or in combination, fails to disclose or suggest
(claims 2, 12)
“wherein the simulated execution process comprises a resumption of the simulating of the execution of the quantum circuit”,
(claims 4, 14)
“wherein the restoring is performed for multiple gates and, for each gate, respective hashes are restored in reverse order”,
(claims 8, 18)
“wherein a gate of the quantum circuit comprises a custom gate which, when executed, triggers hashing of a state vector associated with the custom gate”,
in combination with the remaining elements and features of the claimed invention. It is for these reasons that the applicant’s invention defines over the prior art of record.
Additional References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and are cited in the attached PTOL-892.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NITHYA J. MOLL whose telephone number is (571)270-1003. The examiner can normally be reached Monday-Friday 10am-6pm EST.
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/NITHYA J. MOLL/Primary Examiner, Art Unit 2189
