Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on June 30, 2023 and June 19, 2024. U.S. patents and patent application publications, foreign patents and patent application publications, and non-patent literature documents have been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hundal (US 2016/0110305) in view of Baker (US 8976799).
Regarding Claim 1: Hundal teaches a system having physical board and connector components, specifically teaching:
“A circuit board comprising:” (Hundal [0037], [0041], teaching a printed circuit board assembly).
“a Universal Serial Bus (USB) connector on the circuit board” and “wherein the USB connector is to output the display port stream data.” (Hundal [0005], teaching a USB Type-C receptacle; and Hundal [0031], teaching the DisplayPort GPU provides lanes of DisplayPort output routed through the USB Type-C receptacle).
However, Hundal does not explicitly teach “decoding circuitry to decode Peripheral Component Interconnect Express (PCIe) data packets into a display port stream data, the PCIe data packets encoded by a discrete graphics circuitry;” and does not teach the USB connector “coupled to the decoding circuitry”.
Baker teaches:
“decoding circuitry to decode Peripheral Component Interconnect Express (PCIe) data packets into a display port stream data” (Baker [0043], [0051], teaching a DP decoder/encoder 90 that receives PCIe Vendor Defined Messages (VDMs) and decodes the VDMs to encode the data into the desired DisplayPort stream).
“the PCIe data packets encoded by a discrete graphics circuitry;” (Baker [0088], teaching a graphics processing unit (GPU) that is a separate unit communicating via PCIe Graphics; and Baker [0043], teaching encoding the DP stream into PCIe VDMs).
“coupled to the decoding circuitry” (Baker [0038], [0049], teaching the decoding/encoding adapters are coupled to the egress circuitry and output ports).
Before the effective filling date of the claimed inventions. It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the circuit board and USB connector of Hundal to include the PCIe decoding circuitry and discrete graphics PCIe encoding taught by Baker. The motivation for this modification would be to provide a converged I/O interface that encapsulates high-bandwidth native video formats into standardized PCIe packets for efficient, packet-switched routing across internal system buses before reconstructing the stream for output over a single physical USB connector (as taught by Baker [0006]).
Regarding Claim 2: Hundal in view of Baker teaches the circuit board of claim 1. Hundal further teaches “further including an integrated USB sub- system” (Hundal [0030], [0037], teaching a USB host or hub 408 embedded in the computing device). Baker teaches the USB sub-system “coupled to the decoding circuitry.” (Baker [0038], [0049], teaching a USB controller 70 coupled to the bus 40 and PCIe adapters).
Regarding Claim 3: Hundal in view of Baker teaches the circuit board of claim 1. Baker further teaches “wherein the discrete graphics circuitry transmits PCIe data packets to a USB sub-system based on PCIe peer-to-peer transaction” (Baker [0045], teaching a peer management adapter 122 that supports peer-to-peer functionality for routing packets between endpoints). Examiner’s Note: The use of a “dedicated virtual channel” is a standard, well-known feature of PCIe packet routing architecture inherent to the PCIe standard utilized by Baker.
Regarding Claim 4: Hundal in view of Baker teaches the circuit board of claim 1. Baker further teaches “wherein the circuit board is in a housing, and there is no cabling external to the housing to couple a discrete graphics card to a USB sub-system.” (Baker [0087]-[0088], teaching the computer is a laptop or iMac containing internal interfaces including a GPU and an I/O controller hub on a motherboard, requiring no external cabling for internal routing).
Regarding Claim 5: Hundal in view of Baker teaches the circuit board of claim 1. Baker further teaches “wherein the decoding circuitry is a root complex integrated end point (RCiEP) circuitry.” (Baker [0018], [0021], teaching a master or root router 10R having an upstream-facing PCIe port that communicates with the host computer, functioning as the root complex/endpoint for the routing fabric).
Regarding Claim 6: Hundal in view of Baker teaches the circuit board of claim 1. Baker further teaches “wherein the decoding circuitry is included in a System on Chip (SoC).” (Baker [0035], teaching the majority of the electronic components of the router are implemented in an integrated circuit or semiconductor chip).
Regarding Claim 7: Hundal in view of Baker teaches the circuit board of claim 1. Hundal further teaches “wherein the decoding circuitry is included in a USB sub-system.” (Hundal [0037], teaching the switching device logic may be embedded within the USB host or hub 408).
Regarding Claim 8: Hundal in view of Baker teaches the circuit board of claim 1. Baker further teaches “wherein the decoding circuitry is included in an integrated graphics.” (Baker [0088], teaching an internal GPU that is integrated with the system logic chipset, such as the North Bridge chip).
Regarding Claim 9: Hundal in view of Baker teaches the circuit board of claim 1. Hundal further teaches “further including a system to support display over the USB connector.” (Hundal [0005], teaching a system for communicating USB and DisplayPort information via a USB Type-C receptacle).
Regarding Claim 10: Hundal in view of Baker teaches the circuit board of claim 1. Baker further teaches “wherein the circuit board includes a motherboard.” (Baker [0089], teaching the router is implemented as an integrated circuit chip on the computer’s motherboard).
Regarding Claim 11: Hundal teaches an electronic device with a circuit board and USB output, specifically teaching:
“An electronic device comprising:” (Hundal [0005], teaching a computing device).
“a circuit board” (Hundal [0037], [0041], teaching a printed circuit board assembly).
“a USB connector to output the display port stream data.” (Hundal [0005], [0031], teaching a USB Type-C receptacle outputting DisplayPort lanes).
However, Hundal does not explicitly teach “a discrete graphics card to encode display port stream data into PC~e data packets; and” nor does Hundal teach “a circuit board coupled to the discrete graphics card, the circuit board including: circuitry to decode the PC~e data packets into a display port stream data;”. (Note: “PC~e” is reproduced exactly as claimed).
Baker teaches the limitations not taught by Hundal. Specifically, Baker teaches:
“a discrete graphics card to encode display port stream data into PC~e data packets; and” (Baker [0088], teaching a separate GPU unit communicating via PCIe Graphics; and Baker [0043], teaching a DP decoder/encoder 90 that packages the representation into PCIe Vendor Defined Messages).
“a circuit board coupled to the discrete graphics card, the circuit board including: circuitry to decode the PC~e data packets into a display port stream data;” (Baker [0051], teaching the encoding portion of DP decoder/encoder 90 which decodes the VDMs and encodes the data into the desired DisplayPort stream; and Baker [0089], teaching the integrated circuit/motherboard coupled to the GPU).
Before the effective filling date of the claimed inventions. It would have been obvious to modify the electronic device of Hundal to employ the discrete graphics card encoding and PCIe decoding circuitry of Baker. The motivation would be to allow the electronic device to seamlessly transport display data over an internal, packet-based PCIe architecture to overcome internal bandwidth limitations before outputting the reconstructed display stream using a standardized USB interface.
Regarding Claim 12: Hundal in view of Baker teaches the electronic device of claim 11. Baker further teaches “wherein the circuitry includes a System on Chip (SoC) with a USB sub-system.” (Baker [0035], [0038], teaching the router components are implemented in a semiconductor chip/integrated circuit and includes a USB controller 70).
Regarding Claim 13: Hundal in view of Baker teaches the electronic device of claim 11. Baker further teaches “further including a housing, wherein there is no cabling external to the housing to couple the discrete graphics card to a USB sub-system.” (Baker [0087]-[0088], teaching a laptop computer housing containing the internal GPU and I/O controller hub).
Regarding Claim 14: Hundal in view of Baker teaches the electronic device of claim 11. Baker further teaches “wherein the circuitry includes a decoding circuitry.” (Baker [0043], [0051], teaching a DP decoder/encoder 90).
Regarding Claim 15: Hundal in view of Baker teaches the electronic device of claim 14. Baker further teaches “wherein the decoding circuitry is a root complex integrated end point (RCiEP) circuitry.” (Baker [0018], [0021], teaching a master or root router 10R communicating with the host computer).
Regarding Claim 16: Hundal in view of Baker teaches the electronic device of claim 11. Hundal further teaches “further including a hardware interface to support display port stream data over the USB connector.” (Hundal [0030], teaching a switching device 306 and USB Type-C receptacle 308 configured to route DisplayPort lanes).
Regarding Claim 17: Hundal teaches a graphics processing system on a board, specifically teaching:
“a circuit board; and” (Hundal [0037], [0041], teaching a printed circuit board assembly).
However, Hundal does not explicitly teach “A discrete graphics card comprising:” and does not teach “a display port adapter to encode a display port stream data as Peripheral Component Interconnect Express (PCIe) data packets.”
Baker teaches:
“A discrete graphics card comprising:” (Baker [0088], teaching a separate graphics processing unit (GPU) communicating via PCIe Graphics).
“a display port adapter to encode a display port stream data as Peripheral Component Interconnect Express (PCIe) data packets.” (Baker [0043], teaching a DP decoder/encoder 90 that decodes the DP stream, creates a logical representation, and packages the representation into PCIe Vendor Defined Messages (VDMs)).
Before the effective filling date of the claimed inventions. It would have been obvious to implement the graphics processing system of Hundal as a discrete graphics card utilizing the specific display port PCIe encoding adapter taught by Baker. The motivation would be to utilize a standardized PCIe-based packet protocol to tunnel high-speed display streams across internal system buses, allowing multiple native I/O formats to be handled by a single unified routing fabric (as explicitly motivated by Baker in [0006]).
Regarding Claim 18: Hundal in view of Baker teaches the discrete graphics card of claim 17. Baker further teaches “wherein the discrete graphics card is in a housing, and there is no cabling external to the housing to couple the discrete graphics card to a USB sub-system.” (Baker [0087]-[0088], teaching a laptop computer housing containing the GPU and I/O controller hub internally).
Motivation to Combine (Claims 2-10, 12-16, 18): It would have been obvious to a person of ordinary skill in the art to incorporate the specific housing, motherboard, SoC integration, and internal routing features taught by Baker and Hundal into the base systems of claims 1, 11, and 17. The motivation to do so is to provide a highly integrated, compact computing device (such as a laptop or tablet) where internal components communicate efficiently over an internal PCIe fabric without the need for external cabling, ultimately outputting a converged signal to a standardized external USB connector (as motivated by Baker [0004] and Hundal [0030]).
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Schnell (US 20180068412)
Schnell discloses a computing system comprising a CPU, a GPU, and an external port (USB Type-C). Schnell teaches that the GPU can selectively function as a switch to forward PCIe packets to a remote GPU via the USB Type-C port. Under the Broadest Reasonable Interpretation (BRI), the “interface circuitry” (202a/250a) in Schnell that converts between DisplayPort and PCIe modes is interpreted as “decoding circuitry” capable of translating data between protocols.
Pappu (US 20180285305)
Pappu discloses an interconnect architecture for a system comprising a plurality of protocol adapters (530, 532, 540) coupled to a switch fabric (550). Pappu teaches that these adapters support conversion between various protocols, including PCIe, DisplayPort, and Thunderbolt (Pappu, para 50). Pappu further discloses that such an architecture is implemented on a circuit board or integrated circuit (IC) substrate. Under the Broadest Reasonable Interpretation (BRI), the “protocol adapter” of Pappu is interpreted as “decoding circuitry” configured to convert data from a first protocol (PCIe) to a second protocol (DisplayPort) and to output the same via a physical interface, such as a USB connector, which is a known physical layer for these protocols.
Raval (US 2023/0214346).
Raval teaches the dynamic allocation of PCIe streams and the management of session-based data in a multiport controller. Raval further teaches that a PCIe controller can be configured to manage a pool of streams for different devices, utilizing configuration spaces (112) to manage operational parameters and protocol versions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tim Vo whose telephone number is (571)272-3642. The examiner can normally be reached on Monday-Thursday 5:30 AM – 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached on (571)272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
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/TIM T VO/Supervisory Patent Examiner, Art Unit 2138
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