DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the application filed 06/30/2023. Claims 1-20 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted 06/30/2023 has been considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 8-10, 14-16, 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1
Step 1: The claim recites “A system, comprising”; therefore, it is directed to the statutory category of a machine.
Step 2A Prong 1: The claim recites, inter alia:
processes an input temporal sequence at respective time steps to an output temporal sequence, wherein the machine learning component comprises: stack layers comprising direct connections in time and in space and also skip connections in time and in space: These limitations recite a mathematical relationship of processing and outputting an input temporal sequence at respective time steps, using a machine learning component comprising stack layers with direct and skip connections in time and space similar to a mathematical relationship between enhanced directional radio activity and antenna conductor arrangement per MPEP 2106.04(a)(2)(A)(iii). Thus, the claim recites a judicial exception.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The additional elements of the claim are as follows:
A system, comprising: a memory that stores computer executable components: These additional elements are recited at a high level of generality and amount to invoking computers or other machinery merely as a tool to apply the underlying judicial exception. See MPEP § 2106.05(f).
a processor that executes the computer executable components stored in the memory: These additional elements are recited at a high level of generality and amount to invoking computers or other machinery merely as a tool to apply the underlying judicial exception. See MPEP § 2106.05(f).
wherein the computer executable components comprise: a machine learning component that: These additional elements are recited at a high level of generality and amount to invoking computers or other machinery merely as a tool to apply the underlying judicial exception. See MPEP § 2106.05(f).
Thus, the way in which the additional elements use or interact with the judicial exception do not integrate the judicial exception into a practical application.
Step 2B: The additional elements from Step 2A Prong 2 include invoking generic computer components to apply the underlying judicial exception. Thus, the additional elements, viewed individually or in combination, do not provide an inventive concept or otherwise amount to significantly more than the abstract idea itself. See MPEP § 2106.05.
Claim 2
Step 1: A machine, as above.
Step 2A Prong 1: The claim recites the abstract ideas as the judicial exception of claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The additional elements of the claim are as follows:
wherein a hidden state within a first stack layer has a time connection to another hidden state within the first stack layer: These additional elements are recited at a high level of generality and merely indicate a field of use or technological environment in which to apply a judicial exception, e.g. stack layers comprising direct connections in time, to a particular technological environment or field of use, e.g. wherein a hidden state within the first stack layer has a time connection to another hidden state within the first stack layer. See MPEP 2106.05(h). Thus, the way in which the additional elements use or interact with the judicial exception do not integrate the judicial exception into a practical application.
Step 2B: The additional elements from Step 2A Prong 2 include generally link the use of the judicial exception to indicate a field of use or technological environment. Thus, the additional elements, viewed individually or in combination, do not provide an inventive concept or otherwise amount to significantly more than the abstract idea itself. See MPEP 2106.05.
Claim 3
Step 1: A machine, as above.
Step 2A Prong 1: The claim recites the abstract ideas as the judicial exception of claim 2.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The additional elements of the claim are as follows:
wherein the first stack layer has a space connection to a preceding stack layer: These additional elements are recited at a high level of generality and merely indicate a field of use or technological environment in which to apply a judicial exception, e.g. stack layers comprising direct connections in space, to a particular technological environment or field of use, e.g. wherein the first stack layer has a space connection to a preceding stack layer. See MPEP 2106.05(h). Thus, the way in which the additional elements use or interact with the judicial exception do not integrate the judicial exception into a practical application.
Step 2B: The additional elements from Step 2A Prong 2 include generally link the use of the judicial exception to indicate a field of use or technological environment. Thus, the additional elements, viewed individually or in combination, do not provide an inventive concept or otherwise amount to significantly more than the abstract idea itself. See MPEP 2106.05.
Claim 4
Step 1: A machine, as above.
Step 2A Prong 1: The claim recites the abstract ideas as the judicial exception of claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The additional elements of the claim are as follows:
wherein the input temporal sequence comprises an input for the respective time steps: These additional elements are recited at a high level of generality and merely indicate a field of use or technological environment in which to apply a judicial exception, e.g. processing an input temporal sequence at respective time steps, to a particular technological environment or field of use, e.g. wherein the input temporal sequence comprises an input for the respective time steps. See MPEP 2106.05(h). Thus, the way in which the additional elements use or interact with the judicial exception do not integrate the judicial exception into a practical application.
Step 2B: The additional elements from Step 2A Prong 2 include generally link the use of the judicial exception to indicate a field of use or technological environment. Thus, the additional elements, viewed individually or in combination, do not provide an inventive concept or otherwise amount to significantly more than the abstract idea itself. See MPEP 2106.05.
Claim 8-10
Step 1: These claims are directed to “A computer-implemented method comprising:”; therefore, it is directed the statutory category of a process.
Step 2A Prong 1: Claims 8-10 recite the same judicial exception as Claims 1-3, respectively.
Step 2A Prong 2: The judicial exception recited in these claims are not integrated into a practical application. The analysis at this step for Claims and 8-10 mirrors that of Claims 1-3, respectively.
Step 2B: The additional elements from Step 2A Prong 2 do not contain significantly more than the judicial exception for these claims. The analysis at this step for Claims 8-10 mirrors that of Claims 1-3, respectively.
Claims 14-16 and 20
Step 1: These claims recite "A computer program product comprising a non-transitory computer readable medium having program instructions embodied therewith"; therefore, it is directed to the statutory category of an article of manufacture.
Step 2A Prong 1: Claims 14-16 and 20 recite the same judicial exception as Claims 1-4, respectively.
Step 2A Prong 2: The judicial exception recited in these claims are not integrated into a practical application. The only difference between Claims 14-16 & 20 and Claims 1-4, is that Claims 14-16 & 20 are directed to "A computer program product comprising a non-transitory computer readable medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to:”. However, mere recitation that a judicial exception is to be performed using generic computer equipment in their ordinary capacity, i.e. a computer program product comprising a non-transitory computer readable medium having program instructions embodied therewith wherein the program instructions are executable by a processor to cause the processor to, cannot meaningfully integrate the judicial exception into a practical application. See MPEP 2106.05(f). With that exception, the analysis at this step for Claims 14-16 & 20 mirrors that of Claims1-4, respectively.
Step 2B: The additional elements from Step 2A Prong 2 do not contain significantly more than the judicial exception for these claims. The only difference between Claims 14-16 & 20 and Claims 1-14, is that Claims 14-16 & 20 are directed to "A computer program product comprising a non-transitory computer readable medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to:”. However, mere recitation that a judicial exception is to be performed using generic computer equipment in their ordinary capacity, i.e. a computer program product comprising a non-transitory computer readable medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method, cannot amount to significantly more than the judicial exception. See MPEP 2106.05(f). With that exception, the analysis at this step for Claims 14-16 & 20 mirrors that of Claims 1-4, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Graves ("Generating Sequences With Recurrent Neural Networks", Department of Computer Science, University of Toronto, arXiv, 2014) hereafter Graves, in view of Chang et al. ("Dilated Recurrent Neural Networks", 31st Conference on Neural Information Processing Systems, arXiv, 2017) hereafter Chang and in view of Sharma et al. (US 2023/0252285 A1) hereafter Sharma.
Regarding claim 1, Graves teaches a system comprising: a machine learning component that receives and processes an input (FIG. 1, [Chapter 2, Pg. 3] discuss a neural network prediction architecture that takes an input vector sequence; thus, the system inherently uses of a machine learning component to process the input into the neural network graph); stack layers comprising direct connections in time and in space (FIG. 1, [Ch. 5.1, Pg. 26] shows the neural network architecture in which the arrows point to direct connections in both time and in space and each hidden layer is stacked on top of each other); skip connections in space (FIG. 1, 12, [Ch. 5.1, Pg. 26] discuss hidden layers stacked on top of each other with skip connections between layers, which is effectively, skip connections in space).
Graves does not expressly teach a memory that stores computer executable components; a processor that executes the computer executable components stored in the memory; a machine learning component that processes an input temporal sequence at respective time steps to an output temporal sequence; skip connections in time.
However, in the same field of endeavor, Chang teaches skip connections in time (Chang FIG. 1, 2, [CH. 1, Pg. 1-2] discuss skip connections across different time inputs, pointed out by the arrows in figures 1 and 2).
Because Graves teaches a machine learning component that receives and processes an input, stack layers comprising direct connections in time and space, and skip connections in space, and Chang teaches skip connections in time, accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate skip connections in time taught by Chang into Graves’ system, with a reasonable expectation of success, to teach a machine learning component that processes an input; wherein the machine learning component comprises: stack layers comprising direct connections in time and in space and also skip connections in time and in space. This combination would have been motivated by the desire to alleviate gradient problems and extend the range of temporal dependencies [Chang Pg. 2].
The combination of Graves and Chang does not expressly teach a memory that stores computer executable components; a processor that executes the computer executable components stored in the memory; a machine learning component that processes an input temporal sequence at respective time steps to an output temporal sequence.
However, in the same field of endeavor, Sharma teaches a system comprising a memory (Sharma [0003] discusses memory that stores instructions that are executable by the processor), processor (Sharma [0003] discusses a processor that executes the components stored in memory) and a machine learning component to process an input temporal sequence at respective time steps to an output temporal sequence (Sharma [0003] discusses the neural network receiving run-time input data that includes time series data indicating a state of a graph network at each of a series of time steps, and further outputs that sequence).
Because the combination of Graves and Chang teaches a machine learning component that receives and processes an input, stack layers comprising direct connections in time and space, and skip connections in time and space, and Sharma teaches a memory, processor, and a machine learning component to process an input temporal sequence at respective time steps, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a memory, processor, and machine learning component to process an input temporal sequence at respective time steps as taught by Sharma into the combination of Graves and Chang’s system, with a reasonable expectation of success, to teach a memory that stores computer executable components; a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise: a machine learning component that processes an input temporal sequence at respective time steps to an output temporal sequence, wherein the machine learning component comprises: stack layers comprising direct connections in time and in space and also skip connections in time and in space. This combination would have been motivated by the desire to receive run-time data at each input’s respective time steps using a processor and memory to store instructions [Sharma 0003, 0022].
Regarding dependent claim 2, the combination of Graves, Chang, and Sharma teaches the claimed invention as claimed in claim 2 including a hidden state within a first stack layer has a time connection to another hidden state within the first stack layer (Graves, [FIG. 1, & Pg. 3] teaches an input being passed through weighted connections to a stack of N recurrently connected hidden layers and the arrows in FIG. 1 show a direct connection within each layer, demonstrating a time connection).
Regarding dependent claim 3, the combination of Graves, Chang, and Sharma teaches the claimed invention as claimed in claim 3 including the first stack layer has a space connection to a preceding stack layer (Graves, [FIG. 1, & Pg. 3] teaches an input being passed through weighted connections to a stack of N recurrently connected hidden layers and the arrows in FIG. 1 show a direct connection between each layer, demonstrating a space connection).
Regarding dependent claim 4, the combination of Graves, Chang, and Sharma teaches the claimed invention as claimed in claim 4 including the input temporal sequence comprises an input for the respective time steps (Sharma, [0022] discusses receiving a temporal input sequence containing time series data indicating a state at each respective time step).
Regarding dependent claim 5, the combination of Graves, Chang, and Sharma teaches the claimed invention as claimed in claim 5 including the plurality of stack layers are configured for each time step to: receive input xt at the time step (Graves, [CH. 2, Pg. 3] discusses an input sequence x = (x1,…,xT)); process the input xt at the time step by computing a hidden state for the time step in a current layer from a second hidden state for the time step in a previous layer and a third hidden state for a previous time step in the current layer (Graves, [CH. 2, Pg. 3] discusses computing the hidden vector sequence hn = (hn1,…,hnT), within a layer); and output a first activation function for the input xt and the second hidden state and a second activation function for the input xt and the third hidden state (Graves, [CH. 2, Pg. 3] discusses output vector sequence y = (y1,…,yT) for each layer which operates as the activation function).
Regarding dependent claim 6, the combination of Graves, Chang, and Sharma teaches the claimed invention as claimed in claim 6 including the machine learning component is trained sequentially from an input layer (Graves, [CH. 2, Pg. 3] discusses output vector yt is used to parameterize a predictive distribution Pr(xt+1|yt) over the possible next inputs xt+1).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Graves, in view of Chang and Sharma, as applied to claims 5 above, and further in view of Liu et al. ("Learning Efficient Convolutional Networks through Network Slimming", Intel Labs China, arXiv, 2017) hereafter Liu.
Regarding dependent claim 7, the combination of Graves, Chang, and Sharma teaches the use of an activation function (Graves, [CH. 2, Pg. 3] discusses output vector sequence y = (y1,…,yT) for each layer which operates as the activation function).
The combination of Graves, Chang and Sharma does not expressly teach a sparse regularizer is applied to parameters in an activation function utilized in training.
However, in the same field of endeavor, Liu teaches the use of a sparse regularizer (Liu, [Sec. 3, Pg. 3] discusses sparsity-induced penalty, where a neural network is trained using network weights and scaling factors to compute the normal training loss of a neural network).
Because the combination of Graves, Chang, and Sharma teaches the use of an activation function, and Liu teaches a sparse regularizer being used on a neural network for training, accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of using a sparse regularizer to train the activation function and neural network as taught by Liu into the combination of Graves, Chang, and Sharma’s system, with a reasonable expectation of success, to teach a sparse regularizer is applied to parameters in an activation function utilized in training. This combination would have been motivated by the desire to address issues with large neural network model sizes, run-time memories of neural networks, and number of computing operations that are high-intensive (Liu [Introduction, Pg. 1]).
Claims 8-12, 14-18, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Graves ("Generating Sequences With Recurrent Neural Networks", Department of Computer Science, University of Toronto, arXiv, 2014) hereafter Graves, in view of Sharma et al. (US 2023/0252285 A1) hereafter Sharma.
Regarding claim 8, Graves teaches a system comprising: a machine learning model that receives and processes an input (FIG. 1, [Chapter 2, Pg. 3] discuss a neural network prediction architecture that takes an input vector sequence; thus, the system inherently uses of a machine learning component to process the input into the neural network graph); the machine learning model comprises a plurality of direct connections between a plurality of stack layers in time and space directions (FIG. 1, [Ch. 5.1, Pg. 26] shows the neural network architecture in which the arrows point to direct connections in both time and in space and each hidden layer is stacked on top of each other).
Graves does not expressly teach receiving, by a computer, an input temporal sequence; and processing, by the computer, utilizing a machine learning model, the input temporal sequence at respective time steps to an output temporal sequence.
However, in the same field of endeavor, Sharma teaches a computer-implemented method comprising receiving and processing an input temporal sequence at respective time steps to an output temporal sequence utilizing a machine learning model (Sharma [0003] discusses the neural network receiving run-time input data that includes time series data indicating a state of a graph network at each of a series of time steps, and further outputs that sequence, and [0022] further details processing the input temporal sequence into a neural network graph).
Because Graves teaches a machine learning component that receives and processes input, and a plurality of stack layers comprising direct connections in time and space and Sharma teaches a computer-implemented method comprising receiving and processing an input temporal sequence at respective time steps to an output temporal sequence utilizing a machine learning model, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the specific machine learning methods of receiving and processing an input temporal sequence at respective time steps to an output temporal sequence and as taught by Sharma into Graves’ system, with a reasonable expectation of success, to teach a method comprising: receiving, by a computer, an input temporal sequence; and processing, by the computer, utilizing a machine learning model, the input temporal sequence at respective time steps to an output temporal sequence, wherein the machine learning model comprises a plurality of direct connections between a plurality of stack layers in time and space directions. This combination would have been motivated by the desire to forecast, predict, or analyze how each time step input relates to or affects one another within real world or larger datasets [Sharma 0002].
Regarding dependent claim 9, the combination of Graves and Sharma teaches the claimed invention as claimed in claim 9 including a hidden state within a first stack layer has a time connection to another hidden state within the first stack layer (Graves, [FIG. 1, & Pg. 3] teaches an input being passed through weighted connections to a stack of N recurrently connected hidden layers and the arrows in FIG. 1 show a direct connection within each layer, demonstrating a time connection).
Regarding dependent claim 10, the combination of Graves and Sharma teaches the claimed invention as claimed in claim 10 including the first stack layer has a space connection to a preceding stack layer (Graves, [FIG. 1, & Pg. 3] teaches an input being passed through weighted connections to a stack of N recurrently connected hidden layers and the arrows in FIG. 1 show a direct connection between each layer, demonstrating a space connection).
Regarding dependent claim 11, the combination of Graves and Sharma teaches the claimed invention as claimed in claim 11 including receiving, by the system, input xt at a time step (Graves, [CH. 2, Pg. 3] discusses an input sequence x = (x1,…,xT)); processing, by the system, the input xt at the time step by computing a hidden state for the time step in a current layer from a second hidden state for the time step in a previous layer and a third hidden state for a previous time step in the current layer (Graves, [CH. 2, Pg. 3] discusses computing the hidden vector sequence hn = (hn1,…,hnT), within a layer); outputting, by the system, a first activation function for the input xt and the second hidden state and a second activation function for the input xt and the third hidden state (Graves, [CH. 2, Pg. 3] discusses output vector sequence y = (y1,…,yT) for each layer which operates as the activation function).
Regarding dependent claim 12, the combination of Graves and Sharma teaches the claimed invention as claimed in claim 12 including training, by the system, the machine learning model sequentially from an input layer (Graves, [CH. 2, Pg. 3] discusses output vector yt is used to parameterize a predictive distribution Pr(xt+1|yt) over the possible next inputs xt+1).
Regarding dependent claims 14, 15, 16, 17, and 18, claims 14, 15, 16, 17, and 18 are non-transitory computer-readable medium claims that are substantially the same as the method of claims 8, 9, 10, 11, and 12, respectively. Therefore, claims 14, 15, 16, 17, and 18 are rejected for the same reasons as claims 8, 9, 10, 11, and 12.
Regarding dependent claim 20, the combination of Graves and Sharma teaches the claimed invention as claimed in claim 20 including the input temporal sequence comprises an input for the respective time steps (Sharma, [0022] discusses receiving a temporal input sequence containing time series data indicating a state at each respective time step).
Claims 13 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Graves, in view of Sharma, as applied to claims 12 & 18 above, and further in view of Liu et al. ("Learning Efficient Convolutional Networks through Network Slimming", Intel Labs China, arXiv, 2017) hereafter Liu.
Regarding dependent claim 13, the combination of Graves and Sharma teaches the use of an activation function (Graves, [CH. 2, Pg. 3] discusses output vector sequence y = (y1,…,yT) for each layer which operates as the activation function).
The combination of Graves and Sharma does not expressly teach a sparse regularizer is applied to parameters in an activation function utilized in training.
However, in the same field of endeavor, Liu teaches the use of a sparse regularizer (Liu, [Sec. 3, Pg. 3] discusses sparsity-induced penalty, where a neural network is trained using network weights and scaling factors to compute the normal training loss of a neural network).
Because the combination of Graves and Sharma teaches the use of an activation function, and Liu teaches a sparse regularizer being used on a neural network for training, accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of using a sparse regularizer to train the activation function and neural network as taught by Liu into the combination of Graves and Sharma’s system, with a reasonable expectation of success, to teach a sparse regularizer is applied to parameters in an activation function utilized in training. This combination would have been motivated by the desire to address issues with large neural network model sizes, run-time memories of neural networks, and number of computing operations that are high-intensive (Liu [Introduction, Pg. 1]).
Regarding dependent claim 19, claim 19 is a non-transitory computer-readable medium claim that is substantially the same as the method of claim 13. Therefore, claim 19 is rejected for the same reasons as claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hawkins et al. US 2014/0114896 A1 (April 24, 2014) ([0002] Embodiments relate to making predictions using spatial patterns and temporal sequences learned by a spatial and temporal memory system, and more specifically to making predictions for values, states or distribution of values to follow multiple time steps after a current time using the spatial and temporal memory system).
Mao et al. CN 114626607 A (June 14, 2022) (ABSTRACT The invention relates to a traffic flow prediction on time space map wavelet convolutional neural network module Including: S1, traffic flow data pre-process; S2, establishing traffic flow prediction model; S3, traffic flow prediction model training and parameter optimization).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RILEY S ACOSTA whose telephone number is (571)272-8714. The examiner can normally be reached Monday-Thursday 6am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer N Welch can be reached at (571)272-7212. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RILEY S ACOSTA/Examiner, Art Unit 2143
/JENNIFER N WELCH/Supervisory Patent Examiner, Art Unit 2143
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