Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Rejections under 35 U.S.C. §103
Applicant's arguments filed 1/12/26 have been fully considered but they are not persuasive.
Initially it is noted that the rejection addresses the limitation(s) in question as obvious in view of Alvanos. Accordingly, the applicant’s description of Matsuoka and Tal is immaterial and thus will not be directly addressed here.
Finally, Alvanos does not describe replacing the loop variable with a collection of variables corresponding to an object followed by a chosen variable for each attribute access. Instead, Alvanos describes an optimization where remote data is pre-fetched into local buffers (arrays) and then accessed via indices. "The dereference runtime call receives the address and size of the shared reference, returns the address of the local data buffer used by the runtime to prefetch the shared reference, and stores the appropriate buffer index into a local variable." Alvanos at [0081]. "Each shared reference can accordingly be replaced with a local access by using the buffer and the buffer index." Alvanos at [0081]. "The compiler searches through statements of the inner main loop and epilogue loop to replace the shared access with a local access in the buffer returned by the runtime call of dereference." Alvanos at [0081]. (emphasis added)
The applicant has not explicitly asserted a distinction over Alvanos, instead merely juxtaposing specific passages without further discussion. Here the examiner understands Alvanos’ buffers/arrays to fall within a reasonably broad understanding of the claimed “object of the loop variable” and their “index” to fall within a reasonably broad understanding of the claimed variable. More specifically, Alanos’ buffer/array would have been considered an “object” in the prior art and is generated, at least partially, with regard to the loop variable, and is thus reasonably considered an “object of the loop variable” as claimed. Whereas their “index” identifies an individual stored value and thus would have reasonably been construed as a ”variable” (note e.g. the claim does not explicitly require a variable “name”). Accordingly, at least without more, the claims do not appear to distinguish over the cited references and the claim(s) remain rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-8, 10-15, and 17-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “replacing the loop variable with a collection of variables corresponding to an object of the loop variable followed by a chosen variable for each of the attribute access”. Here the presented language does not make clear if the “chosen variable” requires the variable to be “chosen” from the “collection of variables” or some other variable found in the code or created specifically for this use. For the purposes of this examination the former understanding will be used.
Claims 3-7 depend from claim 1 and are rejected accordingly.
Claims 8 and 15 recite language similar to that of claim 1 and are thus similarly rejected.
Claims 10-14, and 17-21 depend from claim 1 and are rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-8, 11-15, and 17-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0017473 to Matsuoka et al. (Matsuoka) in view of US 2006/0048115 to Tal et al. (Tal) in view of US 2013/0167130 to Alvanos et al. (Alvanos).
Claims 1, 8 and 15: Matsuoka discloses a computer program product for optimizing attribute accesses, the computer program product being tangibly embodied on a non-transitory computer-readable storage medium and comprising instructions that, when executed by at least one computing device, are configured to cause the at least one computing device to:
receive a first data structure, the first data structure including a first sequence of statements representing programming functions having an input and an output (par. [0083] “retrieves the source code form the source file “ca””);
parse the first sequence of statements to collect attribute accesses defined in the first sequence of statements (par. [0083] “detects the structure or the array having the member targeted for access in the loop processing”, See e.g. Fig. 10, par. [0130] “reads one line of code from the source file “ca””);
transform the first data structure and the first sequence of statements defining the attribute accesses to a second data structure including a second sequence of statements representing the programming functions having the input and the output (par. [0084]-[0085] “inserts the first code declaring a pointer variable and the second code setting an address of the structure or the array … replaces a code accessing the member … with a code accessing the member based on the pointer variable”, also see fig. 5), wherein the first sequence of statements includes a loop expression defining a loop variable and the second sequence of statements defines a smaller number of the attribute accesses than the first sequence of statements (par. [0076] “reduce the number of times of the calculation processing of address “p1”-“p14” by moving the calculation process of the address “p1”-“p14” outside the third loop”);
output the second data structure (par. [0108] “The optimized source file”).
Matsuoka does not explicitly teach:
processing the second data structure by the at least one computing device, wherein the second data structure including the second sequence of statements generates a same output result as the first data structure using the smaller number of attribute accesses than the first data structure and the first sequence of statements.
Tal teaches:
processing the second data structure by the at least one computing device, wherein the second data structure including the second sequence of statements generates a same output result as the first data structure using the smaller number of attribu5te accesses than the first data structure and the first sequence of statements (par. [0123] “initializes temporary variables 1102 and inserts feeder statements 1104, 1106 and 1108”, par. [0125] “reducing the number of memory access required in a program loop”).
It would have been obvious at the time of filing to process the second data structure using a smaller number of attribute accesses. Those of ordinary skill in the art would have been motivated to do so to enhance performance (see e.g. Tal par. [0125]).
Matsuoka and Tal do not explicitly teach:
wherein transforming the first data structure includes:
replacing the loop expression with a bulk expression that performs and returns a bulk data retrieval for the attribute accesses in a single operation, and
replacing the loop variable with a collection of variables corresponding to an object of the loop variable followed by a chosen variable for each of the attribute access.
Alvanos teaches:
wherein transforming the first data structure includes:
replacing the loop expression with a bulk expression that performs and returns a bulk data retrieval for the attribute accesses in a single operation (par. [0087] “the coalesced entries … combine entries of a same identified pattern comprising remote accesses”, [0088] “calls the proper communication functions to start fetching the associated shared data of the coalesced entry”, par. [0094] “versions the loop into a set of loops, storing shared access associated information of the loop using a prologue loop … coalesces entries … using a single network communication”), and
replacing the loop variable with a collection of variables corresponding to an object of the loop variable followed by a chosen variable for each of the attribute access (par. [0081] “each shared reference can accordingly be replaced with a local access by using the buffer and the buffer index”)
It would have been obvious at the time of filing to replace the loop expression with a bulk expression and replace the loop variable with a collection of variables (Alvanos par. [0087] “the coalesced entries … combine entries of a same identified pattern comprising remote accesses”, par. [0081] “each shared reference can accordingly be replaced with a local access by using the buffer and the buffer index”). Those of ordinary skill in the art would have been motivated to do so as a known loop optimization which would have reduced network traffic and improved the execution of the loop.
Claims 3, 10 and 17: Matsuoka, Tal and Alvanos teach claims 1, 8 and 15, wherein:
the loop expression includes a loop body (e.g. Matsuoka Fig. 1, lp1, lp2, lp3); and
the instructions, when executed, are further configured to cause the at least one computing device to:
recursively replace all the attribute accesses in the loop body with values from the bulk data retrieval (Matsuoka par. [0085] “replaces a code accessing the member … with a code accessing the member based on the pointer variable”, Alvanos par. [0094] “entries of the reduced data structure”).
Claims 4, 11 and 18: Matsuoka, Tal and Alvanos teach claims 1, 8 and 15, wherein the instructions, when executed, are further configured to cause the at least one computing device to:
parse the first sequence of statements by traversing the first sequence of statements in a first pass (e.g. Fig. 10, “Read one Line form Source File” S31, S36);
record information for the attribute accesses in a memory during the first pass (Fig. 10 “write Detected code in loop statement detection table”, S34, “write code in loop statement detection table”); and
transform the first data structure and the first sequence of statements by traversing the first sequence of statements in a second pass using the information for the attribute accesses recorded in the memory (e.g. Fig. 16, “Replace code accessing to member in loop processing with code accessing based on pointer variable”, S104).
Claims 5, 12 and 19: Matsuoka, Tal and Alvanos teach claims 4, 11 and 18, wherein the information for the attribute accesses in the memory includes:
a first table comprising a first mapping from a variable name to a generation number for a variable corresponding to the variable name (e.g. Fig. 11, “Variable in the loop”, “No”); and
a second table comprising a second mapping from pairs of the variable name and the generation number to names of attributes read from the pairs (e.g. Fig. 16, “No”, “Loop Constitution”).
Claims 6, 13 and 20: Matsuoka, Tal and Alvanos teach claims 1, 8 and 15, wherein the attribute accesses include remote attribute accesses (Alvanos par. [0087] “the coalesced entries comprise remote accesses”).
Claims 7, 14 and 21: Matsuoka, Tal and Alvanos teach claims 1, 8 and 15, wherein the instructions, when executed, are further configured to cause the at least one computing device to parse the first sequence of statements, transform the first data structure, and output the second data structure without user intervention (e.g. Matsuoka par. [0072] “processing of compiler program”).
Conclusion
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/JASON D MITCHELL/Primary Examiner, Art Unit 2199