Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
Applicant's arguments filed 9/22/2025 have been fully considered but they are not persuasive.
Pages 7 and 8 of the Remarks argue that the office action does not demonstrate that the reference discloses the limitations of independent claim 1. However, the Remarks do not address any of the paragraphs cited in the NF rejection, and instead only repeat the Examiner’s statement from the rejection without addressing its teachings. The Applicant also cites paragraph 37 as support for the argument that Sodhi does not teach the limitation cited in the rejection. However, this paragraph and its specific teachings were neither cited by the Examiner or relied upon to teach the claim limitations in the NF rejection. Therefore, the arguments are not persuasive.
The Examiner maintains that Sodhi in view of Kakkireni teaches the limitations of claim 1, as detailed in the rejection.
Pages 8 and 9 generally argue that claim 17 is allowable for the same reasons as presented with respect to claim 1.
The Examiner maintains that Sodhi in view of Kakkireni and Branover teaches the limitations of claim 17, as detailed in the rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Sodhi, et al. U.S. PGPUB No. 2023/0059725 in view of Kakkireni et al. U.S. PGPUB No. 2022/0413593.
Per Claim 1, Sodhi discloses a device (integrated circuit assembly 100) comprising: a plurality of IC Die’s (IC dies 110A and 110B), wherein a first die of the plurality of dies is configured to: report, to a second die in response to receiving an indication of the device initiating entry of a low power state (Paragraph 20; transition request 125), locally reaching an idle state; and in response to receiving a confirmation of the idle state from the second die, locally complete the entry of the low power state (Paragraphs 34, 39, 41 and 43, Figures 3 and 4; When transitioning from memory state 330 to suspend state 340, PMGRs 230 and 235 may communicate over D2Dinterface 420 until a particular synchronization point 350 is reached, where a switch to communicating over GPIO interface 410 is made, which includes a GPIO synch acknowledgement that represents a confirmation of idle state and therefore local completion of low power state entry.).
Sodhi discloses that the dies are different (Paragraph 19), but does not refer to them as heterogenous or chiplets.
However, Kakkireni discloses a system-in-a package (104; similar to Sodhi’s integrated circuit assembly 100) and further teaches a plurality of chiplets (110a-d) that can be included as part of a heterogeneous processor cluster architecture (Paragraphs 44-46, Fig. 1).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit dies of Sodhi to be implemented in a heterogeneous processor (chiplet) cluster, as taught by Kakkireni, because Sodhi teaches that CPU 222 may include any suitable number of processor cores and the IC dies are shown to have different components (Sodhi, Paragraph 25, Fig. 2).
* * * * * * * *
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sodhi, et al. U.S. PGPUB No. 2023/0059725 in view of Kakkireni et al. U.S. PGPUB No. 2022/0413593, in further view of Branover et al. U.S. PGPUB No. 2019/0147926.
Per Claim 17, Sodhi discloses a method comprising: transitioning a plurality of IC dies to a new power state that corresponds to power gating idle dies of the plurality of dies (Paragraphs 23, 24 and 34, Figures 2 and 3; Certain sections of the dies (always-on sections) remain powered while other portions of the dies are transitioned to a suspend state 340.); confirming, while a client cie of the plurality of dies is kept at least partially powered on, the idle dies have completed operations for reaching an idle state; and in response to confirmations from the idle dies of the idle state, completing the transition to the new power state (Paragraphs 34, 39, 41 and 43, Figures 3 and 4; When transitioning from memory state 330 to suspend state 340, PMGRs 230 and 235 may communicate over D2Dinterface 420 until a particular synchronization point 350 is reached, where a switch to communicating over GPIO interface 410 is made, which includes a GPIO synch acknowledgement that represents a confirmation of idle state and therefore local completion of low power state entry.).
Sodhi discloses that the dies are different (Paragraph 19), but does not refer to them as heterogenous or chiplets.
However, Kakkireni discloses a system-in-a package (104; similar to Sodhi’s integrated circuit assembly 100) and further teaches a plurality of chiplets (110a-d) that can be included as part of a heterogeneous processor cluster architecture (Paragraphs 44-46, Fig. 1).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit dies of Sodhi to be implemented in a heterogeneous processor (chiplet) cluster, as taught by Kakkireni, because Sodhi teaches that CPU 222 may include any suitable number of processor cores and the IC dies are shown to have different components (Sodhi, Paragraph 25, Fig. 2).
Neither Sodhi nor Kakkireni specifically refer to the dies/chiplets as “stutter client chiplets”.
However, Branover, discloses power-gating stutter clients as a method of power management (Paragraph 14).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the integrated circuit dies of Sodhi and the chiplets of Kakkireni to be “stutter clients” as disclosed by Branover because dies/chiplets/clients that operate in a “bursty” or sporadic manner can be effectively power managed during their frequent periods of inactivity.
Allowable Subject Matter
Claims 10-16 are allowed.
Claims 2, 8, 9, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2, 8, 10, 18, and 20 distinguish over the prior art due to no combination of the prior art specifically teaching the nature of “locally reaching the idle state” claimed in said limitations, when considered in combination with the limitations of the interceding/independent claims. Per claim 9, no combination of the prior art teaches the heterogeneous aborting of entrance to the low power state as claimed.
Claims 3-7 and 19 inherit the allowable subject matter of Claims 2 and 18, respectively.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kim Huynh can be reached on (571) 272-4147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Brian T Misiura/
Primary Examiner, Art Unit 2175