Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the amendment and remarks filed on 12/16/2025.
Claims 1-20 are currently pending.
Claims 1-2 are currently amended.
Claims 1-10 are rejected.
Claims 11-20 are allowable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Stuart R. Soloway (US 20030165137 A1) in view of Benjamin Graniello et al (US 20200125503 A1) & Michael Florea et al (US 20170195259 A1).
For Claim 1, Soloway discloses a device (Soloway teaches, in ¶ 0010, lines 1-2, a method of routing a flow through a switch in a Fibre Channel fabric) comprising:
a plurality of mesh lanes (Soloway teaches, in ¶ 0030, lines 1-4, that FIG. 3, switch 300 has three candidate neighboring switches 303, 305 and 310 for establishing a path, shown as paths 301, 304 and 308 respectively); and a control circuit configured to:
receive a data packet (Soloway teaches, in ¶ 0029, lines 4-5, that a frame arrives on receive port 302 of switch 300 destined for a particular destination switch. The frame has a unique identifier or address that identifies a destination location); select a mesh lane of the plurality of mesh lanes based on an attribute of the data packet (Soloway teaches, in ¶ 0029, lines 6-11, that The frame has a unique identifier or address that identifies a destination location. Using the identity of the destination identifier, a protocol embodied on switch 300 determines one or more shortest paths to the destination);
and forward the data packet to the selected mesh lane (Soloway teaches, in ¶ 0056, lines 5-7, that More particularly, ISL 370 is chosen as the link on the shortest path between switch 300 and 310. Traffic is therefore routed on ISL 370).
Soloway fails to expressly disclose that the plurality of mesh lanes each corresponding to a memory channel interface.
However, Graniello, in the analogous art of path/route determination, discloses that the plurality of mesh lanes each corresponding to a memory channel interface (Graniello teaches, in ¶ 0062, lines 1-4, that compute node 800. Processor/SOC 802 includes a pair of memory controller 900 and 902, each including three memory channels 904 (also labeled Ch(annel) 1, Ch 2, and Ch 3). Graniello also teaches, in ¶ 0033, lines 12-14, that Under one embodiment one of more of memory channels 235 comprises an interconnect segment (link) with configurable lanes).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the invention taught in Soloway with the bandwidth prediction algorithm taught in Graniello. The motivation is to improve bandwidth utilizations of the interconnects for both local memory and remote memory implementations, leading to increased throughput [Graniello: ¶ 0074].
Soloway & Graniello fail to expressly disclose that the mesh lane is selected in response to identifying a destination of the received data packet as outside of the device.
However, Florea, in the analogous art of path/route determination, discloses that the mesh lane is selected, in response to identifying a destination of the received data packet as outside of the device (Florea teaches, in ¶ 0070, that After a packet is enqueued into the data queue, the ingress processor 221 reads the destination address of the packet. Based on the destination address, the ingress processor 221 determines the egress port to which the packet should be routed. Florea also teaches, in ¶ 0054, lines 7-10, that The chip-level router (L1) 102/142 routes packets destined for other chips or destinations through the external transmission ports 103 over one or more high-speed serial busses 105).
Florea also teaches, in ¶ 0219, lines 1-5, that The L1 routers 102 and 142 have been described in the context of device 100, where internal egress ports are used for routing to destinations within the device 100 and external egress ports are used for routing to destinations outside of the device 100.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the invention taught in Soloway & Graniello with the routing framework taught in Florea. The motivation is to allow execution-time optimization of the fabric to adapt to changing data flows [Florea: ¶ 0030, lines 18-20].
For Claim 2, Soloway discloses a device, wherein a source of the data packet is outside of the device and the destination of the data packet is outside of the device (Soloway teaches, in ¶ 0062, lines 8-10, that FIG. 6B differs from FIG. 6A in that switch 600 couples to switch 615 and switch 610 couples to switch 620 over one or more E-Ports. Thus, a packet coming from switch 615 will be a source outside of switch 600 and switch 610 will be a destination outside of switch 600).
For Claim 3, Soloway discloses a device, wherein the selected mesh lane is selected based on a bandwidth availability of the selected mesh lane (Soloway teaches, in ¶ 0047, lines 4-8, that The FSPF protocol may determine that the shortest path is identical between a first switch and two neighboring switches, and base the selection of the switch on the highest bandwidth link or any other arbitrary static criterion).
For Claim 4, Soloway discloses a device, further comprising: a plurality of ports; wherein the data packet was forwarded to a port of the plurality of ports based on an inter-device routing scheme (Soloway teaches, in ¶ 0038, lines 4-9, that five inter-switch links are illustrated having different data rates for transmitting traffic. As shown, ISL 330 and ISL 340 transmit traffic at a rate of 1 Gbps; ISL 350 and ISL 360 transmit at a rate of 2 Gbps; and ISL 370 transmits at a rate of 10 Gbps).
For Claim 5, Soloway discloses a device, wherein the data packet is forwarded along the mesh lane to a second port of the plurality of ports (Soloway teaches, in ¶ 0011, lines 4-6, that Embodied within the switch is a first protocol for selecting a second port to receive a frame from the first port).
For Claim 6, Soloway discloses a device, wherein at the second port an inter-device routing scheme is applied to the data packet (Soloway teaches, in ¶ 0023, lines 4-8, that switch 40 is coupled to a single switch 50 over a plurality of inter-switch links (ISLs) 45. Switch 50 is coupled to F-port 60 that couples fabric 10 to the destination device 80 through N-port 70).
For Claim 7, Soloway discloses a device, wherein a source of the received data packet is within the device (Soloway teaches, in ¶ 0011, lines 4-6, that Embodied within the switch is a first protocol for selecting a second port to receive a frame from the first port).
For Claim 9, Soloway discloses a device, wherein a destination of the data packet is within the device (Soloway teaches, in ¶ 0011, lines 4-6, that Embodied within the switch is a first protocol for selecting a second port to receive a frame from the first port).
Claims 8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Stuart R. Soloway (US 20030165137 A1) in view of Benjamin Graniello et al (US 20200125503 A1) & Michael Florea et al (US 20170195259 A1) as applied to claim 7 or 9 above, and further in view of KE-LIN Chen et al (CN 113783806 B).
For Claim 8, Soloway, Graniello and Florea disclose all of the claimed subject matter with the exception that the selected mesh lane is selected based on a closest mesh lane to the source.
However, Chen, in the analogous art of path/route determination, discloses that the selected mesh lane is selected based on a closest mesh lane to the source (Wu teaches, in Abstract, that selecting an output port closest to the target address of the data packet to be forwarded from the screened multiple output ports for forwarding the data packet to be forwarded to the target address).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Soloway and Graniello with the routing algorithm taught in Chen. The motivation is to ensure that the bandwidth is approximately uniformly distributed on the output ports [Chen: Abstract].
For Claim 10, Soloway, Graniello and Florea disclose all of the claimed subject matter with the exception that the selected mesh lane is selected based on a closest mesh lane to the destination.
However, Chen, in the analogous art of path/route determination, discloses that the selected mesh lane is selected based on a closest mesh lane to the destination (Wu teaches, in Abstract, that selecting an output port closest to the target address of the data packet to be forwarded from the screened multiple output ports for forwarding the data packet to be forwarded to the target address).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Soloway and Graniello with the routing algorithm taught in Chen. The motivation is to ensure that the bandwidth is approximately uniformly distributed on the output ports [Chen: Abstract].
Allowable Subject Matter
Claims 11-20 allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 11, 18 are considered allowable because the prior art does not teach limitations including:
“apply an inter-die routing scheme for data traffic outside the first die and the second die, and apply an intra-die routing scheme for data traffic within the first die or the second die,” in addition to other claim limitations as recited in independent claim 11.
“applying an intra-die routing scheme to select, based at least on the destination, a mesh lane of the die for sending the data packet across the die; and forwarding the data packet to the selected mesh lane using at least one routing element of the die,” in addition to other claim limitations as recited in independent claim 18.
Response to Arguments
Applicant's arguments filed on 12/16/2025 have been fully considered but they are not persuasive. Examiner will respond in the rebuttal that follows:
Claim Rejections under 35 U.S.C. § 103
Examiner respectfully disagrees with Applicant’s argument that the cited combination of references does not teach or suggest “"select, in response to identifying a destination of the received data packet as outside of the device, a mesh lane," as recited by claim 1.
For at least these reasons, claim 1 patentably distinguishes any combination of Soloway and Graniello. Withdrawal of the rejections under § 103 of claims 1 and of each claim that depends therefrom is respectfully requested,” (pages 8-9).
Examiner respectfully disagrees because Florea teaches, in ¶ 0070, that After a packet is enqueued into the data queue, the ingress processor 221 reads the destination address of the packet. Based on the destination address, the ingress processor 221 determines the egress port to which the packet should be routed. Florea also teaches, in ¶ 0054, lines 7-10, that The chip-level router (L1) 102/142 routes packets destined for other chips or destinations through the external transmission ports 103 over one or more high-speed serial busses 105).
Florea also teaches, in ¶ 0219, lines 1-5, that The L1 routers 102 and 142 have been described in the context of device 100, where internal egress ports are used for routing to destinations within the device 100 and external egress ports are used for routing to destinations outside of the device 100.
Clearly, it can be seen that Florea’s chip-level router (L1) 102/142 routes packets destined for other [external] chips after determining the egress port to which the packet should be routed based on the destination address information in the packet.
Therefore, Examiner respectfully submits that the combination of Soloway, Graniello, and Florea does disclose, suggest, or otherwise render obvious the limitations recited in Independent Claims 1.
Dependent claims 2-10 are not yet allowable for multiple reasons, including being rejected on their own merits, as well as for depending from rejected base claim 1.
For at least the above reasons, Examiner respectfully submits that the pending claims 1-10 are not yet allowable.
In light of the above rejection and rebuttal, the rejection of claims 1-10, in this office action, is hereby made final.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes: Maiyuran (US 20080151894 A1) is pertinent to An apparatus is described that routes packets to, from, and within a socket. The apparatus includes routing components that provide different functionality based upon which socket component they are connected to. One routing component is connected to an interface that communicates with the processor core of the socket.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED A KAMARA whose telephone number is (571)270-5629. The examiner can normally be reached M-F 9AM-4PM.
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/MOHAMED A KAMARA/Primary Examiner, Art Unit 2412